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Searched refs:UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h108 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK … macro
H A Dvcn_2_5_sh_mask.h1573 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK … macro
H A Dvcn_2_0_0_sh_mask.h1570 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3011 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2119 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK … macro
H A Dvcn_4_0_0_sh_mask.h6400 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK … macro
H A Dvcn_4_0_3_sh_mask.h7216 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v2_0.c1222 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; in vcn_v2_0_pause_dpg_mode()
1269 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; in vcn_v2_0_pause_dpg_mode()
H A Dvcn_v4_0.c1562 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; in vcn_v4_0_pause_dpg_mode()
1575 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; in vcn_v4_0_pause_dpg_mode()
H A Dvcn_v1_0.c1239 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; in vcn_v1_0_pause_dpg_mode()
1269 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; in vcn_v1_0_pause_dpg_mode()
H A Dvcn_v2_5.c1470 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; in vcn_v2_5_pause_dpg_mode()
1512 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; in vcn_v2_5_pause_dpg_mode()
H A Dvcn_v3_0.c1618 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; in vcn_v3_0_pause_dpg_mode()
1668 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; in vcn_v3_0_pause_dpg_mode()