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/openbmc/u-boot/doc/
H A DREADME.mpc85xx55 TLB Entry : 15
61 TLB Entry : 14
67 TLB Entry : 13
86 TLB entry : Search from TLB entries
106 TLB Entry : 15
117 TLB Entry : 14
123 TLB Entry : 13
129 TLB Entry : 9
135 TLB Entry : Get Flash TLB
160 TLB entry : Search free TLB entry
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H A DREADME.mpc85xx-spin-table10 is more than 4GB), and creates a TLB to map it to 0xffff_f000, regardless of
20 TLB. While booting, they set up another TLB in AS=1 space and jump into
21 the new space. The new TLB covers the physical address of the spin table page,
H A DREADME.N121321 - TLB
23 - 32/64/128-entry 4-way set-associati.ve main TLB.
24 - TLB locking support
/openbmc/linux/Documentation/translations/zh_CN/core-api/
H A Dcachetlb.rst17 Linux下的缓存和TLB刷新
24 本文描述了由Linux虚拟内存子系统调用的缓存/TLB刷新接口。它列举了每个接
34 首先是TLB刷新接口，因为它们是最简单的。在Linux下，TLB被抽象为cpu
36 表发生变化，这个“TLB”缓存中就有可能出现过时（脏）的翻译。因此，当软件页表
47 这个接口从TLB中刷新整个用户地址空间。在运行后，这个接口必须确保
49 运行后，TLB中不会有‘mm’的页表项。
57 这里我们要从TLB中刷新一个特定范围的（用户）虚拟地址转换。在运行后，
59 的任何页表修改对cpu来说是可见的。也就是说，在运行后，TLB中不会有
64 提供这个接口是希望端口能够找到一个合适的有效方法来从TLB中删除多
73 可执行的（因此在split-tlb类型的设置中可能在“指令TLB”中）。
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/openbmc/linux/Documentation/translations/zh_CN/mm/
H A Dmmu_notifier.rst17 对于二级TLB（非CPU TLB），如IOMMU TLB或设备TLB（当设备使用类似ATS/PASID的东西让
19 表锁的同时通知这些二级TLB：
47 DEV-thread-0 {读取addrA并填充设备TLB}
48 DEV-thread-2 {读取addrB并填充设备TLB}
92 所以在这里，因为在N+2的时候，清空页表项没有和通知一起作废二级TLB，设备在看到addrA的新值之前
H A Dhighmem.rst30 出付出全部的TLB作废代价。这意味着可用的虚拟内存空间（i386上为4GiB）必须在用户和内核空间之
46 其他有mm上下文标签的TLB的架构可以有独立的内核和用户映射。然而，一些硬件（如一些ARM）在使
102 映射变化必须广播到所有CPU（核）上，kmap()还需要在kmap的池被回绕（TLB项用光了，需要从第
103 一项复用）时进行全局TLB无效化，当映射空间被完全利用时，它可能会阻塞，直到有一个可用的
120 创建临时映射的代价可能相当高。体系架构必须操作内核的页表、数据TLB和/或MMU的寄存器。
138 * PAE使你的页表变大--这使系统变慢，因为更多的数据需要在TLB填充等方面被访问。一个好处
/openbmc/linux/Documentation/powerpc/
H A Dcpu_families.rst14 - Software loaded TLB (603 and e300)
15 - Selectable Software loaded TLB in addition to hash MMU (755, 7450, e600)
127 - Software loaded TLB.
185 - Software loaded TLB.
186 - e6500 adds HW loaded indirect TLB entries.
219 | e6500 (HW TLB) (Multithreaded) |
226 - Book3E, software loaded TLB + HW loaded indirect TLB entries.
/openbmc/linux/Documentation/arch/x86/
H A Dtlb.rst4 The TLB
10 1. Flush the entire TLB with a two-instruction sequence. This is
11 a quick operation, but it causes collateral damage: TLB entries
17 damage to other TLB entries.
23 entire TLB than doing 2^48/PAGE_SIZE individual flushes.
24 2. The contents of the TLB. If the TLB is empty, then there will
28 3. The size of the TLB. The larger the TLB, the more collateral
32 4. The microarchitecture. The TLB has become a multi-level
37 especially the contents of the TLB during a given flush. The
62 with the cycles that you spend refilling the TLB later.
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H A Dpti.rst91 feature of the MMU allows different processes to share TLB
93 TLB misses after a context switch. The actual loss of
96 allows us to skip flushing the entire TLB when switching page
101 and kernel entries out of the TLB. The user PCID TLB flush is
117 the entire TLB. That means that each syscall, interrupt
118 or exception flushes the TLB.
119 h. INVPCID is a TLB-flushing instruction which allows flushing
120 of TLB entries for non-current PCIDs. Some systems support
122 can only be flushed from the TLB for the current PCID. When
124 single kernel address flush will require a TLB-flushing CR3
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/openbmc/linux/Documentation/translations/zh_CN/arch/loongarch/
H A Dintroduction.rst133 0x88 TLB重填异常入口地址 TLBRENTRY
134 0x89 TLB重填异常出错(Faulting)虚地址 TLBRBADV
135 0x8A TLB重填异常返回地址 TLBRERA
136 0x8B TLB重填异常数据保存 TLBRSAVE
137 0x8C TLB重填异常表项低位0 TLBRELO0
138 0x8D TLB重填异常表项低位1 TLBRELO1
139 0x8E TLB重填异常表项高位 TLBEHI
140 0x8F TLB重填异常前模式信息 TLBRPRMD
267 分页映射的虚拟地址（VA）和物理地址（PA）有任意的映射关系，这种关系记录在TLB和页
268 表中。LoongArch的TLB包括一个全相联的MTLB（Multiple Page Size TLB，多样页大小TLB）
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/openbmc/linux/arch/arm/mm/
H A Dtlb-v7.S49 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
51 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
53 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
78 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
80 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
82 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
H A Dtlb-v6.S48 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
50 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
52 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
77 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
78 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
80 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
H A Dtlb-v4wb.S38 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB
41 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
61 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
62 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
H A Dtlb-v4wbi.S40 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
41 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
52 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
53 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
H A Dproc-arm720.S68 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
95 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
110 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
138 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
/openbmc/qemu/target/nios2/
H A Dtrace-events2 …2_t pid, uint32_t index, uint32_t tag) "mmu_translate: MISS vaddr=0x%08x pid=%u TLB[%u] tag=0x%08x"
3 …ex, uint32_t paddr, uint32_t prot) "mmu_translate: HIT vaddr=0x%08x pid=%u TLB[%u] paddr=0x%08x pr…
5 nios2_mmu_flush_pid_miss(uint32_t pid, uint32_t index, uint32_t vaddr) "mmu_flush: MISS pid=%u TLB[…
6 nios2_mmu_flush_pid_hit(uint32_t pid, uint32_t index, uint32_t vaddr) "mmu_flush: HIT pid=%u TLB[%u…
/openbmc/linux/Documentation/mm/
H A Dmmu_notifier.rst8 For secondary TLB (non CPU TLB) like IOMMU TLB or device TLB (when device use
11 those secondary TLB while holding page table lock when clearing a pte/pmd:
43 DEV-thread-0 {read addrA and populate device TLB}
44 DEV-thread-2 {read addrB and populate device TLB}
89 notification to invalidate the secondary TLB, the device see the new value for
/openbmc/linux/Documentation/translations/zh_CN/arch/arm64/
H A Dhugetlbpage.rst23 不管 TLB 中支持的条目大小如何，块映射可以减少翻译大页地址
31 个 TLB 条目中。
/openbmc/linux/Documentation/devicetree/bindings/nios2/
H A Dnios2.txt23 - altr,tlb-num-ways: Specifies the number of set-associativity ways in the TLB.
24 - altr,tlb-num-entries: Specifies the number of entries in the TLB.
25 - altr,tlb-ptr-sz: Specifies size of TLB pointer.
30 - altr,fast-tlb-miss-addr: Specifies CPU fast TLB miss exception address
/openbmc/linux/arch/arc/mm/
H A Dtlbex.S51 ; Since the Fast Path TLB Miss handler is coded with 4 regs, the remaining 3
54 ; [All of this dance is to avoid stack switching for each TLB Miss, since we
/openbmc/linux/Documentation/translations/zh_TW/arch/arm64/
H A Dhugetlbpage.rst26 不管 TLB 中支持的條目大小如何，塊映射可以減少翻譯大頁地址
34 個 TLB 條目中。
/openbmc/linux/Documentation/arch/loongarch/
H A Dintroduction.rst111 0x10 TLB Index TLBIDX
112 0x11 TLB Entry High-order Bits TLBEHI
113 0x12 TLB Entry Low-order Bits 0 TLBELO0
114 0x13 TLB Entry Low-order Bits 1 TLBELO1
142 0x89 TLB Refill Exception BAD (Faulting) TLBRBADV
144 0x8A TLB Refill Exception Return Address TLBRERA
145 0x8B TLB Refill Exception Saved Data TLBRSAVE
147 0x8C TLB Refill Exception Entry Low-order TLBRELO0
151 0x8E TLB Refill Exception Entry High-order TLBEHI
301 is recorded in TLB and page tables. LoongArch's TLB includes a fully-associative
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/openbmc/linux/Documentation/arch/arm/
H A Dinterrupts.rst10 MMU TLB. Each MMU TLB variant is now handled completely separately -
11 we have TLB v3, TLB v4 (without write buffer), TLB v4 (with write buffer),
12 and finally TLB v4 (with write buffer, with I TLB invalidate entry).
14 allow more flexible TLB handling for the future.
/openbmc/linux/arch/xtensa/
H A DKconfig.debug4 bool "Debug TLB sanity"
7 Enable this to turn on TLB sanity check on each entry to userspace.
8 This check can spot missing TLB invalidation/wrong PTE permissions/
/openbmc/linux/arch/parisc/
H A DKconfig.debug15 bool "Use page table locks in TLB fault handler"
19 Select this option to enable page table locking in the TLB

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