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Searched refs:TLB (Results 1 – 25 of 40) sorted by relevance

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/openbmc/u-boot/doc/
H A DREADME.mpc85xx12 immediately on entry and keeps it set. It also uses a temporary TLB to keep a
40 TLB Entries during u-boot execution
47 1) TLB entry to overcome e500 v1/v2 debug restriction
49 TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
53 2) TLB entry for working in AS1
55 TLB Entry : 15
59 3) TLB entry for the stack during AS1
61 TLB Entry : 14
65 4) TLB entry for CCSRBAR during AS1 execution
67 TLB Entry : 13
[all …]
H A DREADME.mpc85xx-spin-table10 is more than 4GB), and creates a TLB to map it to 0xffff_f000, regardless of
20 TLB. While booting, they set up another TLB in AS=1 space and jump into
21 the new space. The new TLB covers the physical address of the spin table page,
H A DREADME.N121321 - TLB
23 - 32/64/128-entry 4-way set-associati.ve main TLB.
24 - TLB locking support
H A DREADME.mips38 * Probe CPU types, I-/D-cache and TLB size etc. automatically
42 * Initialize TLB entries redardless of their use
H A DREADME.srio-pcie-boot-corenet74 i) Slave will set a specific TLB entry for the boot process.
77 k) Slave will set a specific TLB entry in order to fetch UCode and ENV
H A DREADME.ramboot-ppc85xx54 - setup DDR TLB
H A DREADME.arm-relocation178 TLB addr = XXXXXXXXXX
/openbmc/qemu/docs/system/openrisc/
H A Dcpu-features.rst8 - MMU TLB with 128 entries, 1 way
/openbmc/qemu/target/arm/tcg/
H A Dsve_ldst_internal.h50 #define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \ argument
54 TYPEM val = TLB(env, useronly_clean_ptr(addr), ra); \
58 #define DO_ST_TLB(NAME, H, TYPEE, TYPEM, TLB) \ argument
63 TLB(env, useronly_clean_ptr(addr), val, ra); \
/openbmc/qemu/docs/devel/
H A Dmulti-thread-tcg.rst177 handled with a per-vCPU TLB structure which once populated will allow
179 translated code. It is possible to set flags in the TLB address which
185 - Virtual TLB (for translating guest address->real address)
187 When the TLB tables are updated by a vCPU thread other than their own
196 - TLB Flush All/Page
198 - cross vCPU TLB flush may need other vCPU brought to halt
200 - TLB Flag Update
203 - TLB Update (update a CPUTLBEntry, via tlb_set_page_with_attrs)
214 TLB flag updates are all done atomically and are also protected by the
/openbmc/u-boot/arch/arc/
H A DKconfig87 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
/openbmc/qemu/docs/system/i386/
H A Dhyperv.rst108 Enables paravirtualized TLB shoot-down mechanism. On x86 architecture, remote
109 TLB flush procedure requires sending IPIs and waiting for other CPUs to perform
110 local TLB flush. In virtualized environment some virtual CPUs may not even be
113 implements TLB shoot-down through hypervisor enabling the optimization.
243 Allow for extended GVA ranges to be passed to Hyper-V TLB flush hypercalls
250 enabled, it allows L0 (KVM) to directly handle TLB flush hypercalls from L2
H A Dkvm-pv.rst61 Enable paravirtualized TLB flush mechanism. Supported since Linux v4.16.
/openbmc/libcper/specification/document/
H A Dcper-json-specification.tex419 % IA32/x64 Processor Error Check Info (Cache/TLB Error)
420 \subsection{IA32/x64 Processor Error Check Info (Cache/TLB Error) Structure}
422 …structure (\ref{subsection:ia32x64processorerrorinfostructure}) stemming from a cache or TLB error.
423 The GUIDs for cache and TLB error check info structures can be found in the library repository's \t…
425 validationBits & object & An IA32/x64 Processor Error Check Info (Cache/TLB/Bus) Validation structu…
427 transactionType.value & uint64 & The raw value of the type of cache/TLB error that occurred.\\
428 transactionType.name & string & The human readable name, if available, of the type of cache/TLB err…
430 operation.value & uint64 & The raw value of the type of cache/TLB operation that caused the error.\\
431 operation.name & string & The human readable name, if available, of the type of cache/TLB operation…
433 level & uint64 & The cache/TLB level at which the error occurred.\\
[all …]
/openbmc/u-boot/board/renesas/MigoR/
H A Dlowlevel_init.S35 ! TI == TLB Invalidate bit
/openbmc/u-boot/arch/nds32/cpu/n1213/
H A Dstart.S516 li $p1, 0x2 ! TLB MMU
518 tlbop flushall ! Flush TLB
/openbmc/qemu/target/ppc/translate/
H A Dmisc-impl.c.inc65 * We may need to check for a pending TLB flush.
H A Dstorage-ctrl-impl.c.inc229 * Global TLB flush uses async-work which must run before the
/openbmc/qemu/target/mips/
H A Dcpu-defs.c.inc398 /* This is the TLB-based MMU core. */
1043 /* MVPConf1 implemented, TLB shareable, no gating storage support,
1045 and shareable TLB entries, MVP has allocatable TCs, 2 VPEs
1055 /* Usermode has no TLB support */
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A DKconfig1490 int "Number of TLB CAM entries"
1494 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1510 int "Temporary TLB entry for external debugger"
1526 Select a temporary TLB entry to be used during boot to work
/openbmc/qemu/target/mips/tcg/
H A Dsystem_helper.h.inc162 /* TLB */
/openbmc/u-boot/arch/arm/cpu/armv8/
H A DKconfig25 cache and TLB maintenance operations.
/openbmc/u-boot/board/freescale/t4qds/
H A DREADME106 …0_0000_0000) - 0x0_7fff_ffff 2GB DDR (more than 2GB is initialized but not mapped under with TLB)
/openbmc/openbmc/poky/meta/classes-recipe/
H A Dqemuboot.bbclass115 # With 6.5+ (specifically, if DMA_BOUNCE_UNALIGNED_KMALLOC is set) the SW IO TLB
/openbmc/qemu/target/s390x/
H A Dcpu_features_def.h.inc26 DEF_FEAT(IDTE_SEGMENT, "idtes", STFL, 4, "IDTE selective TLB segment-table clearing")
27 DEF_FEAT(IDTE_REGION, "idter", STFL, 5, "IDTE selective TLB region-table clearing")
70 DEF_FEAT(LOCAL_TLB_CLEARING, "ltlbc", STFL, 51, "Local-TLB-clearing facility")

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