1afa6b551SPrabhakar KushwahaExternal Debug Support 2afa6b551SPrabhakar Kushwaha---------------------- 3afa6b551SPrabhakar Kushwaha 4afa6b551SPrabhakar KushwahaFreescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some 5afa6b551SPrabhakar Kushwaharestrictions on external debugging (JTAG). In particular, for the debugger to 6afa6b551SPrabhakar Kushwahabe able to receive control after a single step or breakpoint: 7afa6b551SPrabhakar Kushwaha - MSR[DE] must be set 8afa6b551SPrabhakar Kushwaha - A valid opcode must be fetchable, through the MMU, from the debug 9afa6b551SPrabhakar Kushwaha exception vector (IVPR + IVOR15). 10afa6b551SPrabhakar Kushwaha 11afa6b551SPrabhakar KushwahaTo maximize the time during which this requirement is met, U-Boot sets MSR[DE] 12afa6b551SPrabhakar Kushwahaimmediately on entry and keeps it set. It also uses a temporary TLB to keep a 13afa6b551SPrabhakar Kushwahamapping to a valid opcode at the debug exception vector, even if we normally 14afa6b551SPrabhakar Kushwahadon't support exception vectors being used that early, and that's not the area 15afa6b551SPrabhakar Kushwahawhere U-Boot currently executes from. 16afa6b551SPrabhakar Kushwaha 17afa6b551SPrabhakar KushwahaNote that there may still be some small windows where debugging will not work, 18afa6b551SPrabhakar Kushwahasuch as in between updating IVPR and IVOR15. 19afa6b551SPrabhakar Kushwaha 20afa6b551SPrabhakar KushwahaConfig Switches: 21afa6b551SPrabhakar Kushwaha---------------- 22afa6b551SPrabhakar Kushwaha 23afa6b551SPrabhakar KushwahaPlease refer README section "MPC85xx External Debug Support" 24afa6b551SPrabhakar Kushwaha 25afa6b551SPrabhakar KushwahaMajor Config Switches during various boot Modes 26afa6b551SPrabhakar Kushwaha---------------------------------------------- 27afa6b551SPrabhakar Kushwaha 28afa6b551SPrabhakar KushwahaNOR boot 29c97cd1baSScott Wood !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL) 30afa6b551SPrabhakar KushwahaNOR boot Secure 31afa6b551SPrabhakar Kushwaha !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) 32afa6b551SPrabhakar KushwahaRAMBOOT(SD, SPI & NAND boot) 33afa6b551SPrabhakar Kushwaha defined(CONFIG_SYS_RAMBOOT) 34afa6b551SPrabhakar KushwahaRAMBOOT Secure (SD, SPI & NAND) 35afa6b551SPrabhakar Kushwaha defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) 36afa6b551SPrabhakar KushwahaNAND SPL BOOT 37afa6b551SPrabhakar Kushwaha defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NAND_SPL) 38afa6b551SPrabhakar Kushwaha 39afa6b551SPrabhakar Kushwaha 40afa6b551SPrabhakar KushwahaTLB Entries during u-boot execution 41afa6b551SPrabhakar Kushwaha----------------------------------- 42afa6b551SPrabhakar Kushwaha 43afa6b551SPrabhakar KushwahaNote: Sequence number is in order of execution 44afa6b551SPrabhakar Kushwaha 45afa6b551SPrabhakar KushwahaA) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot 46afa6b551SPrabhakar Kushwaha 47afa6b551SPrabhakar Kushwaha 1) TLB entry to overcome e500 v1/v2 debug restriction 48afa6b551SPrabhakar Kushwaha Location : Label "_start_e500" 49afa6b551SPrabhakar Kushwaha TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB 50afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE 51afa6b551SPrabhakar Kushwaha Properties : 256K, AS0, I, IPROT 52afa6b551SPrabhakar Kushwaha 53afa6b551SPrabhakar Kushwaha 2) TLB entry for working in AS1 54afa6b551SPrabhakar Kushwaha Location : Label "create_init_ram_area" 55afa6b551SPrabhakar Kushwaha TLB Entry : 15 56afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE 57afa6b551SPrabhakar Kushwaha Properties : 1M, AS1, I, G, IPROT 58afa6b551SPrabhakar Kushwaha 59afa6b551SPrabhakar Kushwaha 3) TLB entry for the stack during AS1 60afa6b551SPrabhakar Kushwaha Location : Lable "create_init_ram_area" 61afa6b551SPrabhakar Kushwaha TLB Entry : 14 62afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR 63afa6b551SPrabhakar Kushwaha Properties : 16K, AS1, IPROT 64afa6b551SPrabhakar Kushwaha 65afa6b551SPrabhakar Kushwaha 4) TLB entry for CCSRBAR during AS1 execution 66afa6b551SPrabhakar Kushwaha Location : cpu_init_early_f 67afa6b551SPrabhakar Kushwaha TLB Entry : 13 68afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR 69afa6b551SPrabhakar Kushwaha Properties : 1M, AS1, I, G 70afa6b551SPrabhakar Kushwaha 71afa6b551SPrabhakar Kushwaha 5) Invalidate unproctected TLB Entries 72afa6b551SPrabhakar Kushwaha Location : cpu_init_early_f 73afa6b551SPrabhakar Kushwaha Invalidated: 13 74afa6b551SPrabhakar Kushwaha 75afa6b551SPrabhakar Kushwaha 6) Create TLB entries as per boards/freescale/<board>/tlb.c 76afa6b551SPrabhakar Kushwaha Location : cpu_init_early_f --> init_tlbs() 77afa6b551SPrabhakar Kushwaha Properties : ..., AS0, ... 78afa6b551SPrabhakar Kushwaha Please note It can overwrites previous TLB Entries. 79afa6b551SPrabhakar Kushwaha 80afa6b551SPrabhakar Kushwaha 7) Disable TLB Entries of AS1 81afa6b551SPrabhakar Kushwaha Location : cpu_init_f --> disable_tlb() 82afa6b551SPrabhakar Kushwaha Disable : 15, 14 83afa6b551SPrabhakar Kushwaha 84afa6b551SPrabhakar Kushwaha 8) Update Flash's TLB entry 85afa6b551SPrabhakar Kushwaha Location : Board_init_r 86afa6b551SPrabhakar Kushwaha TLB entry : Search from TLB entries 87afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS 88afa6b551SPrabhakar Kushwaha Properties : Board specific size, AS0, I, G, IPROT 89afa6b551SPrabhakar Kushwaha 90afa6b551SPrabhakar Kushwaha 91afa6b551SPrabhakar KushwahaB) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot 92afa6b551SPrabhakar Kushwaha 93afa6b551SPrabhakar Kushwaha 1) TLB entry to overcome e500 v1/v2 debug restriction 94afa6b551SPrabhakar Kushwaha Location : Label "_start_e500" 95afa6b551SPrabhakar Kushwaha TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB 96afa6b551SPrabhakar Kushwaha#if defined(CONFIG_SECURE_BOOT) 97afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW 98afa6b551SPrabhakar Kushwaha Properties : 1M, AS1, I, G, IPROT 99afa6b551SPrabhakar Kushwaha#else 100afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 101afa6b551SPrabhakar Kushwaha Properties : 4M, AS0, I, G, IPROT 102afa6b551SPrabhakar Kushwaha#endif 103afa6b551SPrabhakar Kushwaha 104afa6b551SPrabhakar Kushwaha 2) TLB entry for working in AS1 105afa6b551SPrabhakar Kushwaha Location : Label "create_init_ram_area" 106afa6b551SPrabhakar Kushwaha TLB Entry : 15 107afa6b551SPrabhakar Kushwaha#if defined(CONFIG_SECURE_BOOT) 108afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW 109afa6b551SPrabhakar Kushwaha Properties : 1M, AS1, I, G, IPROT 110afa6b551SPrabhakar Kushwaha#else 111afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 112afa6b551SPrabhakar Kushwaha Properties : 4M, AS1, I, G, IPROT 113afa6b551SPrabhakar Kushwaha#endif 114afa6b551SPrabhakar Kushwaha 115afa6b551SPrabhakar Kushwaha 3) TLB entry for the stack during AS1 116afa6b551SPrabhakar Kushwaha Location : Lable "create_init_ram_area" 117afa6b551SPrabhakar Kushwaha TLB Entry : 14 118afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR 119afa6b551SPrabhakar Kushwaha Properties : 16K, AS1, IPROT 120afa6b551SPrabhakar Kushwaha 121afa6b551SPrabhakar Kushwaha 4) TLB entry for CCSRBAR during AS1 execution 122afa6b551SPrabhakar Kushwaha Location : cpu_init_early_f 123afa6b551SPrabhakar Kushwaha TLB Entry : 13 124afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR 125afa6b551SPrabhakar Kushwaha Properties : 1M, AS1, I, G 126afa6b551SPrabhakar Kushwaha 127afa6b551SPrabhakar Kushwaha 5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399 128afa6b551SPrabhakar Kushwaha Location : cpu_init_early_f 129afa6b551SPrabhakar Kushwaha TLB Entry : 9 130afa6b551SPrabhakar Kushwaha EPN -->RPN : SRAM_BASE_ADDR --> SRAM_BASE_ADDR 131afa6b551SPrabhakar Kushwaha Properties : 1M, AS1, I 132afa6b551SPrabhakar Kushwaha 133afa6b551SPrabhakar Kushwaha 6) CONFIG_SYS_FSL_ERRATUM_IFC_A003399 Adjust flash's phys addr 134afa6b551SPrabhakar Kushwaha Location : cpu_init_early_f --> setup_ifc 135afa6b551SPrabhakar Kushwaha TLB Entry : Get Flash TLB 136afa6b551SPrabhakar Kushwaha EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys 137afa6b551SPrabhakar Kushwaha Properties : 4M, AS1, I, G, IPROT 138afa6b551SPrabhakar Kushwaha 139afa6b551SPrabhakar Kushwaha 7) CONFIG_SYS_FSL_ERRATUM_IFC_A003399: E500 v1,v2 debug restriction 140afa6b551SPrabhakar Kushwaha Location : cpu_init_early_f --> setup_ifc 141afa6b551SPrabhakar Kushwaha TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB 142afa6b551SPrabhakar Kushwaha EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys 143afa6b551SPrabhakar Kushwaha Properties : 4M, AS0, I, G, IPROT 144afa6b551SPrabhakar Kushwaha 145afa6b551SPrabhakar Kushwaha 8) Invalidate unproctected TLB Entries 146afa6b551SPrabhakar Kushwaha Location : cpu_init_early_f 147afa6b551SPrabhakar Kushwaha Invalidated: 13, 9 148afa6b551SPrabhakar Kushwaha 149afa6b551SPrabhakar Kushwaha 9) Create TLB entries as per boards/freescale/<board>/tlb.c 150afa6b551SPrabhakar Kushwaha Location : cpu_init_early_f --> init_tlbs() 151afa6b551SPrabhakar Kushwaha Properties : ..., AS0, ... 152afa6b551SPrabhakar Kushwaha Note: It can overwrites previous TLB Entries 153afa6b551SPrabhakar Kushwaha 154afa6b551SPrabhakar Kushwaha 10) Disable TLB Entries of AS1 155afa6b551SPrabhakar Kushwaha Location : cpu_init_f --> disable_tlb() 156afa6b551SPrabhakar Kushwaha Disable : 15, 14 157afa6b551SPrabhakar Kushwaha 158afa6b551SPrabhakar Kushwaha 11) Create DDR's TLB entriy 159*f1683aa7SSimon Glass Location : Board_init_f -> dram_init 160afa6b551SPrabhakar Kushwaha TLB entry : Search free TLB entry 161afa6b551SPrabhakar Kushwaha 162afa6b551SPrabhakar Kushwaha 12) Update Flash's TLB entry 163afa6b551SPrabhakar Kushwaha Location : Board_init_r 164afa6b551SPrabhakar Kushwaha TLB entry : Search from TLB entries 165afa6b551SPrabhakar Kushwaha EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS 166afa6b551SPrabhakar Kushwaha Properties : Board specific size, AS0, I, G, IPROT 167