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Searched refs:SDMA0_STATUS_REG__SEM_IDLE__SHIFT (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_sh_mask.h508 #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT … macro
H A Dsdma0_4_0_sh_mask.h509 #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a macro
H A Dsdma0_4_2_sh_mask.h509 #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT … macro
H A Dsdma0_4_2_2_sh_mask.h515 #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_sh_mask.h1038 #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a macro
H A Doss_2_0_sh_mask.h954 #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a macro
H A Doss_3_0_1_sh_mask.h1056 #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a macro
H A Doss_3_0_sh_mask.h1562 #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_sh_mask.h200 #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_sh_mask.h185 #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h193 #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h217 #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h218 #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT … macro