14f727eceSLe Ma /* 24f727eceSLe Ma * Copyright (C) 2018 Advanced Micro Devices, Inc. 34f727eceSLe Ma * 44f727eceSLe Ma * Permission is hereby granted, free of charge, to any person obtaining a 54f727eceSLe Ma * copy of this software and associated documentation files (the "Software"), 64f727eceSLe Ma * to deal in the Software without restriction, including without limitation 74f727eceSLe Ma * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84f727eceSLe Ma * and/or sell copies of the Software, and to permit persons to whom the 94f727eceSLe Ma * Software is furnished to do so, subject to the following conditions: 104f727eceSLe Ma * 114f727eceSLe Ma * The above copyright notice and this permission notice shall be included 124f727eceSLe Ma * in all copies or substantial portions of the Software. 134f727eceSLe Ma * 144f727eceSLe Ma * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 154f727eceSLe Ma * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164f727eceSLe Ma * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174f727eceSLe Ma * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 184f727eceSLe Ma * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 194f727eceSLe Ma * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 204f727eceSLe Ma */ 214f727eceSLe Ma #ifndef _sdma0_4_2_2_SH_MASK_HEADER 224f727eceSLe Ma #define _sdma0_4_2_2_SH_MASK_HEADER 234f727eceSLe Ma 244f727eceSLe Ma 254f727eceSLe Ma // addressBlock: sdma0_sdma0dec 264f727eceSLe Ma //SDMA0_UCODE_ADDR 274f727eceSLe Ma #define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 284f727eceSLe Ma #define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL 294f727eceSLe Ma //SDMA0_UCODE_DATA 304f727eceSLe Ma #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 314f727eceSLe Ma #define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 324f727eceSLe Ma //SDMA0_VM_CNTL 334f727eceSLe Ma #define SDMA0_VM_CNTL__CMD__SHIFT 0x0 344f727eceSLe Ma #define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL 354f727eceSLe Ma //SDMA0_VM_CTX_LO 364f727eceSLe Ma #define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 374f727eceSLe Ma #define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 384f727eceSLe Ma //SDMA0_VM_CTX_HI 394f727eceSLe Ma #define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 404f727eceSLe Ma #define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 414f727eceSLe Ma //SDMA0_ACTIVE_FCN_ID 424f727eceSLe Ma #define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 434f727eceSLe Ma #define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 444f727eceSLe Ma #define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f 454f727eceSLe Ma #define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 464f727eceSLe Ma #define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 474f727eceSLe Ma #define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L 484f727eceSLe Ma //SDMA0_VM_CTX_CNTL 494f727eceSLe Ma #define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 504f727eceSLe Ma #define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 514f727eceSLe Ma #define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L 524f727eceSLe Ma #define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L 534f727eceSLe Ma //SDMA0_VIRT_RESET_REQ 544f727eceSLe Ma #define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 554f727eceSLe Ma #define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f 564f727eceSLe Ma #define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 574f727eceSLe Ma #define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L 584f727eceSLe Ma //SDMA0_VF_ENABLE 594f727eceSLe Ma #define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 604f727eceSLe Ma #define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 614f727eceSLe Ma //SDMA0_CONTEXT_REG_TYPE0 624f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 634f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 644f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 654f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 664f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 674f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 684f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 694f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 704f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 714f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 724f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa 734f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb 744f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc 754f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd 764f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe 774f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf 784f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 794f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 804f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 814f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 824f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L 834f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L 844f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L 854f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L 864f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L 874f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L 884f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L 894f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 904f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 914f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 924f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L 934f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L 944f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L 954f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L 964f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L 974f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L 984f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L 994f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L 1004f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L 1014f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L 1024f727eceSLe Ma //SDMA0_CONTEXT_REG_TYPE1 1034f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 1044f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 1054f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa 1064f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb 1074f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc 1084f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd 1094f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 1104f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf 1114f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 1124f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 1134f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 1144f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 1154f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 1164f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 1174f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 1184f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L 1194f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L 1204f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L 1214f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L 1224f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L 1234f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L 1244f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L 1254f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L 1264f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L 1274f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L 1284f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 1294f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 1304f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L 1314f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 1324f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 1334f727eceSLe Ma //SDMA0_CONTEXT_REG_TYPE2 1344f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 1354f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 1364f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 1374f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 1384f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 1394f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 1404f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 1414f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 1424f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 1434f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 1444f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 1454f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L 1464f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L 1474f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L 1484f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L 1494f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L 1504f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L 1514f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L 1524f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L 1534f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L 1544f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L 1554f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L 1564f727eceSLe Ma //SDMA0_CONTEXT_REG_TYPE3 1574f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 1584f727eceSLe Ma #define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 1594f727eceSLe Ma //SDMA0_PUB_REG_TYPE0 1604f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 1614f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 1624f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 1634f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 1644f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 1654f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 1664f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 1674f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 1684f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 1694f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 1704f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb 1714f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc 1724f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd 1734f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe 1744f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf 1754f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 1764f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 1774f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 1784f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 1794f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x15 1804f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 1814f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a 1824f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b 1834f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c 1844f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d 1854f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e 1864f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f 1874f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L 1884f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L 1894f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L 1904f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L 1914f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L 1924f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L 1934f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L 1944f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L 1954f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L 1964f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L 1974f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L 1984f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L 1994f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L 2004f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L 2014f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L 2024f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L 2034f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L 2044f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L 2054f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L 2064f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01E00000L 2074f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L 2084f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L 2094f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L 2104f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L 2114f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L 2124f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L 2134f727eceSLe Ma #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L 2144f727eceSLe Ma //SDMA0_PUB_REG_TYPE1 2154f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 2164f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 2174f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 2184f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 2194f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 2204f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 2214f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 2224f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 2234f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 2244f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 2254f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa 2264f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb 2274f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc 2284f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd 2294f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 2304f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 2314f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 2324f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 2334f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 2344f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 2354f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 2364f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 2374f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 2384f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 2394f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 2404f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 2414f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a 2424f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b 2434f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c 2444f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d 2454f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e 2464f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f 2474f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L 2484f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 2494f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L 2504f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L 2514f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L 2524f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L 2534f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L 2544f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L 2554f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L 2564f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L 2574f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L 2584f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L 2594f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L 2604f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L 2614f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 2624f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 2634f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 2644f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 2654f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L 2664f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L 2674f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L 2684f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L 2694f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L 2704f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L 2714f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L 2724f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L 2734f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L 2744f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L 2754f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L 2764f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L 2774f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L 2784f727eceSLe Ma #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L 2794f727eceSLe Ma //SDMA0_PUB_REG_TYPE2 2804f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 2814f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 2824f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 2834f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 2844f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 2854f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 2864f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 2874f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 2884f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 2894f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 2904f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa 2914f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb 2924f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc 2934f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd 2944f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe 2954f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0xf 2964f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 2974f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 2984f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 2994f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 3004f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 3014f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 3024f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16 3034f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 3044f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 3054f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 3064f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a 3074f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b 3084f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__RESERVED28__SHIFT 0x1c 3094f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d 3104f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e 3114f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f 3124f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L 3134f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L 3144f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L 3154f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L 3164f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L 3174f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L 3184f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L 3194f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L 3204f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L 3214f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L 3224f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L 3234f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L 3244f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L 3254f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L 3264f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L 3274f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L 3284f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L 3294f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L 3304f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L 3314f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L 3324f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L 3334f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L 3344f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L 3354f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L 3364f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L 3374f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L 3384f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L 3394f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L 3404f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__RESERVED28_MASK 0x10000000L 3414f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L 3424f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L 3434f727eceSLe Ma #define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L 3444f727eceSLe Ma //SDMA0_PUB_REG_TYPE3 3454f727eceSLe Ma #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 3464f727eceSLe Ma #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 3474f727eceSLe Ma #define SDMA0_PUB_REG_TYPE3__SDMA0_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 3484f727eceSLe Ma #define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x3 3494f727eceSLe Ma #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L 3504f727eceSLe Ma #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 3514f727eceSLe Ma #define SDMA0_PUB_REG_TYPE3__SDMA0_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L 3524f727eceSLe Ma #define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFF8L 3534f727eceSLe Ma //SDMA0_MMHUB_CNTL 3544f727eceSLe Ma #define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 3554f727eceSLe Ma #define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 3564f727eceSLe Ma //SDMA0_CONTEXT_GROUP_BOUNDARY 3574f727eceSLe Ma #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 3584f727eceSLe Ma #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 3594f727eceSLe Ma //SDMA0_POWER_CNTL 3604f727eceSLe Ma #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 3614f727eceSLe Ma #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 3624f727eceSLe Ma #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 3634f727eceSLe Ma #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 3644f727eceSLe Ma #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 3654f727eceSLe Ma #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 3664f727eceSLe Ma #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 3674f727eceSLe Ma #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 3684f727eceSLe Ma #define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 3694f727eceSLe Ma #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a 3704f727eceSLe Ma #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L 3714f727eceSLe Ma #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L 3724f727eceSLe Ma #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L 3734f727eceSLe Ma #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 3744f727eceSLe Ma #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 3754f727eceSLe Ma #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 3764f727eceSLe Ma #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 3774f727eceSLe Ma #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 3784f727eceSLe Ma #define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 3794f727eceSLe Ma #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 3804f727eceSLe Ma //SDMA0_CLK_CTRL 3814f727eceSLe Ma #define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 3824f727eceSLe Ma #define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 3834f727eceSLe Ma #define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc 3844f727eceSLe Ma #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 3854f727eceSLe Ma #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 3864f727eceSLe Ma #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 3874f727eceSLe Ma #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 3884f727eceSLe Ma #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 3894f727eceSLe Ma #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 3904f727eceSLe Ma #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 3914f727eceSLe Ma #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 3924f727eceSLe Ma #define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 3934f727eceSLe Ma #define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 3944f727eceSLe Ma #define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L 3954f727eceSLe Ma #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 3964f727eceSLe Ma #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 3974f727eceSLe Ma #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 3984f727eceSLe Ma #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 3994f727eceSLe Ma #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 4004f727eceSLe Ma #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 4014f727eceSLe Ma #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 4024f727eceSLe Ma #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 4034f727eceSLe Ma //SDMA0_CNTL 4044f727eceSLe Ma #define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 4054f727eceSLe Ma #define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 4064f727eceSLe Ma #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 4074f727eceSLe Ma #define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 4084f727eceSLe Ma #define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 4094f727eceSLe Ma #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 4104f727eceSLe Ma #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 4114f727eceSLe Ma #define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 4124f727eceSLe Ma #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 4134f727eceSLe Ma #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 4144f727eceSLe Ma #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 4154f727eceSLe Ma #define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L 4164f727eceSLe Ma #define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 4174f727eceSLe Ma #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 4184f727eceSLe Ma #define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 4194f727eceSLe Ma #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 4204f727eceSLe Ma #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 4214f727eceSLe Ma #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 4224f727eceSLe Ma #define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 4234f727eceSLe Ma #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 4244f727eceSLe Ma #define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 4254f727eceSLe Ma #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 4264f727eceSLe Ma //SDMA0_CHICKEN_BITS 4274f727eceSLe Ma #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 4284f727eceSLe Ma #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 4294f727eceSLe Ma #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 4304f727eceSLe Ma #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 4314f727eceSLe Ma #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 4324f727eceSLe Ma #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 4334f727eceSLe Ma #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 4344f727eceSLe Ma #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 4354f727eceSLe Ma #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 4364f727eceSLe Ma #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 4374f727eceSLe Ma #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 4384f727eceSLe Ma #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 4394f727eceSLe Ma #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 4404f727eceSLe Ma #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 4414f727eceSLe Ma #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 4424f727eceSLe Ma #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 4434f727eceSLe Ma #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 4444f727eceSLe Ma #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 4454f727eceSLe Ma #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 4464f727eceSLe Ma #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 4474f727eceSLe Ma #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 4484f727eceSLe Ma #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 4494f727eceSLe Ma #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 4504f727eceSLe Ma #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L 4514f727eceSLe Ma #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L 4524f727eceSLe Ma #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L 4534f727eceSLe Ma //SDMA0_GB_ADDR_CONFIG 4544f727eceSLe Ma #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 4554f727eceSLe Ma #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 4564f727eceSLe Ma #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 4574f727eceSLe Ma #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 4584f727eceSLe Ma #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 4594f727eceSLe Ma #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 4604f727eceSLe Ma #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 4614f727eceSLe Ma #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 4624f727eceSLe Ma #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 4634f727eceSLe Ma #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 4644f727eceSLe Ma //SDMA0_GB_ADDR_CONFIG_READ 4654f727eceSLe Ma #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 4664f727eceSLe Ma #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 4674f727eceSLe Ma #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 4684f727eceSLe Ma #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 4694f727eceSLe Ma #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 4704f727eceSLe Ma #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 4714f727eceSLe Ma #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 4724f727eceSLe Ma #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 4734f727eceSLe Ma #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 4744f727eceSLe Ma #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 4754f727eceSLe Ma //SDMA0_RB_RPTR_FETCH_HI 4764f727eceSLe Ma #define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 4774f727eceSLe Ma #define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 4784f727eceSLe Ma //SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 4794f727eceSLe Ma #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 4804f727eceSLe Ma #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 4814f727eceSLe Ma //SDMA0_RB_RPTR_FETCH 4824f727eceSLe Ma #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 4834f727eceSLe Ma #define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 4844f727eceSLe Ma //SDMA0_IB_OFFSET_FETCH 4854f727eceSLe Ma #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 4864f727eceSLe Ma #define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 4874f727eceSLe Ma //SDMA0_PROGRAM 4884f727eceSLe Ma #define SDMA0_PROGRAM__STREAM__SHIFT 0x0 4894f727eceSLe Ma #define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL 4904f727eceSLe Ma //SDMA0_STATUS_REG 4914f727eceSLe Ma #define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 4924f727eceSLe Ma #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 4934f727eceSLe Ma #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 4944f727eceSLe Ma #define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 4954f727eceSLe Ma #define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 4964f727eceSLe Ma #define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 4974f727eceSLe Ma #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 4984f727eceSLe Ma #define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 4994f727eceSLe Ma #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 5004f727eceSLe Ma #define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 5014f727eceSLe Ma #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa 5024f727eceSLe Ma #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 5034f727eceSLe Ma #define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc 5044f727eceSLe Ma #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 5054f727eceSLe Ma #define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe 5064f727eceSLe Ma #define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 5074f727eceSLe Ma #define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 5084f727eceSLe Ma #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 5094f727eceSLe Ma #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 5104f727eceSLe Ma #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 5114f727eceSLe Ma #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 5124f727eceSLe Ma #define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 5134f727eceSLe Ma #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 5144f727eceSLe Ma #define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 5154f727eceSLe Ma #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a 5164f727eceSLe Ma #define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 5174f727eceSLe Ma #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 5184f727eceSLe Ma #define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e 5194f727eceSLe Ma #define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 5204f727eceSLe Ma #define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L 5214f727eceSLe Ma #define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L 5224f727eceSLe Ma #define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L 5234f727eceSLe Ma #define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L 5244f727eceSLe Ma #define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 5254f727eceSLe Ma #define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 5264f727eceSLe Ma #define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 5274f727eceSLe Ma #define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 5284f727eceSLe Ma #define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 5294f727eceSLe Ma #define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L 5304f727eceSLe Ma #define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L 5314f727eceSLe Ma #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 5324f727eceSLe Ma #define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L 5334f727eceSLe Ma #define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 5344f727eceSLe Ma #define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 5354f727eceSLe Ma #define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 5364f727eceSLe Ma #define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 5374f727eceSLe Ma #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 5384f727eceSLe Ma #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 5394f727eceSLe Ma #define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 5404f727eceSLe Ma #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 5414f727eceSLe Ma #define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 5424f727eceSLe Ma #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 5434f727eceSLe Ma #define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 5444f727eceSLe Ma #define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L 5454f727eceSLe Ma #define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 5464f727eceSLe Ma #define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 5474f727eceSLe Ma #define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L 5484f727eceSLe Ma #define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 5494f727eceSLe Ma //SDMA0_STATUS1_REG 5504f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 5514f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 5524f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 5534f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 5544f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 5554f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 5564f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 5574f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 5584f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 5594f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 5604f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 5614f727eceSLe Ma #define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf 5624f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 5634f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 5644f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 5654f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 5664f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 5674f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 5684f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 5694f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 5704f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 5714f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 5724f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 5734f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 5744f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 5754f727eceSLe Ma #define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L 5764f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 5774f727eceSLe Ma #define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 5784f727eceSLe Ma //SDMA0_RD_BURST_CNTL 5794f727eceSLe Ma #define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 5804f727eceSLe Ma #define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 5814f727eceSLe Ma #define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 5824f727eceSLe Ma #define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL 5834f727eceSLe Ma //SDMA0_HBM_PAGE_CONFIG 5844f727eceSLe Ma #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 5854f727eceSLe Ma #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L 5864f727eceSLe Ma //SDMA0_UCODE_CHECKSUM 5874f727eceSLe Ma #define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 5884f727eceSLe Ma #define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 5894f727eceSLe Ma //SDMA0_F32_CNTL 5904f727eceSLe Ma #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 5914f727eceSLe Ma #define SDMA0_F32_CNTL__STEP__SHIFT 0x1 5924f727eceSLe Ma #define SDMA0_F32_CNTL__HALT_MASK 0x00000001L 5934f727eceSLe Ma #define SDMA0_F32_CNTL__STEP_MASK 0x00000002L 5944f727eceSLe Ma //SDMA0_FREEZE 5954f727eceSLe Ma #define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 5964f727eceSLe Ma #define SDMA0_FREEZE__FREEZE__SHIFT 0x4 5974f727eceSLe Ma #define SDMA0_FREEZE__FROZEN__SHIFT 0x5 5984f727eceSLe Ma #define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 5994f727eceSLe Ma #define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L 6004f727eceSLe Ma #define SDMA0_FREEZE__FREEZE_MASK 0x00000010L 6014f727eceSLe Ma #define SDMA0_FREEZE__FROZEN_MASK 0x00000020L 6024f727eceSLe Ma #define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L 6034f727eceSLe Ma //SDMA0_PHASE0_QUANTUM 6044f727eceSLe Ma #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 6054f727eceSLe Ma #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 6064f727eceSLe Ma #define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 6074f727eceSLe Ma #define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 6084f727eceSLe Ma #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 6094f727eceSLe Ma #define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 6104f727eceSLe Ma //SDMA0_PHASE1_QUANTUM 6114f727eceSLe Ma #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 6124f727eceSLe Ma #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 6134f727eceSLe Ma #define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 6144f727eceSLe Ma #define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 6154f727eceSLe Ma #define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 6164f727eceSLe Ma #define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 6174f727eceSLe Ma //SDMA_POWER_GATING 6184f727eceSLe Ma #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 6194f727eceSLe Ma #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 6204f727eceSLe Ma #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 6214f727eceSLe Ma #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 6224f727eceSLe Ma #define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 6234f727eceSLe Ma #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L 6244f727eceSLe Ma #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L 6254f727eceSLe Ma #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L 6264f727eceSLe Ma #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L 6274f727eceSLe Ma #define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L 6284f727eceSLe Ma //SDMA_PGFSM_CONFIG 6294f727eceSLe Ma #define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 6304f727eceSLe Ma #define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 6314f727eceSLe Ma #define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 6324f727eceSLe Ma #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa 6334f727eceSLe Ma #define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb 6344f727eceSLe Ma #define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc 6354f727eceSLe Ma #define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd 6364f727eceSLe Ma #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b 6374f727eceSLe Ma #define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 6384f727eceSLe Ma #define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL 6394f727eceSLe Ma #define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L 6404f727eceSLe Ma #define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L 6414f727eceSLe Ma #define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L 6424f727eceSLe Ma #define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L 6434f727eceSLe Ma #define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L 6444f727eceSLe Ma #define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L 6454f727eceSLe Ma #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L 6464f727eceSLe Ma #define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L 6474f727eceSLe Ma //SDMA_PGFSM_WRITE 6484f727eceSLe Ma #define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 6494f727eceSLe Ma #define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL 6504f727eceSLe Ma //SDMA_PGFSM_READ 6514f727eceSLe Ma #define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 6524f727eceSLe Ma #define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL 6534f727eceSLe Ma //SDMA0_EDC_CONFIG 6544f727eceSLe Ma #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 6554f727eceSLe Ma #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 6564f727eceSLe Ma #define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 6574f727eceSLe Ma #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L 6584f727eceSLe Ma //SDMA0_BA_THRESHOLD 6594f727eceSLe Ma #define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 6604f727eceSLe Ma #define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 6614f727eceSLe Ma #define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 6624f727eceSLe Ma #define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 6634f727eceSLe Ma //SDMA0_ID 6644f727eceSLe Ma #define SDMA0_ID__DEVICE_ID__SHIFT 0x0 6654f727eceSLe Ma #define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL 6664f727eceSLe Ma //SDMA0_VERSION 6674f727eceSLe Ma #define SDMA0_VERSION__MINVER__SHIFT 0x0 6684f727eceSLe Ma #define SDMA0_VERSION__MAJVER__SHIFT 0x8 6694f727eceSLe Ma #define SDMA0_VERSION__REV__SHIFT 0x10 6704f727eceSLe Ma #define SDMA0_VERSION__MINVER_MASK 0x0000007FL 6714f727eceSLe Ma #define SDMA0_VERSION__MAJVER_MASK 0x00007F00L 6724f727eceSLe Ma #define SDMA0_VERSION__REV_MASK 0x003F0000L 6734f727eceSLe Ma //SDMA0_EDC_COUNTER 6744f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 6754f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 6764f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 6774f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 6784f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 6794f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 6804f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 6814f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 6824f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 6834f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 6844f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb 6854f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc 6864f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd 6874f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 6884f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf 6894f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 6904f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 6914f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 6924f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 6934f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 6944f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 6954f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 6964f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 6974f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 6984f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L 6994f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L 7004f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L 7014f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L 7024f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L 7034f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L 7044f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L 7054f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L 7064f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L 7074f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L 7084f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L 7094f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L 7104f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L 7114f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L 7124f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L 7134f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L 7144f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L 7154f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L 7164f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L 7174f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L 7184f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L 7194f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L 7204f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L 7214f727eceSLe Ma #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L 7224f727eceSLe Ma //SDMA0_EDC_COUNTER_CLEAR 7234f727eceSLe Ma #define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 7244f727eceSLe Ma #define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L 7254f727eceSLe Ma //SDMA0_STATUS2_REG 7264f727eceSLe Ma #define SDMA0_STATUS2_REG__ID__SHIFT 0x0 7274f727eceSLe Ma #define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 7284f727eceSLe Ma #define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 7294f727eceSLe Ma #define SDMA0_STATUS2_REG__ID_MASK 0x00000007L 7304f727eceSLe Ma #define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L 7314f727eceSLe Ma #define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 7324f727eceSLe Ma //SDMA0_ATOMIC_CNTL 7334f727eceSLe Ma #define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 7344f727eceSLe Ma #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 7354f727eceSLe Ma #define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 7364f727eceSLe Ma #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 7374f727eceSLe Ma //SDMA0_ATOMIC_PREOP_LO 7384f727eceSLe Ma #define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 7394f727eceSLe Ma #define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 7404f727eceSLe Ma //SDMA0_ATOMIC_PREOP_HI 7414f727eceSLe Ma #define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 7424f727eceSLe Ma #define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 7434f727eceSLe Ma //SDMA0_UTCL1_CNTL 7444f727eceSLe Ma #define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 7454f727eceSLe Ma #define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 7464f727eceSLe Ma #define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 7474f727eceSLe Ma #define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 7484f727eceSLe Ma #define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 7494f727eceSLe Ma #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 7504f727eceSLe Ma #define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 7514f727eceSLe Ma #define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 7524f727eceSLe Ma #define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 7534f727eceSLe Ma #define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 7544f727eceSLe Ma #define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 7554f727eceSLe Ma #define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 7564f727eceSLe Ma //SDMA0_UTCL1_WATERMK 7574f727eceSLe Ma #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 7584f727eceSLe Ma #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 7594f727eceSLe Ma #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 7604f727eceSLe Ma #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 7614f727eceSLe Ma #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL 7624f727eceSLe Ma #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L 7634f727eceSLe Ma #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L 7644f727eceSLe Ma #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L 7654f727eceSLe Ma //SDMA0_UTCL1_RD_STATUS 7664f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 7674f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 7684f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 7694f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 7704f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 7714f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 7724f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 7734f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 7744f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 7754f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 7764f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 7774f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 7784f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 7794f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 7804f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 7814f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 7824f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 7834f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 7844f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 7854f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 7864f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 7874f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 7884f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 7894f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 7904f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 7914f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 7924f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 7934f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 7944f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 7954f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 7964f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 7974f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 7984f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 7994f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 8004f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 8014f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 8024f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 8034f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 8044f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 8054f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 8064f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 8074f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 8084f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 8094f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 8104f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 8114f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 8124f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 8134f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 8144f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 8154f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 8164f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 8174f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 8184f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 8194f727eceSLe Ma #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 8204f727eceSLe Ma //SDMA0_UTCL1_WR_STATUS 8214f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 8224f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 8234f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 8244f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 8254f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 8264f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 8274f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 8284f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 8294f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 8304f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 8314f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 8324f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 8334f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 8344f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 8354f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 8364f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 8374f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 8384f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 8394f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 8404f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 8414f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 8424f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 8434f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 8444f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 8454f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 8464f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 8474f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 8484f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 8494f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 8504f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 8514f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 8524f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 8534f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 8544f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 8554f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 8564f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 8574f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 8584f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 8594f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 8604f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 8614f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 8624f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 8634f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 8644f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 8654f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 8664f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 8674f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 8684f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 8694f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 8704f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 8714f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 8724f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 8734f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 8744f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 8754f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 8764f727eceSLe Ma #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 8774f727eceSLe Ma //SDMA0_UTCL1_INV0 8784f727eceSLe Ma #define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 8794f727eceSLe Ma #define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 8804f727eceSLe Ma #define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 8814f727eceSLe Ma #define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 8824f727eceSLe Ma #define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 8834f727eceSLe Ma #define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 8844f727eceSLe Ma #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 8854f727eceSLe Ma #define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 8864f727eceSLe Ma #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 8874f727eceSLe Ma #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 8884f727eceSLe Ma #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 8894f727eceSLe Ma #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 8904f727eceSLe Ma #define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 8914f727eceSLe Ma #define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 8924f727eceSLe Ma #define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 8934f727eceSLe Ma #define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 8944f727eceSLe Ma #define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 8954f727eceSLe Ma #define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 8964f727eceSLe Ma #define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 8974f727eceSLe Ma #define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 8984f727eceSLe Ma #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 8994f727eceSLe Ma #define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 9004f727eceSLe Ma #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 9014f727eceSLe Ma #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 9024f727eceSLe Ma #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 9034f727eceSLe Ma #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 9044f727eceSLe Ma #define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 9054f727eceSLe Ma #define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 9064f727eceSLe Ma //SDMA0_UTCL1_INV1 9074f727eceSLe Ma #define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 9084f727eceSLe Ma #define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 9094f727eceSLe Ma //SDMA0_UTCL1_INV2 9104f727eceSLe Ma #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 9114f727eceSLe Ma #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 9124f727eceSLe Ma //SDMA0_UTCL1_RD_XNACK0 9134f727eceSLe Ma #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 9144f727eceSLe Ma #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 9154f727eceSLe Ma //SDMA0_UTCL1_RD_XNACK1 9164f727eceSLe Ma #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 9174f727eceSLe Ma #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 9184f727eceSLe Ma #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 9194f727eceSLe Ma #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 9204f727eceSLe Ma #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 9214f727eceSLe Ma #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 9224f727eceSLe Ma #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 9234f727eceSLe Ma #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 9244f727eceSLe Ma //SDMA0_UTCL1_WR_XNACK0 9254f727eceSLe Ma #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 9264f727eceSLe Ma #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 9274f727eceSLe Ma //SDMA0_UTCL1_WR_XNACK1 9284f727eceSLe Ma #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 9294f727eceSLe Ma #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 9304f727eceSLe Ma #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 9314f727eceSLe Ma #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 9324f727eceSLe Ma #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 9334f727eceSLe Ma #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 9344f727eceSLe Ma #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 9354f727eceSLe Ma #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 9364f727eceSLe Ma //SDMA0_UTCL1_TIMEOUT 9374f727eceSLe Ma #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 9384f727eceSLe Ma #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 9394f727eceSLe Ma #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 9404f727eceSLe Ma #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 9414f727eceSLe Ma //SDMA0_UTCL1_PAGE 9424f727eceSLe Ma #define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 9434f727eceSLe Ma #define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 9444f727eceSLe Ma #define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 9454f727eceSLe Ma #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 9464f727eceSLe Ma #define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 9474f727eceSLe Ma #define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 9484f727eceSLe Ma #define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 9494f727eceSLe Ma #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 9504f727eceSLe Ma //SDMA0_POWER_CNTL_IDLE 9514f727eceSLe Ma #define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 9524f727eceSLe Ma #define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 9534f727eceSLe Ma #define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 9544f727eceSLe Ma #define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 9554f727eceSLe Ma #define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 9564f727eceSLe Ma #define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 9574f727eceSLe Ma //SDMA0_RELAX_ORDERING_LUT 9584f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 9594f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 9604f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 9614f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 9624f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 9634f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 9644f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 9654f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 9664f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 9674f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 9684f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 9694f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 9704f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 9714f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 9724f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 9734f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 9744f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 9754f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 9764f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 9774f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 9784f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 9794f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 9804f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 9814f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 9824f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 9834f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 9844f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 9854f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 9864f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 9874f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 9884f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 9894f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 9904f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 9914f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 9924f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 9934f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 9944f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 9954f727eceSLe Ma #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 9964f727eceSLe Ma //SDMA0_CHICKEN_BITS_2 9974f727eceSLe Ma #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 9984f727eceSLe Ma #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 9994f727eceSLe Ma //SDMA0_STATUS3_REG 10004f727eceSLe Ma #define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 10014f727eceSLe Ma #define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 10024f727eceSLe Ma #define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 10034f727eceSLe Ma #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 10044f727eceSLe Ma #define SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 10054f727eceSLe Ma #define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 10064f727eceSLe Ma #define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 10074f727eceSLe Ma #define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 10084f727eceSLe Ma #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L 10094f727eceSLe Ma #define SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L 10104f727eceSLe Ma //SDMA0_PHYSICAL_ADDR_LO 10114f727eceSLe Ma #define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 10124f727eceSLe Ma #define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 10134f727eceSLe Ma #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 10144f727eceSLe Ma #define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 10154f727eceSLe Ma #define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 10164f727eceSLe Ma #define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 10174f727eceSLe Ma #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 10184f727eceSLe Ma #define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 10194f727eceSLe Ma //SDMA0_PHYSICAL_ADDR_HI 10204f727eceSLe Ma #define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 10214f727eceSLe Ma #define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 10224f727eceSLe Ma //SDMA0_PHASE2_QUANTUM 10234f727eceSLe Ma #define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0 10244f727eceSLe Ma #define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8 10254f727eceSLe Ma #define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 10264f727eceSLe Ma #define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 10274f727eceSLe Ma #define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 10284f727eceSLe Ma #define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 10294f727eceSLe Ma //SDMA0_ERROR_LOG 10304f727eceSLe Ma #define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 10314f727eceSLe Ma #define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 10324f727eceSLe Ma #define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 10334f727eceSLe Ma #define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L 10344f727eceSLe Ma //SDMA0_PUB_DUMMY_REG0 10354f727eceSLe Ma #define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 10364f727eceSLe Ma #define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 10374f727eceSLe Ma //SDMA0_PUB_DUMMY_REG1 10384f727eceSLe Ma #define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 10394f727eceSLe Ma #define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 10404f727eceSLe Ma //SDMA0_PUB_DUMMY_REG2 10414f727eceSLe Ma #define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 10424f727eceSLe Ma #define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 10434f727eceSLe Ma //SDMA0_PUB_DUMMY_REG3 10444f727eceSLe Ma #define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 10454f727eceSLe Ma #define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 10464f727eceSLe Ma //SDMA0_F32_COUNTER 10474f727eceSLe Ma #define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 10484f727eceSLe Ma #define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 10494f727eceSLe Ma //SDMA0_UNBREAKABLE 10504f727eceSLe Ma #define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0 10514f727eceSLe Ma #define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L 10524f727eceSLe Ma //SDMA0_PERFMON_CNTL 10534f727eceSLe Ma #define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 10544f727eceSLe Ma #define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 10554f727eceSLe Ma #define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 10564f727eceSLe Ma #define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 10574f727eceSLe Ma #define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 10584f727eceSLe Ma #define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 10594f727eceSLe Ma #define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 10604f727eceSLe Ma #define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 10614f727eceSLe Ma #define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 10624f727eceSLe Ma #define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 10634f727eceSLe Ma #define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 10644f727eceSLe Ma #define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 10654f727eceSLe Ma //SDMA0_PERFCOUNTER0_RESULT 10664f727eceSLe Ma #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 10674f727eceSLe Ma #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 10684f727eceSLe Ma //SDMA0_PERFCOUNTER1_RESULT 10694f727eceSLe Ma #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 10704f727eceSLe Ma #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 10714f727eceSLe Ma //SDMA0_PERFCOUNTER_TAG_DELAY_RANGE 10724f727eceSLe Ma #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 10734f727eceSLe Ma #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe 10744f727eceSLe Ma #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c 10754f727eceSLe Ma #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL 10764f727eceSLe Ma #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L 10774f727eceSLe Ma #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L 10784f727eceSLe Ma //SDMA0_CRD_CNTL 10794f727eceSLe Ma #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 10804f727eceSLe Ma #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 10814f727eceSLe Ma #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 10824f727eceSLe Ma #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 10834f727eceSLe Ma //SDMA0_GPU_IOV_VIOLATION_LOG 10844f727eceSLe Ma #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 10854f727eceSLe Ma #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 10864f727eceSLe Ma #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 10874f727eceSLe Ma #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 10884f727eceSLe Ma #define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 10894f727eceSLe Ma #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 10904f727eceSLe Ma #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 10914f727eceSLe Ma #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 10924f727eceSLe Ma #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL 10934f727eceSLe Ma #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L 10944f727eceSLe Ma #define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L 10954f727eceSLe Ma #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L 10964f727eceSLe Ma //SDMA0_ULV_CNTL 10974f727eceSLe Ma #define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 10984f727eceSLe Ma #define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b 10994f727eceSLe Ma #define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c 11004f727eceSLe Ma #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 11014f727eceSLe Ma #define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 11024f727eceSLe Ma #define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 11034f727eceSLe Ma #define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 11044f727eceSLe Ma #define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L 11054f727eceSLe Ma #define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L 11064f727eceSLe Ma #define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 11074f727eceSLe Ma #define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 11084f727eceSLe Ma #define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 11094f727eceSLe Ma //SDMA0_EA_DBIT_ADDR_DATA 11104f727eceSLe Ma #define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 11114f727eceSLe Ma #define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 11124f727eceSLe Ma //SDMA0_EA_DBIT_ADDR_INDEX 11134f727eceSLe Ma #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 11144f727eceSLe Ma #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 11154f727eceSLe Ma //SDMA0_GPU_IOV_VIOLATION_LOG2 11164f727eceSLe Ma #define SDMA0_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 11174f727eceSLe Ma #define SDMA0_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000000FFL 11184f727eceSLe Ma //SDMA0_GFX_RB_CNTL 11194f727eceSLe Ma #define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 11204f727eceSLe Ma #define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 11214f727eceSLe Ma #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 11224f727eceSLe Ma #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 11234f727eceSLe Ma #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 11244f727eceSLe Ma #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 11254f727eceSLe Ma #define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 11264f727eceSLe Ma #define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 11274f727eceSLe Ma #define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 11284f727eceSLe Ma #define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL 11294f727eceSLe Ma #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 11304f727eceSLe Ma #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 11314f727eceSLe Ma #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 11324f727eceSLe Ma #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 11334f727eceSLe Ma #define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 11344f727eceSLe Ma #define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 11354f727eceSLe Ma //SDMA0_GFX_RB_BASE 11364f727eceSLe Ma #define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 11374f727eceSLe Ma #define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 11384f727eceSLe Ma //SDMA0_GFX_RB_BASE_HI 11394f727eceSLe Ma #define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 11404f727eceSLe Ma #define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 11414f727eceSLe Ma //SDMA0_GFX_RB_RPTR 11424f727eceSLe Ma #define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 11434f727eceSLe Ma #define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 11444f727eceSLe Ma //SDMA0_GFX_RB_RPTR_HI 11454f727eceSLe Ma #define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 11464f727eceSLe Ma #define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 11474f727eceSLe Ma //SDMA0_GFX_RB_WPTR 11484f727eceSLe Ma #define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 11494f727eceSLe Ma #define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 11504f727eceSLe Ma //SDMA0_GFX_RB_WPTR_HI 11514f727eceSLe Ma #define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 11524f727eceSLe Ma #define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 11534f727eceSLe Ma //SDMA0_GFX_RB_WPTR_POLL_CNTL 11544f727eceSLe Ma #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 11554f727eceSLe Ma #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 11564f727eceSLe Ma #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 11574f727eceSLe Ma #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 11584f727eceSLe Ma #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 11594f727eceSLe Ma #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 11604f727eceSLe Ma #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 11614f727eceSLe Ma #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 11624f727eceSLe Ma #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 11634f727eceSLe Ma #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 11644f727eceSLe Ma //SDMA0_GFX_RB_RPTR_ADDR_HI 11654f727eceSLe Ma #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 11664f727eceSLe Ma #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 11674f727eceSLe Ma //SDMA0_GFX_RB_RPTR_ADDR_LO 11684f727eceSLe Ma #define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 11694f727eceSLe Ma #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 11704f727eceSLe Ma #define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 11714f727eceSLe Ma #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 11724f727eceSLe Ma //SDMA0_GFX_IB_CNTL 11734f727eceSLe Ma #define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 11744f727eceSLe Ma #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 11754f727eceSLe Ma #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 11764f727eceSLe Ma #define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 11774f727eceSLe Ma #define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 11784f727eceSLe Ma #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 11794f727eceSLe Ma #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 11804f727eceSLe Ma #define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 11814f727eceSLe Ma //SDMA0_GFX_IB_RPTR 11824f727eceSLe Ma #define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 11834f727eceSLe Ma #define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 11844f727eceSLe Ma //SDMA0_GFX_IB_OFFSET 11854f727eceSLe Ma #define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 11864f727eceSLe Ma #define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 11874f727eceSLe Ma //SDMA0_GFX_IB_BASE_LO 11884f727eceSLe Ma #define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 11894f727eceSLe Ma #define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 11904f727eceSLe Ma //SDMA0_GFX_IB_BASE_HI 11914f727eceSLe Ma #define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 11924f727eceSLe Ma #define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 11934f727eceSLe Ma //SDMA0_GFX_IB_SIZE 11944f727eceSLe Ma #define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 11954f727eceSLe Ma #define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 11964f727eceSLe Ma //SDMA0_GFX_SKIP_CNTL 11974f727eceSLe Ma #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 11984f727eceSLe Ma #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 11994f727eceSLe Ma //SDMA0_GFX_CONTEXT_STATUS 12004f727eceSLe Ma #define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 12014f727eceSLe Ma #define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 12024f727eceSLe Ma #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 12034f727eceSLe Ma #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 12044f727eceSLe Ma #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 12054f727eceSLe Ma #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 12064f727eceSLe Ma #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 12074f727eceSLe Ma #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 12084f727eceSLe Ma #define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 12094f727eceSLe Ma #define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 12104f727eceSLe Ma #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 12114f727eceSLe Ma #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 12124f727eceSLe Ma #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 12134f727eceSLe Ma #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 12144f727eceSLe Ma #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 12154f727eceSLe Ma #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 12164f727eceSLe Ma //SDMA0_GFX_DOORBELL 12174f727eceSLe Ma #define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c 12184f727eceSLe Ma #define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 12194f727eceSLe Ma #define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L 12204f727eceSLe Ma #define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 12214f727eceSLe Ma //SDMA0_GFX_CONTEXT_CNTL 12224f727eceSLe Ma #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 12234f727eceSLe Ma #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 12244f727eceSLe Ma //SDMA0_GFX_STATUS 12254f727eceSLe Ma #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 12264f727eceSLe Ma #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 12274f727eceSLe Ma #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 12284f727eceSLe Ma #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 12294f727eceSLe Ma //SDMA0_GFX_DOORBELL_LOG 12304f727eceSLe Ma #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 12314f727eceSLe Ma #define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 12324f727eceSLe Ma #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 12334f727eceSLe Ma #define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 12344f727eceSLe Ma //SDMA0_GFX_WATERMARK 12354f727eceSLe Ma #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 12364f727eceSLe Ma #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 12374f727eceSLe Ma #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 12384f727eceSLe Ma #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 12394f727eceSLe Ma //SDMA0_GFX_DOORBELL_OFFSET 12404f727eceSLe Ma #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 12414f727eceSLe Ma #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 12424f727eceSLe Ma //SDMA0_GFX_CSA_ADDR_LO 12434f727eceSLe Ma #define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 12444f727eceSLe Ma #define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 12454f727eceSLe Ma //SDMA0_GFX_CSA_ADDR_HI 12464f727eceSLe Ma #define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 12474f727eceSLe Ma #define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 12484f727eceSLe Ma //SDMA0_GFX_IB_SUB_REMAIN 12494f727eceSLe Ma #define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 12504f727eceSLe Ma #define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 12514f727eceSLe Ma //SDMA0_GFX_PREEMPT 12524f727eceSLe Ma #define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 12534f727eceSLe Ma #define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 12544f727eceSLe Ma //SDMA0_GFX_DUMMY_REG 12554f727eceSLe Ma #define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 12564f727eceSLe Ma #define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 12574f727eceSLe Ma //SDMA0_GFX_RB_WPTR_POLL_ADDR_HI 12584f727eceSLe Ma #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 12594f727eceSLe Ma #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 12604f727eceSLe Ma //SDMA0_GFX_RB_WPTR_POLL_ADDR_LO 12614f727eceSLe Ma #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 12624f727eceSLe Ma #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 12634f727eceSLe Ma //SDMA0_GFX_RB_AQL_CNTL 12644f727eceSLe Ma #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 12654f727eceSLe Ma #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 12664f727eceSLe Ma #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 12674f727eceSLe Ma #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 12684f727eceSLe Ma #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 12694f727eceSLe Ma #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 12704f727eceSLe Ma //SDMA0_GFX_MINOR_PTR_UPDATE 12714f727eceSLe Ma #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 12724f727eceSLe Ma #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 12734f727eceSLe Ma //SDMA0_GFX_MIDCMD_DATA0 12744f727eceSLe Ma #define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 12754f727eceSLe Ma #define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 12764f727eceSLe Ma //SDMA0_GFX_MIDCMD_DATA1 12774f727eceSLe Ma #define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 12784f727eceSLe Ma #define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 12794f727eceSLe Ma //SDMA0_GFX_MIDCMD_DATA2 12804f727eceSLe Ma #define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 12814f727eceSLe Ma #define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 12824f727eceSLe Ma //SDMA0_GFX_MIDCMD_DATA3 12834f727eceSLe Ma #define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 12844f727eceSLe Ma #define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 12854f727eceSLe Ma //SDMA0_GFX_MIDCMD_DATA4 12864f727eceSLe Ma #define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 12874f727eceSLe Ma #define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 12884f727eceSLe Ma //SDMA0_GFX_MIDCMD_DATA5 12894f727eceSLe Ma #define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 12904f727eceSLe Ma #define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 12914f727eceSLe Ma //SDMA0_GFX_MIDCMD_DATA6 12924f727eceSLe Ma #define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 12934f727eceSLe Ma #define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 12944f727eceSLe Ma //SDMA0_GFX_MIDCMD_DATA7 12954f727eceSLe Ma #define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 12964f727eceSLe Ma #define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 12974f727eceSLe Ma //SDMA0_GFX_MIDCMD_DATA8 12984f727eceSLe Ma #define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 12994f727eceSLe Ma #define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 13004f727eceSLe Ma //SDMA0_GFX_MIDCMD_CNTL 13014f727eceSLe Ma #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 13024f727eceSLe Ma #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 13034f727eceSLe Ma #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 13044f727eceSLe Ma #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 13054f727eceSLe Ma #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 13064f727eceSLe Ma #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 13074f727eceSLe Ma #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 13084f727eceSLe Ma #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 13094f727eceSLe Ma //SDMA0_PAGE_RB_CNTL 13104f727eceSLe Ma #define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 13114f727eceSLe Ma #define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 13124f727eceSLe Ma #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 13134f727eceSLe Ma #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 13144f727eceSLe Ma #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 13154f727eceSLe Ma #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 13164f727eceSLe Ma #define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 13174f727eceSLe Ma #define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 13184f727eceSLe Ma #define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 13194f727eceSLe Ma #define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL 13204f727eceSLe Ma #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 13214f727eceSLe Ma #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 13224f727eceSLe Ma #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 13234f727eceSLe Ma #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 13244f727eceSLe Ma #define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 13254f727eceSLe Ma #define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 13264f727eceSLe Ma //SDMA0_PAGE_RB_BASE 13274f727eceSLe Ma #define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0 13284f727eceSLe Ma #define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 13294f727eceSLe Ma //SDMA0_PAGE_RB_BASE_HI 13304f727eceSLe Ma #define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 13314f727eceSLe Ma #define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 13324f727eceSLe Ma //SDMA0_PAGE_RB_RPTR 13334f727eceSLe Ma #define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 13344f727eceSLe Ma #define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 13354f727eceSLe Ma //SDMA0_PAGE_RB_RPTR_HI 13364f727eceSLe Ma #define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 13374f727eceSLe Ma #define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 13384f727eceSLe Ma //SDMA0_PAGE_RB_WPTR 13394f727eceSLe Ma #define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 13404f727eceSLe Ma #define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 13414f727eceSLe Ma //SDMA0_PAGE_RB_WPTR_HI 13424f727eceSLe Ma #define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 13434f727eceSLe Ma #define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 13444f727eceSLe Ma //SDMA0_PAGE_RB_WPTR_POLL_CNTL 13454f727eceSLe Ma #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 13464f727eceSLe Ma #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 13474f727eceSLe Ma #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 13484f727eceSLe Ma #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 13494f727eceSLe Ma #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 13504f727eceSLe Ma #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 13514f727eceSLe Ma #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 13524f727eceSLe Ma #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 13534f727eceSLe Ma #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 13544f727eceSLe Ma #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 13554f727eceSLe Ma //SDMA0_PAGE_RB_RPTR_ADDR_HI 13564f727eceSLe Ma #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 13574f727eceSLe Ma #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 13584f727eceSLe Ma //SDMA0_PAGE_RB_RPTR_ADDR_LO 13594f727eceSLe Ma #define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 13604f727eceSLe Ma #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 13614f727eceSLe Ma #define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 13624f727eceSLe Ma #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 13634f727eceSLe Ma //SDMA0_PAGE_IB_CNTL 13644f727eceSLe Ma #define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 13654f727eceSLe Ma #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 13664f727eceSLe Ma #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 13674f727eceSLe Ma #define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 13684f727eceSLe Ma #define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 13694f727eceSLe Ma #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 13704f727eceSLe Ma #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 13714f727eceSLe Ma #define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 13724f727eceSLe Ma //SDMA0_PAGE_IB_RPTR 13734f727eceSLe Ma #define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 13744f727eceSLe Ma #define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 13754f727eceSLe Ma //SDMA0_PAGE_IB_OFFSET 13764f727eceSLe Ma #define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 13774f727eceSLe Ma #define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 13784f727eceSLe Ma //SDMA0_PAGE_IB_BASE_LO 13794f727eceSLe Ma #define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 13804f727eceSLe Ma #define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 13814f727eceSLe Ma //SDMA0_PAGE_IB_BASE_HI 13824f727eceSLe Ma #define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 13834f727eceSLe Ma #define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 13844f727eceSLe Ma //SDMA0_PAGE_IB_SIZE 13854f727eceSLe Ma #define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0 13864f727eceSLe Ma #define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 13874f727eceSLe Ma //SDMA0_PAGE_SKIP_CNTL 13884f727eceSLe Ma #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 13894f727eceSLe Ma #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 13904f727eceSLe Ma //SDMA0_PAGE_CONTEXT_STATUS 13914f727eceSLe Ma #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 13924f727eceSLe Ma #define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 13934f727eceSLe Ma #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 13944f727eceSLe Ma #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 13954f727eceSLe Ma #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 13964f727eceSLe Ma #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 13974f727eceSLe Ma #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 13984f727eceSLe Ma #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 13994f727eceSLe Ma #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 14004f727eceSLe Ma #define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 14014f727eceSLe Ma #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 14024f727eceSLe Ma #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 14034f727eceSLe Ma #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 14044f727eceSLe Ma #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 14054f727eceSLe Ma #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 14064f727eceSLe Ma #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 14074f727eceSLe Ma //SDMA0_PAGE_DOORBELL 14084f727eceSLe Ma #define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 14094f727eceSLe Ma #define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 14104f727eceSLe Ma #define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 14114f727eceSLe Ma #define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 14124f727eceSLe Ma //SDMA0_PAGE_STATUS 14134f727eceSLe Ma #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 14144f727eceSLe Ma #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 14154f727eceSLe Ma #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 14164f727eceSLe Ma #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 14174f727eceSLe Ma //SDMA0_PAGE_DOORBELL_LOG 14184f727eceSLe Ma #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 14194f727eceSLe Ma #define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 14204f727eceSLe Ma #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 14214f727eceSLe Ma #define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 14224f727eceSLe Ma //SDMA0_PAGE_WATERMARK 14234f727eceSLe Ma #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 14244f727eceSLe Ma #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 14254f727eceSLe Ma #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 14264f727eceSLe Ma #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 14274f727eceSLe Ma //SDMA0_PAGE_DOORBELL_OFFSET 14284f727eceSLe Ma #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 14294f727eceSLe Ma #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 14304f727eceSLe Ma //SDMA0_PAGE_CSA_ADDR_LO 14314f727eceSLe Ma #define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 14324f727eceSLe Ma #define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 14334f727eceSLe Ma //SDMA0_PAGE_CSA_ADDR_HI 14344f727eceSLe Ma #define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 14354f727eceSLe Ma #define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 14364f727eceSLe Ma //SDMA0_PAGE_IB_SUB_REMAIN 14374f727eceSLe Ma #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 14384f727eceSLe Ma #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 14394f727eceSLe Ma //SDMA0_PAGE_PREEMPT 14404f727eceSLe Ma #define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 14414f727eceSLe Ma #define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 14424f727eceSLe Ma //SDMA0_PAGE_DUMMY_REG 14434f727eceSLe Ma #define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 14444f727eceSLe Ma #define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 14454f727eceSLe Ma //SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 14464f727eceSLe Ma #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 14474f727eceSLe Ma #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 14484f727eceSLe Ma //SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 14494f727eceSLe Ma #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 14504f727eceSLe Ma #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 14514f727eceSLe Ma //SDMA0_PAGE_RB_AQL_CNTL 14524f727eceSLe Ma #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 14534f727eceSLe Ma #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 14544f727eceSLe Ma #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 14554f727eceSLe Ma #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 14564f727eceSLe Ma #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 14574f727eceSLe Ma #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 14584f727eceSLe Ma //SDMA0_PAGE_MINOR_PTR_UPDATE 14594f727eceSLe Ma #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 14604f727eceSLe Ma #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 14614f727eceSLe Ma //SDMA0_PAGE_MIDCMD_DATA0 14624f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 14634f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 14644f727eceSLe Ma //SDMA0_PAGE_MIDCMD_DATA1 14654f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 14664f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 14674f727eceSLe Ma //SDMA0_PAGE_MIDCMD_DATA2 14684f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 14694f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 14704f727eceSLe Ma //SDMA0_PAGE_MIDCMD_DATA3 14714f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 14724f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 14734f727eceSLe Ma //SDMA0_PAGE_MIDCMD_DATA4 14744f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 14754f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 14764f727eceSLe Ma //SDMA0_PAGE_MIDCMD_DATA5 14774f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 14784f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 14794f727eceSLe Ma //SDMA0_PAGE_MIDCMD_DATA6 14804f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 14814f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 14824f727eceSLe Ma //SDMA0_PAGE_MIDCMD_DATA7 14834f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 14844f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 14854f727eceSLe Ma //SDMA0_PAGE_MIDCMD_DATA8 14864f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 14874f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 14884f727eceSLe Ma //SDMA0_PAGE_MIDCMD_CNTL 14894f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 14904f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 14914f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 14924f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 14934f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 14944f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 14954f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 14964f727eceSLe Ma #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 14974f727eceSLe Ma //SDMA0_RLC0_RB_CNTL 14984f727eceSLe Ma #define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 14994f727eceSLe Ma #define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 15004f727eceSLe Ma #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 15014f727eceSLe Ma #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 15024f727eceSLe Ma #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 15034f727eceSLe Ma #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 15044f727eceSLe Ma #define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 15054f727eceSLe Ma #define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 15064f727eceSLe Ma #define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 15074f727eceSLe Ma #define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL 15084f727eceSLe Ma #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 15094f727eceSLe Ma #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 15104f727eceSLe Ma #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 15114f727eceSLe Ma #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 15124f727eceSLe Ma #define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 15134f727eceSLe Ma #define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 15144f727eceSLe Ma //SDMA0_RLC0_RB_BASE 15154f727eceSLe Ma #define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 15164f727eceSLe Ma #define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 15174f727eceSLe Ma //SDMA0_RLC0_RB_BASE_HI 15184f727eceSLe Ma #define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 15194f727eceSLe Ma #define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 15204f727eceSLe Ma //SDMA0_RLC0_RB_RPTR 15214f727eceSLe Ma #define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 15224f727eceSLe Ma #define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 15234f727eceSLe Ma //SDMA0_RLC0_RB_RPTR_HI 15244f727eceSLe Ma #define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 15254f727eceSLe Ma #define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 15264f727eceSLe Ma //SDMA0_RLC0_RB_WPTR 15274f727eceSLe Ma #define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 15284f727eceSLe Ma #define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 15294f727eceSLe Ma //SDMA0_RLC0_RB_WPTR_HI 15304f727eceSLe Ma #define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 15314f727eceSLe Ma #define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 15324f727eceSLe Ma //SDMA0_RLC0_RB_WPTR_POLL_CNTL 15334f727eceSLe Ma #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 15344f727eceSLe Ma #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 15354f727eceSLe Ma #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 15364f727eceSLe Ma #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 15374f727eceSLe Ma #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 15384f727eceSLe Ma #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 15394f727eceSLe Ma #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 15404f727eceSLe Ma #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 15414f727eceSLe Ma #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 15424f727eceSLe Ma #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 15434f727eceSLe Ma //SDMA0_RLC0_RB_RPTR_ADDR_HI 15444f727eceSLe Ma #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 15454f727eceSLe Ma #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 15464f727eceSLe Ma //SDMA0_RLC0_RB_RPTR_ADDR_LO 15474f727eceSLe Ma #define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 15484f727eceSLe Ma #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 15494f727eceSLe Ma #define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 15504f727eceSLe Ma #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 15514f727eceSLe Ma //SDMA0_RLC0_IB_CNTL 15524f727eceSLe Ma #define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 15534f727eceSLe Ma #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 15544f727eceSLe Ma #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 15554f727eceSLe Ma #define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 15564f727eceSLe Ma #define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 15574f727eceSLe Ma #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 15584f727eceSLe Ma #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 15594f727eceSLe Ma #define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 15604f727eceSLe Ma //SDMA0_RLC0_IB_RPTR 15614f727eceSLe Ma #define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 15624f727eceSLe Ma #define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 15634f727eceSLe Ma //SDMA0_RLC0_IB_OFFSET 15644f727eceSLe Ma #define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 15654f727eceSLe Ma #define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 15664f727eceSLe Ma //SDMA0_RLC0_IB_BASE_LO 15674f727eceSLe Ma #define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 15684f727eceSLe Ma #define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 15694f727eceSLe Ma //SDMA0_RLC0_IB_BASE_HI 15704f727eceSLe Ma #define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 15714f727eceSLe Ma #define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 15724f727eceSLe Ma //SDMA0_RLC0_IB_SIZE 15734f727eceSLe Ma #define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 15744f727eceSLe Ma #define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 15754f727eceSLe Ma //SDMA0_RLC0_SKIP_CNTL 15764f727eceSLe Ma #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 15774f727eceSLe Ma #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 15784f727eceSLe Ma //SDMA0_RLC0_CONTEXT_STATUS 15794f727eceSLe Ma #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 15804f727eceSLe Ma #define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 15814f727eceSLe Ma #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 15824f727eceSLe Ma #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 15834f727eceSLe Ma #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 15844f727eceSLe Ma #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 15854f727eceSLe Ma #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 15864f727eceSLe Ma #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 15874f727eceSLe Ma #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 15884f727eceSLe Ma #define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 15894f727eceSLe Ma #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 15904f727eceSLe Ma #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 15914f727eceSLe Ma #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 15924f727eceSLe Ma #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 15934f727eceSLe Ma #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 15944f727eceSLe Ma #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 15954f727eceSLe Ma //SDMA0_RLC0_DOORBELL 15964f727eceSLe Ma #define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 15974f727eceSLe Ma #define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 15984f727eceSLe Ma #define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 15994f727eceSLe Ma #define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 16004f727eceSLe Ma //SDMA0_RLC0_STATUS 16014f727eceSLe Ma #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 16024f727eceSLe Ma #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 16034f727eceSLe Ma #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 16044f727eceSLe Ma #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 16054f727eceSLe Ma //SDMA0_RLC0_DOORBELL_LOG 16064f727eceSLe Ma #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 16074f727eceSLe Ma #define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 16084f727eceSLe Ma #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 16094f727eceSLe Ma #define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 16104f727eceSLe Ma //SDMA0_RLC0_WATERMARK 16114f727eceSLe Ma #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 16124f727eceSLe Ma #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 16134f727eceSLe Ma #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 16144f727eceSLe Ma #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 16154f727eceSLe Ma //SDMA0_RLC0_DOORBELL_OFFSET 16164f727eceSLe Ma #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 16174f727eceSLe Ma #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 16184f727eceSLe Ma //SDMA0_RLC0_CSA_ADDR_LO 16194f727eceSLe Ma #define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 16204f727eceSLe Ma #define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 16214f727eceSLe Ma //SDMA0_RLC0_CSA_ADDR_HI 16224f727eceSLe Ma #define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 16234f727eceSLe Ma #define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 16244f727eceSLe Ma //SDMA0_RLC0_IB_SUB_REMAIN 16254f727eceSLe Ma #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 16264f727eceSLe Ma #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 16274f727eceSLe Ma //SDMA0_RLC0_PREEMPT 16284f727eceSLe Ma #define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 16294f727eceSLe Ma #define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 16304f727eceSLe Ma //SDMA0_RLC0_DUMMY_REG 16314f727eceSLe Ma #define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 16324f727eceSLe Ma #define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 16334f727eceSLe Ma //SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 16344f727eceSLe Ma #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 16354f727eceSLe Ma #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 16364f727eceSLe Ma //SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 16374f727eceSLe Ma #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 16384f727eceSLe Ma #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 16394f727eceSLe Ma //SDMA0_RLC0_RB_AQL_CNTL 16404f727eceSLe Ma #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 16414f727eceSLe Ma #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 16424f727eceSLe Ma #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 16434f727eceSLe Ma #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 16444f727eceSLe Ma #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 16454f727eceSLe Ma #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 16464f727eceSLe Ma //SDMA0_RLC0_MINOR_PTR_UPDATE 16474f727eceSLe Ma #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 16484f727eceSLe Ma #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 16494f727eceSLe Ma //SDMA0_RLC0_MIDCMD_DATA0 16504f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 16514f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 16524f727eceSLe Ma //SDMA0_RLC0_MIDCMD_DATA1 16534f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 16544f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 16554f727eceSLe Ma //SDMA0_RLC0_MIDCMD_DATA2 16564f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 16574f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 16584f727eceSLe Ma //SDMA0_RLC0_MIDCMD_DATA3 16594f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 16604f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 16614f727eceSLe Ma //SDMA0_RLC0_MIDCMD_DATA4 16624f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 16634f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 16644f727eceSLe Ma //SDMA0_RLC0_MIDCMD_DATA5 16654f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 16664f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 16674f727eceSLe Ma //SDMA0_RLC0_MIDCMD_DATA6 16684f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 16694f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 16704f727eceSLe Ma //SDMA0_RLC0_MIDCMD_DATA7 16714f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 16724f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 16734f727eceSLe Ma //SDMA0_RLC0_MIDCMD_DATA8 16744f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 16754f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 16764f727eceSLe Ma //SDMA0_RLC0_MIDCMD_CNTL 16774f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 16784f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 16794f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 16804f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 16814f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 16824f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 16834f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 16844f727eceSLe Ma #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 16854f727eceSLe Ma //SDMA0_RLC1_RB_CNTL 16864f727eceSLe Ma #define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 16874f727eceSLe Ma #define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 16884f727eceSLe Ma #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 16894f727eceSLe Ma #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 16904f727eceSLe Ma #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 16914f727eceSLe Ma #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 16924f727eceSLe Ma #define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 16934f727eceSLe Ma #define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 16944f727eceSLe Ma #define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 16954f727eceSLe Ma #define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL 16964f727eceSLe Ma #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 16974f727eceSLe Ma #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 16984f727eceSLe Ma #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 16994f727eceSLe Ma #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 17004f727eceSLe Ma #define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 17014f727eceSLe Ma #define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 17024f727eceSLe Ma //SDMA0_RLC1_RB_BASE 17034f727eceSLe Ma #define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 17044f727eceSLe Ma #define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 17054f727eceSLe Ma //SDMA0_RLC1_RB_BASE_HI 17064f727eceSLe Ma #define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 17074f727eceSLe Ma #define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 17084f727eceSLe Ma //SDMA0_RLC1_RB_RPTR 17094f727eceSLe Ma #define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 17104f727eceSLe Ma #define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 17114f727eceSLe Ma //SDMA0_RLC1_RB_RPTR_HI 17124f727eceSLe Ma #define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 17134f727eceSLe Ma #define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 17144f727eceSLe Ma //SDMA0_RLC1_RB_WPTR 17154f727eceSLe Ma #define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 17164f727eceSLe Ma #define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 17174f727eceSLe Ma //SDMA0_RLC1_RB_WPTR_HI 17184f727eceSLe Ma #define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 17194f727eceSLe Ma #define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 17204f727eceSLe Ma //SDMA0_RLC1_RB_WPTR_POLL_CNTL 17214f727eceSLe Ma #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 17224f727eceSLe Ma #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 17234f727eceSLe Ma #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 17244f727eceSLe Ma #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 17254f727eceSLe Ma #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 17264f727eceSLe Ma #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 17274f727eceSLe Ma #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 17284f727eceSLe Ma #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 17294f727eceSLe Ma #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 17304f727eceSLe Ma #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 17314f727eceSLe Ma //SDMA0_RLC1_RB_RPTR_ADDR_HI 17324f727eceSLe Ma #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 17334f727eceSLe Ma #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 17344f727eceSLe Ma //SDMA0_RLC1_RB_RPTR_ADDR_LO 17354f727eceSLe Ma #define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 17364f727eceSLe Ma #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 17374f727eceSLe Ma #define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 17384f727eceSLe Ma #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 17394f727eceSLe Ma //SDMA0_RLC1_IB_CNTL 17404f727eceSLe Ma #define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 17414f727eceSLe Ma #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 17424f727eceSLe Ma #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 17434f727eceSLe Ma #define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 17444f727eceSLe Ma #define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 17454f727eceSLe Ma #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 17464f727eceSLe Ma #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 17474f727eceSLe Ma #define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 17484f727eceSLe Ma //SDMA0_RLC1_IB_RPTR 17494f727eceSLe Ma #define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 17504f727eceSLe Ma #define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 17514f727eceSLe Ma //SDMA0_RLC1_IB_OFFSET 17524f727eceSLe Ma #define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 17534f727eceSLe Ma #define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 17544f727eceSLe Ma //SDMA0_RLC1_IB_BASE_LO 17554f727eceSLe Ma #define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 17564f727eceSLe Ma #define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 17574f727eceSLe Ma //SDMA0_RLC1_IB_BASE_HI 17584f727eceSLe Ma #define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 17594f727eceSLe Ma #define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 17604f727eceSLe Ma //SDMA0_RLC1_IB_SIZE 17614f727eceSLe Ma #define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 17624f727eceSLe Ma #define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 17634f727eceSLe Ma //SDMA0_RLC1_SKIP_CNTL 17644f727eceSLe Ma #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 17654f727eceSLe Ma #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 17664f727eceSLe Ma //SDMA0_RLC1_CONTEXT_STATUS 17674f727eceSLe Ma #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 17684f727eceSLe Ma #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 17694f727eceSLe Ma #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 17704f727eceSLe Ma #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 17714f727eceSLe Ma #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 17724f727eceSLe Ma #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 17734f727eceSLe Ma #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 17744f727eceSLe Ma #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 17754f727eceSLe Ma #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 17764f727eceSLe Ma #define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 17774f727eceSLe Ma #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 17784f727eceSLe Ma #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 17794f727eceSLe Ma #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 17804f727eceSLe Ma #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 17814f727eceSLe Ma #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 17824f727eceSLe Ma #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 17834f727eceSLe Ma //SDMA0_RLC1_DOORBELL 17844f727eceSLe Ma #define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 17854f727eceSLe Ma #define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 17864f727eceSLe Ma #define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 17874f727eceSLe Ma #define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 17884f727eceSLe Ma //SDMA0_RLC1_STATUS 17894f727eceSLe Ma #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 17904f727eceSLe Ma #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 17914f727eceSLe Ma #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 17924f727eceSLe Ma #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 17934f727eceSLe Ma //SDMA0_RLC1_DOORBELL_LOG 17944f727eceSLe Ma #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 17954f727eceSLe Ma #define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 17964f727eceSLe Ma #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 17974f727eceSLe Ma #define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 17984f727eceSLe Ma //SDMA0_RLC1_WATERMARK 17994f727eceSLe Ma #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 18004f727eceSLe Ma #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 18014f727eceSLe Ma #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 18024f727eceSLe Ma #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 18034f727eceSLe Ma //SDMA0_RLC1_DOORBELL_OFFSET 18044f727eceSLe Ma #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 18054f727eceSLe Ma #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 18064f727eceSLe Ma //SDMA0_RLC1_CSA_ADDR_LO 18074f727eceSLe Ma #define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 18084f727eceSLe Ma #define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 18094f727eceSLe Ma //SDMA0_RLC1_CSA_ADDR_HI 18104f727eceSLe Ma #define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 18114f727eceSLe Ma #define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 18124f727eceSLe Ma //SDMA0_RLC1_IB_SUB_REMAIN 18134f727eceSLe Ma #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 18144f727eceSLe Ma #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 18154f727eceSLe Ma //SDMA0_RLC1_PREEMPT 18164f727eceSLe Ma #define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 18174f727eceSLe Ma #define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 18184f727eceSLe Ma //SDMA0_RLC1_DUMMY_REG 18194f727eceSLe Ma #define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 18204f727eceSLe Ma #define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 18214f727eceSLe Ma //SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 18224f727eceSLe Ma #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 18234f727eceSLe Ma #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 18244f727eceSLe Ma //SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 18254f727eceSLe Ma #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 18264f727eceSLe Ma #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 18274f727eceSLe Ma //SDMA0_RLC1_RB_AQL_CNTL 18284f727eceSLe Ma #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 18294f727eceSLe Ma #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 18304f727eceSLe Ma #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 18314f727eceSLe Ma #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 18324f727eceSLe Ma #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 18334f727eceSLe Ma #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 18344f727eceSLe Ma //SDMA0_RLC1_MINOR_PTR_UPDATE 18354f727eceSLe Ma #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 18364f727eceSLe Ma #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 18374f727eceSLe Ma //SDMA0_RLC1_MIDCMD_DATA0 18384f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 18394f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 18404f727eceSLe Ma //SDMA0_RLC1_MIDCMD_DATA1 18414f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 18424f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 18434f727eceSLe Ma //SDMA0_RLC1_MIDCMD_DATA2 18444f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 18454f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 18464f727eceSLe Ma //SDMA0_RLC1_MIDCMD_DATA3 18474f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 18484f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 18494f727eceSLe Ma //SDMA0_RLC1_MIDCMD_DATA4 18504f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 18514f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 18524f727eceSLe Ma //SDMA0_RLC1_MIDCMD_DATA5 18534f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 18544f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 18554f727eceSLe Ma //SDMA0_RLC1_MIDCMD_DATA6 18564f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 18574f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 18584f727eceSLe Ma //SDMA0_RLC1_MIDCMD_DATA7 18594f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 18604f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 18614f727eceSLe Ma //SDMA0_RLC1_MIDCMD_DATA8 18624f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 18634f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 18644f727eceSLe Ma //SDMA0_RLC1_MIDCMD_CNTL 18654f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 18664f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 18674f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 18684f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 18694f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 18704f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 18714f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 18724f727eceSLe Ma #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 18734f727eceSLe Ma //SDMA0_RLC2_RB_CNTL 18744f727eceSLe Ma #define SDMA0_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 18754f727eceSLe Ma #define SDMA0_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 18764f727eceSLe Ma #define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 18774f727eceSLe Ma #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 18784f727eceSLe Ma #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 18794f727eceSLe Ma #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 18804f727eceSLe Ma #define SDMA0_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 18814f727eceSLe Ma #define SDMA0_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 18824f727eceSLe Ma #define SDMA0_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L 18834f727eceSLe Ma #define SDMA0_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL 18844f727eceSLe Ma #define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 18854f727eceSLe Ma #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 18864f727eceSLe Ma #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 18874f727eceSLe Ma #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 18884f727eceSLe Ma #define SDMA0_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L 18894f727eceSLe Ma #define SDMA0_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L 18904f727eceSLe Ma //SDMA0_RLC2_RB_BASE 18914f727eceSLe Ma #define SDMA0_RLC2_RB_BASE__ADDR__SHIFT 0x0 18924f727eceSLe Ma #define SDMA0_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL 18934f727eceSLe Ma //SDMA0_RLC2_RB_BASE_HI 18944f727eceSLe Ma #define SDMA0_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 18954f727eceSLe Ma #define SDMA0_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 18964f727eceSLe Ma //SDMA0_RLC2_RB_RPTR 18974f727eceSLe Ma #define SDMA0_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 18984f727eceSLe Ma #define SDMA0_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 18994f727eceSLe Ma //SDMA0_RLC2_RB_RPTR_HI 19004f727eceSLe Ma #define SDMA0_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 19014f727eceSLe Ma #define SDMA0_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 19024f727eceSLe Ma //SDMA0_RLC2_RB_WPTR 19034f727eceSLe Ma #define SDMA0_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 19044f727eceSLe Ma #define SDMA0_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 19054f727eceSLe Ma //SDMA0_RLC2_RB_WPTR_HI 19064f727eceSLe Ma #define SDMA0_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 19074f727eceSLe Ma #define SDMA0_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 19084f727eceSLe Ma //SDMA0_RLC2_RB_WPTR_POLL_CNTL 19094f727eceSLe Ma #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 19104f727eceSLe Ma #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 19114f727eceSLe Ma #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 19124f727eceSLe Ma #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 19134f727eceSLe Ma #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 19144f727eceSLe Ma #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 19154f727eceSLe Ma #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 19164f727eceSLe Ma #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 19174f727eceSLe Ma #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 19184f727eceSLe Ma #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 19194f727eceSLe Ma //SDMA0_RLC2_RB_RPTR_ADDR_HI 19204f727eceSLe Ma #define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 19214f727eceSLe Ma #define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 19224f727eceSLe Ma //SDMA0_RLC2_RB_RPTR_ADDR_LO 19234f727eceSLe Ma #define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 19244f727eceSLe Ma #define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 19254f727eceSLe Ma #define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 19264f727eceSLe Ma #define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 19274f727eceSLe Ma //SDMA0_RLC2_IB_CNTL 19284f727eceSLe Ma #define SDMA0_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 19294f727eceSLe Ma #define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 19304f727eceSLe Ma #define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 19314f727eceSLe Ma #define SDMA0_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 19324f727eceSLe Ma #define SDMA0_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L 19334f727eceSLe Ma #define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 19344f727eceSLe Ma #define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 19354f727eceSLe Ma #define SDMA0_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L 19364f727eceSLe Ma //SDMA0_RLC2_IB_RPTR 19374f727eceSLe Ma #define SDMA0_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 19384f727eceSLe Ma #define SDMA0_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL 19394f727eceSLe Ma //SDMA0_RLC2_IB_OFFSET 19404f727eceSLe Ma #define SDMA0_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 19414f727eceSLe Ma #define SDMA0_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 19424f727eceSLe Ma //SDMA0_RLC2_IB_BASE_LO 19434f727eceSLe Ma #define SDMA0_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 19444f727eceSLe Ma #define SDMA0_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 19454f727eceSLe Ma //SDMA0_RLC2_IB_BASE_HI 19464f727eceSLe Ma #define SDMA0_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 19474f727eceSLe Ma #define SDMA0_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 19484f727eceSLe Ma //SDMA0_RLC2_IB_SIZE 19494f727eceSLe Ma #define SDMA0_RLC2_IB_SIZE__SIZE__SHIFT 0x0 19504f727eceSLe Ma #define SDMA0_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL 19514f727eceSLe Ma //SDMA0_RLC2_SKIP_CNTL 19524f727eceSLe Ma #define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 19534f727eceSLe Ma #define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 19544f727eceSLe Ma //SDMA0_RLC2_CONTEXT_STATUS 19554f727eceSLe Ma #define SDMA0_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 19564f727eceSLe Ma #define SDMA0_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 19574f727eceSLe Ma #define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 19584f727eceSLe Ma #define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 19594f727eceSLe Ma #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 19604f727eceSLe Ma #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 19614f727eceSLe Ma #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 19624f727eceSLe Ma #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 19634f727eceSLe Ma #define SDMA0_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 19644f727eceSLe Ma #define SDMA0_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L 19654f727eceSLe Ma #define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 19664f727eceSLe Ma #define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 19674f727eceSLe Ma #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 19684f727eceSLe Ma #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 19694f727eceSLe Ma #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 19704f727eceSLe Ma #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 19714f727eceSLe Ma //SDMA0_RLC2_DOORBELL 19724f727eceSLe Ma #define SDMA0_RLC2_DOORBELL__ENABLE__SHIFT 0x1c 19734f727eceSLe Ma #define SDMA0_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e 19744f727eceSLe Ma #define SDMA0_RLC2_DOORBELL__ENABLE_MASK 0x10000000L 19754f727eceSLe Ma #define SDMA0_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L 19764f727eceSLe Ma //SDMA0_RLC2_STATUS 19774f727eceSLe Ma #define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 19784f727eceSLe Ma #define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 19794f727eceSLe Ma #define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 19804f727eceSLe Ma #define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 19814f727eceSLe Ma //SDMA0_RLC2_DOORBELL_LOG 19824f727eceSLe Ma #define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 19834f727eceSLe Ma #define SDMA0_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 19844f727eceSLe Ma #define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 19854f727eceSLe Ma #define SDMA0_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 19864f727eceSLe Ma //SDMA0_RLC2_WATERMARK 19874f727eceSLe Ma #define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 19884f727eceSLe Ma #define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 19894f727eceSLe Ma #define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 19904f727eceSLe Ma #define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 19914f727eceSLe Ma //SDMA0_RLC2_DOORBELL_OFFSET 19924f727eceSLe Ma #define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 19934f727eceSLe Ma #define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 19944f727eceSLe Ma //SDMA0_RLC2_CSA_ADDR_LO 19954f727eceSLe Ma #define SDMA0_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 19964f727eceSLe Ma #define SDMA0_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 19974f727eceSLe Ma //SDMA0_RLC2_CSA_ADDR_HI 19984f727eceSLe Ma #define SDMA0_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 19994f727eceSLe Ma #define SDMA0_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 20004f727eceSLe Ma //SDMA0_RLC2_IB_SUB_REMAIN 20014f727eceSLe Ma #define SDMA0_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 20024f727eceSLe Ma #define SDMA0_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 20034f727eceSLe Ma //SDMA0_RLC2_PREEMPT 20044f727eceSLe Ma #define SDMA0_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 20054f727eceSLe Ma #define SDMA0_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L 20064f727eceSLe Ma //SDMA0_RLC2_DUMMY_REG 20074f727eceSLe Ma #define SDMA0_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 20084f727eceSLe Ma #define SDMA0_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 20094f727eceSLe Ma //SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI 20104f727eceSLe Ma #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 20114f727eceSLe Ma #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 20124f727eceSLe Ma //SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO 20134f727eceSLe Ma #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 20144f727eceSLe Ma #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 20154f727eceSLe Ma //SDMA0_RLC2_RB_AQL_CNTL 20164f727eceSLe Ma #define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 20174f727eceSLe Ma #define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 20184f727eceSLe Ma #define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 20194f727eceSLe Ma #define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 20204f727eceSLe Ma #define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 20214f727eceSLe Ma #define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 20224f727eceSLe Ma //SDMA0_RLC2_MINOR_PTR_UPDATE 20234f727eceSLe Ma #define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 20244f727eceSLe Ma #define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 20254f727eceSLe Ma //SDMA0_RLC2_MIDCMD_DATA0 20264f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 20274f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 20284f727eceSLe Ma //SDMA0_RLC2_MIDCMD_DATA1 20294f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 20304f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 20314f727eceSLe Ma //SDMA0_RLC2_MIDCMD_DATA2 20324f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 20334f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 20344f727eceSLe Ma //SDMA0_RLC2_MIDCMD_DATA3 20354f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 20364f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 20374f727eceSLe Ma //SDMA0_RLC2_MIDCMD_DATA4 20384f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 20394f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 20404f727eceSLe Ma //SDMA0_RLC2_MIDCMD_DATA5 20414f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 20424f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 20434f727eceSLe Ma //SDMA0_RLC2_MIDCMD_DATA6 20444f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 20454f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 20464f727eceSLe Ma //SDMA0_RLC2_MIDCMD_DATA7 20474f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 20484f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 20494f727eceSLe Ma //SDMA0_RLC2_MIDCMD_DATA8 20504f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 20514f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 20524f727eceSLe Ma //SDMA0_RLC2_MIDCMD_CNTL 20534f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 20544f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 20554f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 20564f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 20574f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 20584f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 20594f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 20604f727eceSLe Ma #define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 20614f727eceSLe Ma //SDMA0_RLC3_RB_CNTL 20624f727eceSLe Ma #define SDMA0_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 20634f727eceSLe Ma #define SDMA0_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 20644f727eceSLe Ma #define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 20654f727eceSLe Ma #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 20664f727eceSLe Ma #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 20674f727eceSLe Ma #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 20684f727eceSLe Ma #define SDMA0_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 20694f727eceSLe Ma #define SDMA0_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 20704f727eceSLe Ma #define SDMA0_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L 20714f727eceSLe Ma #define SDMA0_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL 20724f727eceSLe Ma #define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 20734f727eceSLe Ma #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 20744f727eceSLe Ma #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 20754f727eceSLe Ma #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 20764f727eceSLe Ma #define SDMA0_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L 20774f727eceSLe Ma #define SDMA0_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L 20784f727eceSLe Ma //SDMA0_RLC3_RB_BASE 20794f727eceSLe Ma #define SDMA0_RLC3_RB_BASE__ADDR__SHIFT 0x0 20804f727eceSLe Ma #define SDMA0_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL 20814f727eceSLe Ma //SDMA0_RLC3_RB_BASE_HI 20824f727eceSLe Ma #define SDMA0_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 20834f727eceSLe Ma #define SDMA0_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 20844f727eceSLe Ma //SDMA0_RLC3_RB_RPTR 20854f727eceSLe Ma #define SDMA0_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 20864f727eceSLe Ma #define SDMA0_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 20874f727eceSLe Ma //SDMA0_RLC3_RB_RPTR_HI 20884f727eceSLe Ma #define SDMA0_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 20894f727eceSLe Ma #define SDMA0_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 20904f727eceSLe Ma //SDMA0_RLC3_RB_WPTR 20914f727eceSLe Ma #define SDMA0_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 20924f727eceSLe Ma #define SDMA0_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 20934f727eceSLe Ma //SDMA0_RLC3_RB_WPTR_HI 20944f727eceSLe Ma #define SDMA0_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 20954f727eceSLe Ma #define SDMA0_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 20964f727eceSLe Ma //SDMA0_RLC3_RB_WPTR_POLL_CNTL 20974f727eceSLe Ma #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 20984f727eceSLe Ma #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 20994f727eceSLe Ma #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 21004f727eceSLe Ma #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 21014f727eceSLe Ma #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 21024f727eceSLe Ma #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 21034f727eceSLe Ma #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 21044f727eceSLe Ma #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 21054f727eceSLe Ma #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 21064f727eceSLe Ma #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 21074f727eceSLe Ma //SDMA0_RLC3_RB_RPTR_ADDR_HI 21084f727eceSLe Ma #define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 21094f727eceSLe Ma #define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 21104f727eceSLe Ma //SDMA0_RLC3_RB_RPTR_ADDR_LO 21114f727eceSLe Ma #define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 21124f727eceSLe Ma #define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 21134f727eceSLe Ma #define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 21144f727eceSLe Ma #define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 21154f727eceSLe Ma //SDMA0_RLC3_IB_CNTL 21164f727eceSLe Ma #define SDMA0_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 21174f727eceSLe Ma #define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 21184f727eceSLe Ma #define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 21194f727eceSLe Ma #define SDMA0_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 21204f727eceSLe Ma #define SDMA0_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L 21214f727eceSLe Ma #define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 21224f727eceSLe Ma #define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 21234f727eceSLe Ma #define SDMA0_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L 21244f727eceSLe Ma //SDMA0_RLC3_IB_RPTR 21254f727eceSLe Ma #define SDMA0_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 21264f727eceSLe Ma #define SDMA0_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL 21274f727eceSLe Ma //SDMA0_RLC3_IB_OFFSET 21284f727eceSLe Ma #define SDMA0_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 21294f727eceSLe Ma #define SDMA0_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 21304f727eceSLe Ma //SDMA0_RLC3_IB_BASE_LO 21314f727eceSLe Ma #define SDMA0_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 21324f727eceSLe Ma #define SDMA0_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 21334f727eceSLe Ma //SDMA0_RLC3_IB_BASE_HI 21344f727eceSLe Ma #define SDMA0_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 21354f727eceSLe Ma #define SDMA0_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 21364f727eceSLe Ma //SDMA0_RLC3_IB_SIZE 21374f727eceSLe Ma #define SDMA0_RLC3_IB_SIZE__SIZE__SHIFT 0x0 21384f727eceSLe Ma #define SDMA0_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL 21394f727eceSLe Ma //SDMA0_RLC3_SKIP_CNTL 21404f727eceSLe Ma #define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 21414f727eceSLe Ma #define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 21424f727eceSLe Ma //SDMA0_RLC3_CONTEXT_STATUS 21434f727eceSLe Ma #define SDMA0_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 21444f727eceSLe Ma #define SDMA0_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 21454f727eceSLe Ma #define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 21464f727eceSLe Ma #define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 21474f727eceSLe Ma #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 21484f727eceSLe Ma #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 21494f727eceSLe Ma #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 21504f727eceSLe Ma #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 21514f727eceSLe Ma #define SDMA0_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 21524f727eceSLe Ma #define SDMA0_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L 21534f727eceSLe Ma #define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 21544f727eceSLe Ma #define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 21554f727eceSLe Ma #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 21564f727eceSLe Ma #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 21574f727eceSLe Ma #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 21584f727eceSLe Ma #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 21594f727eceSLe Ma //SDMA0_RLC3_DOORBELL 21604f727eceSLe Ma #define SDMA0_RLC3_DOORBELL__ENABLE__SHIFT 0x1c 21614f727eceSLe Ma #define SDMA0_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e 21624f727eceSLe Ma #define SDMA0_RLC3_DOORBELL__ENABLE_MASK 0x10000000L 21634f727eceSLe Ma #define SDMA0_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L 21644f727eceSLe Ma //SDMA0_RLC3_STATUS 21654f727eceSLe Ma #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 21664f727eceSLe Ma #define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 21674f727eceSLe Ma #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 21684f727eceSLe Ma #define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 21694f727eceSLe Ma //SDMA0_RLC3_DOORBELL_LOG 21704f727eceSLe Ma #define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 21714f727eceSLe Ma #define SDMA0_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 21724f727eceSLe Ma #define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 21734f727eceSLe Ma #define SDMA0_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 21744f727eceSLe Ma //SDMA0_RLC3_WATERMARK 21754f727eceSLe Ma #define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 21764f727eceSLe Ma #define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 21774f727eceSLe Ma #define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 21784f727eceSLe Ma #define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 21794f727eceSLe Ma //SDMA0_RLC3_DOORBELL_OFFSET 21804f727eceSLe Ma #define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 21814f727eceSLe Ma #define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 21824f727eceSLe Ma //SDMA0_RLC3_CSA_ADDR_LO 21834f727eceSLe Ma #define SDMA0_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 21844f727eceSLe Ma #define SDMA0_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 21854f727eceSLe Ma //SDMA0_RLC3_CSA_ADDR_HI 21864f727eceSLe Ma #define SDMA0_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 21874f727eceSLe Ma #define SDMA0_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 21884f727eceSLe Ma //SDMA0_RLC3_IB_SUB_REMAIN 21894f727eceSLe Ma #define SDMA0_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 21904f727eceSLe Ma #define SDMA0_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 21914f727eceSLe Ma //SDMA0_RLC3_PREEMPT 21924f727eceSLe Ma #define SDMA0_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 21934f727eceSLe Ma #define SDMA0_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L 21944f727eceSLe Ma //SDMA0_RLC3_DUMMY_REG 21954f727eceSLe Ma #define SDMA0_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 21964f727eceSLe Ma #define SDMA0_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 21974f727eceSLe Ma //SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI 21984f727eceSLe Ma #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 21994f727eceSLe Ma #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 22004f727eceSLe Ma //SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO 22014f727eceSLe Ma #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 22024f727eceSLe Ma #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 22034f727eceSLe Ma //SDMA0_RLC3_RB_AQL_CNTL 22044f727eceSLe Ma #define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 22054f727eceSLe Ma #define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 22064f727eceSLe Ma #define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 22074f727eceSLe Ma #define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 22084f727eceSLe Ma #define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 22094f727eceSLe Ma #define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 22104f727eceSLe Ma //SDMA0_RLC3_MINOR_PTR_UPDATE 22114f727eceSLe Ma #define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 22124f727eceSLe Ma #define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 22134f727eceSLe Ma //SDMA0_RLC3_MIDCMD_DATA0 22144f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 22154f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 22164f727eceSLe Ma //SDMA0_RLC3_MIDCMD_DATA1 22174f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 22184f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 22194f727eceSLe Ma //SDMA0_RLC3_MIDCMD_DATA2 22204f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 22214f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 22224f727eceSLe Ma //SDMA0_RLC3_MIDCMD_DATA3 22234f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 22244f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 22254f727eceSLe Ma //SDMA0_RLC3_MIDCMD_DATA4 22264f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 22274f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 22284f727eceSLe Ma //SDMA0_RLC3_MIDCMD_DATA5 22294f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 22304f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 22314f727eceSLe Ma //SDMA0_RLC3_MIDCMD_DATA6 22324f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 22334f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 22344f727eceSLe Ma //SDMA0_RLC3_MIDCMD_DATA7 22354f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 22364f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 22374f727eceSLe Ma //SDMA0_RLC3_MIDCMD_DATA8 22384f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 22394f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 22404f727eceSLe Ma //SDMA0_RLC3_MIDCMD_CNTL 22414f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 22424f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 22434f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 22444f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 22454f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 22464f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 22474f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 22484f727eceSLe Ma #define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 22494f727eceSLe Ma //SDMA0_RLC4_RB_CNTL 22504f727eceSLe Ma #define SDMA0_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 22514f727eceSLe Ma #define SDMA0_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 22524f727eceSLe Ma #define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 22534f727eceSLe Ma #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 22544f727eceSLe Ma #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 22554f727eceSLe Ma #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 22564f727eceSLe Ma #define SDMA0_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 22574f727eceSLe Ma #define SDMA0_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 22584f727eceSLe Ma #define SDMA0_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L 22594f727eceSLe Ma #define SDMA0_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL 22604f727eceSLe Ma #define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 22614f727eceSLe Ma #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 22624f727eceSLe Ma #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 22634f727eceSLe Ma #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 22644f727eceSLe Ma #define SDMA0_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L 22654f727eceSLe Ma #define SDMA0_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L 22664f727eceSLe Ma //SDMA0_RLC4_RB_BASE 22674f727eceSLe Ma #define SDMA0_RLC4_RB_BASE__ADDR__SHIFT 0x0 22684f727eceSLe Ma #define SDMA0_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL 22694f727eceSLe Ma //SDMA0_RLC4_RB_BASE_HI 22704f727eceSLe Ma #define SDMA0_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 22714f727eceSLe Ma #define SDMA0_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 22724f727eceSLe Ma //SDMA0_RLC4_RB_RPTR 22734f727eceSLe Ma #define SDMA0_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 22744f727eceSLe Ma #define SDMA0_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 22754f727eceSLe Ma //SDMA0_RLC4_RB_RPTR_HI 22764f727eceSLe Ma #define SDMA0_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 22774f727eceSLe Ma #define SDMA0_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 22784f727eceSLe Ma //SDMA0_RLC4_RB_WPTR 22794f727eceSLe Ma #define SDMA0_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 22804f727eceSLe Ma #define SDMA0_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 22814f727eceSLe Ma //SDMA0_RLC4_RB_WPTR_HI 22824f727eceSLe Ma #define SDMA0_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 22834f727eceSLe Ma #define SDMA0_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 22844f727eceSLe Ma //SDMA0_RLC4_RB_WPTR_POLL_CNTL 22854f727eceSLe Ma #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 22864f727eceSLe Ma #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 22874f727eceSLe Ma #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 22884f727eceSLe Ma #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 22894f727eceSLe Ma #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 22904f727eceSLe Ma #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 22914f727eceSLe Ma #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 22924f727eceSLe Ma #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 22934f727eceSLe Ma #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 22944f727eceSLe Ma #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 22954f727eceSLe Ma //SDMA0_RLC4_RB_RPTR_ADDR_HI 22964f727eceSLe Ma #define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 22974f727eceSLe Ma #define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 22984f727eceSLe Ma //SDMA0_RLC4_RB_RPTR_ADDR_LO 22994f727eceSLe Ma #define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 23004f727eceSLe Ma #define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 23014f727eceSLe Ma #define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 23024f727eceSLe Ma #define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 23034f727eceSLe Ma //SDMA0_RLC4_IB_CNTL 23044f727eceSLe Ma #define SDMA0_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 23054f727eceSLe Ma #define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 23064f727eceSLe Ma #define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 23074f727eceSLe Ma #define SDMA0_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 23084f727eceSLe Ma #define SDMA0_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L 23094f727eceSLe Ma #define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 23104f727eceSLe Ma #define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 23114f727eceSLe Ma #define SDMA0_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L 23124f727eceSLe Ma //SDMA0_RLC4_IB_RPTR 23134f727eceSLe Ma #define SDMA0_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 23144f727eceSLe Ma #define SDMA0_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL 23154f727eceSLe Ma //SDMA0_RLC4_IB_OFFSET 23164f727eceSLe Ma #define SDMA0_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 23174f727eceSLe Ma #define SDMA0_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 23184f727eceSLe Ma //SDMA0_RLC4_IB_BASE_LO 23194f727eceSLe Ma #define SDMA0_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 23204f727eceSLe Ma #define SDMA0_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 23214f727eceSLe Ma //SDMA0_RLC4_IB_BASE_HI 23224f727eceSLe Ma #define SDMA0_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 23234f727eceSLe Ma #define SDMA0_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 23244f727eceSLe Ma //SDMA0_RLC4_IB_SIZE 23254f727eceSLe Ma #define SDMA0_RLC4_IB_SIZE__SIZE__SHIFT 0x0 23264f727eceSLe Ma #define SDMA0_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL 23274f727eceSLe Ma //SDMA0_RLC4_SKIP_CNTL 23284f727eceSLe Ma #define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 23294f727eceSLe Ma #define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 23304f727eceSLe Ma //SDMA0_RLC4_CONTEXT_STATUS 23314f727eceSLe Ma #define SDMA0_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 23324f727eceSLe Ma #define SDMA0_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 23334f727eceSLe Ma #define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 23344f727eceSLe Ma #define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 23354f727eceSLe Ma #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 23364f727eceSLe Ma #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 23374f727eceSLe Ma #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 23384f727eceSLe Ma #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 23394f727eceSLe Ma #define SDMA0_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 23404f727eceSLe Ma #define SDMA0_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L 23414f727eceSLe Ma #define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 23424f727eceSLe Ma #define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 23434f727eceSLe Ma #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 23444f727eceSLe Ma #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 23454f727eceSLe Ma #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 23464f727eceSLe Ma #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 23474f727eceSLe Ma //SDMA0_RLC4_DOORBELL 23484f727eceSLe Ma #define SDMA0_RLC4_DOORBELL__ENABLE__SHIFT 0x1c 23494f727eceSLe Ma #define SDMA0_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e 23504f727eceSLe Ma #define SDMA0_RLC4_DOORBELL__ENABLE_MASK 0x10000000L 23514f727eceSLe Ma #define SDMA0_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L 23524f727eceSLe Ma //SDMA0_RLC4_STATUS 23534f727eceSLe Ma #define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 23544f727eceSLe Ma #define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 23554f727eceSLe Ma #define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 23564f727eceSLe Ma #define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 23574f727eceSLe Ma //SDMA0_RLC4_DOORBELL_LOG 23584f727eceSLe Ma #define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 23594f727eceSLe Ma #define SDMA0_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 23604f727eceSLe Ma #define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 23614f727eceSLe Ma #define SDMA0_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 23624f727eceSLe Ma //SDMA0_RLC4_WATERMARK 23634f727eceSLe Ma #define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 23644f727eceSLe Ma #define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 23654f727eceSLe Ma #define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 23664f727eceSLe Ma #define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 23674f727eceSLe Ma //SDMA0_RLC4_DOORBELL_OFFSET 23684f727eceSLe Ma #define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 23694f727eceSLe Ma #define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 23704f727eceSLe Ma //SDMA0_RLC4_CSA_ADDR_LO 23714f727eceSLe Ma #define SDMA0_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 23724f727eceSLe Ma #define SDMA0_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 23734f727eceSLe Ma //SDMA0_RLC4_CSA_ADDR_HI 23744f727eceSLe Ma #define SDMA0_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 23754f727eceSLe Ma #define SDMA0_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 23764f727eceSLe Ma //SDMA0_RLC4_IB_SUB_REMAIN 23774f727eceSLe Ma #define SDMA0_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 23784f727eceSLe Ma #define SDMA0_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 23794f727eceSLe Ma //SDMA0_RLC4_PREEMPT 23804f727eceSLe Ma #define SDMA0_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 23814f727eceSLe Ma #define SDMA0_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L 23824f727eceSLe Ma //SDMA0_RLC4_DUMMY_REG 23834f727eceSLe Ma #define SDMA0_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 23844f727eceSLe Ma #define SDMA0_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 23854f727eceSLe Ma //SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI 23864f727eceSLe Ma #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 23874f727eceSLe Ma #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 23884f727eceSLe Ma //SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO 23894f727eceSLe Ma #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 23904f727eceSLe Ma #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 23914f727eceSLe Ma //SDMA0_RLC4_RB_AQL_CNTL 23924f727eceSLe Ma #define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 23934f727eceSLe Ma #define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 23944f727eceSLe Ma #define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 23954f727eceSLe Ma #define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 23964f727eceSLe Ma #define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 23974f727eceSLe Ma #define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 23984f727eceSLe Ma //SDMA0_RLC4_MINOR_PTR_UPDATE 23994f727eceSLe Ma #define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 24004f727eceSLe Ma #define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 24014f727eceSLe Ma //SDMA0_RLC4_MIDCMD_DATA0 24024f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 24034f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 24044f727eceSLe Ma //SDMA0_RLC4_MIDCMD_DATA1 24054f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 24064f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 24074f727eceSLe Ma //SDMA0_RLC4_MIDCMD_DATA2 24084f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 24094f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 24104f727eceSLe Ma //SDMA0_RLC4_MIDCMD_DATA3 24114f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 24124f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 24134f727eceSLe Ma //SDMA0_RLC4_MIDCMD_DATA4 24144f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 24154f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 24164f727eceSLe Ma //SDMA0_RLC4_MIDCMD_DATA5 24174f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 24184f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 24194f727eceSLe Ma //SDMA0_RLC4_MIDCMD_DATA6 24204f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 24214f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 24224f727eceSLe Ma //SDMA0_RLC4_MIDCMD_DATA7 24234f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 24244f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 24254f727eceSLe Ma //SDMA0_RLC4_MIDCMD_DATA8 24264f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 24274f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 24284f727eceSLe Ma //SDMA0_RLC4_MIDCMD_CNTL 24294f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 24304f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 24314f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 24324f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 24334f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 24344f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 24354f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 24364f727eceSLe Ma #define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 24374f727eceSLe Ma //SDMA0_RLC5_RB_CNTL 24384f727eceSLe Ma #define SDMA0_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 24394f727eceSLe Ma #define SDMA0_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 24404f727eceSLe Ma #define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 24414f727eceSLe Ma #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 24424f727eceSLe Ma #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 24434f727eceSLe Ma #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 24444f727eceSLe Ma #define SDMA0_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 24454f727eceSLe Ma #define SDMA0_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 24464f727eceSLe Ma #define SDMA0_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L 24474f727eceSLe Ma #define SDMA0_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL 24484f727eceSLe Ma #define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 24494f727eceSLe Ma #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 24504f727eceSLe Ma #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 24514f727eceSLe Ma #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 24524f727eceSLe Ma #define SDMA0_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L 24534f727eceSLe Ma #define SDMA0_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L 24544f727eceSLe Ma //SDMA0_RLC5_RB_BASE 24554f727eceSLe Ma #define SDMA0_RLC5_RB_BASE__ADDR__SHIFT 0x0 24564f727eceSLe Ma #define SDMA0_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL 24574f727eceSLe Ma //SDMA0_RLC5_RB_BASE_HI 24584f727eceSLe Ma #define SDMA0_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 24594f727eceSLe Ma #define SDMA0_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 24604f727eceSLe Ma //SDMA0_RLC5_RB_RPTR 24614f727eceSLe Ma #define SDMA0_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 24624f727eceSLe Ma #define SDMA0_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 24634f727eceSLe Ma //SDMA0_RLC5_RB_RPTR_HI 24644f727eceSLe Ma #define SDMA0_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 24654f727eceSLe Ma #define SDMA0_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 24664f727eceSLe Ma //SDMA0_RLC5_RB_WPTR 24674f727eceSLe Ma #define SDMA0_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 24684f727eceSLe Ma #define SDMA0_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 24694f727eceSLe Ma //SDMA0_RLC5_RB_WPTR_HI 24704f727eceSLe Ma #define SDMA0_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 24714f727eceSLe Ma #define SDMA0_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 24724f727eceSLe Ma //SDMA0_RLC5_RB_WPTR_POLL_CNTL 24734f727eceSLe Ma #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 24744f727eceSLe Ma #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 24754f727eceSLe Ma #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 24764f727eceSLe Ma #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 24774f727eceSLe Ma #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 24784f727eceSLe Ma #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 24794f727eceSLe Ma #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 24804f727eceSLe Ma #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 24814f727eceSLe Ma #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 24824f727eceSLe Ma #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 24834f727eceSLe Ma //SDMA0_RLC5_RB_RPTR_ADDR_HI 24844f727eceSLe Ma #define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 24854f727eceSLe Ma #define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 24864f727eceSLe Ma //SDMA0_RLC5_RB_RPTR_ADDR_LO 24874f727eceSLe Ma #define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 24884f727eceSLe Ma #define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 24894f727eceSLe Ma #define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 24904f727eceSLe Ma #define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 24914f727eceSLe Ma //SDMA0_RLC5_IB_CNTL 24924f727eceSLe Ma #define SDMA0_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 24934f727eceSLe Ma #define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 24944f727eceSLe Ma #define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 24954f727eceSLe Ma #define SDMA0_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 24964f727eceSLe Ma #define SDMA0_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L 24974f727eceSLe Ma #define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 24984f727eceSLe Ma #define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 24994f727eceSLe Ma #define SDMA0_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L 25004f727eceSLe Ma //SDMA0_RLC5_IB_RPTR 25014f727eceSLe Ma #define SDMA0_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 25024f727eceSLe Ma #define SDMA0_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL 25034f727eceSLe Ma //SDMA0_RLC5_IB_OFFSET 25044f727eceSLe Ma #define SDMA0_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 25054f727eceSLe Ma #define SDMA0_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 25064f727eceSLe Ma //SDMA0_RLC5_IB_BASE_LO 25074f727eceSLe Ma #define SDMA0_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 25084f727eceSLe Ma #define SDMA0_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 25094f727eceSLe Ma //SDMA0_RLC5_IB_BASE_HI 25104f727eceSLe Ma #define SDMA0_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 25114f727eceSLe Ma #define SDMA0_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 25124f727eceSLe Ma //SDMA0_RLC5_IB_SIZE 25134f727eceSLe Ma #define SDMA0_RLC5_IB_SIZE__SIZE__SHIFT 0x0 25144f727eceSLe Ma #define SDMA0_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL 25154f727eceSLe Ma //SDMA0_RLC5_SKIP_CNTL 25164f727eceSLe Ma #define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 25174f727eceSLe Ma #define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 25184f727eceSLe Ma //SDMA0_RLC5_CONTEXT_STATUS 25194f727eceSLe Ma #define SDMA0_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 25204f727eceSLe Ma #define SDMA0_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 25214f727eceSLe Ma #define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 25224f727eceSLe Ma #define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 25234f727eceSLe Ma #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 25244f727eceSLe Ma #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 25254f727eceSLe Ma #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 25264f727eceSLe Ma #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 25274f727eceSLe Ma #define SDMA0_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 25284f727eceSLe Ma #define SDMA0_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L 25294f727eceSLe Ma #define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 25304f727eceSLe Ma #define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 25314f727eceSLe Ma #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 25324f727eceSLe Ma #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 25334f727eceSLe Ma #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 25344f727eceSLe Ma #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 25354f727eceSLe Ma //SDMA0_RLC5_DOORBELL 25364f727eceSLe Ma #define SDMA0_RLC5_DOORBELL__ENABLE__SHIFT 0x1c 25374f727eceSLe Ma #define SDMA0_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e 25384f727eceSLe Ma #define SDMA0_RLC5_DOORBELL__ENABLE_MASK 0x10000000L 25394f727eceSLe Ma #define SDMA0_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L 25404f727eceSLe Ma //SDMA0_RLC5_STATUS 25414f727eceSLe Ma #define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 25424f727eceSLe Ma #define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 25434f727eceSLe Ma #define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 25444f727eceSLe Ma #define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 25454f727eceSLe Ma //SDMA0_RLC5_DOORBELL_LOG 25464f727eceSLe Ma #define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 25474f727eceSLe Ma #define SDMA0_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 25484f727eceSLe Ma #define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 25494f727eceSLe Ma #define SDMA0_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 25504f727eceSLe Ma //SDMA0_RLC5_WATERMARK 25514f727eceSLe Ma #define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 25524f727eceSLe Ma #define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 25534f727eceSLe Ma #define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 25544f727eceSLe Ma #define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 25554f727eceSLe Ma //SDMA0_RLC5_DOORBELL_OFFSET 25564f727eceSLe Ma #define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 25574f727eceSLe Ma #define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 25584f727eceSLe Ma //SDMA0_RLC5_CSA_ADDR_LO 25594f727eceSLe Ma #define SDMA0_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 25604f727eceSLe Ma #define SDMA0_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 25614f727eceSLe Ma //SDMA0_RLC5_CSA_ADDR_HI 25624f727eceSLe Ma #define SDMA0_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 25634f727eceSLe Ma #define SDMA0_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 25644f727eceSLe Ma //SDMA0_RLC5_IB_SUB_REMAIN 25654f727eceSLe Ma #define SDMA0_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 25664f727eceSLe Ma #define SDMA0_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 25674f727eceSLe Ma //SDMA0_RLC5_PREEMPT 25684f727eceSLe Ma #define SDMA0_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 25694f727eceSLe Ma #define SDMA0_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L 25704f727eceSLe Ma //SDMA0_RLC5_DUMMY_REG 25714f727eceSLe Ma #define SDMA0_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 25724f727eceSLe Ma #define SDMA0_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 25734f727eceSLe Ma //SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI 25744f727eceSLe Ma #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 25754f727eceSLe Ma #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 25764f727eceSLe Ma //SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO 25774f727eceSLe Ma #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 25784f727eceSLe Ma #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 25794f727eceSLe Ma //SDMA0_RLC5_RB_AQL_CNTL 25804f727eceSLe Ma #define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 25814f727eceSLe Ma #define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 25824f727eceSLe Ma #define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 25834f727eceSLe Ma #define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 25844f727eceSLe Ma #define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 25854f727eceSLe Ma #define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 25864f727eceSLe Ma //SDMA0_RLC5_MINOR_PTR_UPDATE 25874f727eceSLe Ma #define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 25884f727eceSLe Ma #define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 25894f727eceSLe Ma //SDMA0_RLC5_MIDCMD_DATA0 25904f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 25914f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 25924f727eceSLe Ma //SDMA0_RLC5_MIDCMD_DATA1 25934f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 25944f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 25954f727eceSLe Ma //SDMA0_RLC5_MIDCMD_DATA2 25964f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 25974f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 25984f727eceSLe Ma //SDMA0_RLC5_MIDCMD_DATA3 25994f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 26004f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 26014f727eceSLe Ma //SDMA0_RLC5_MIDCMD_DATA4 26024f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 26034f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 26044f727eceSLe Ma //SDMA0_RLC5_MIDCMD_DATA5 26054f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 26064f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 26074f727eceSLe Ma //SDMA0_RLC5_MIDCMD_DATA6 26084f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 26094f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 26104f727eceSLe Ma //SDMA0_RLC5_MIDCMD_DATA7 26114f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 26124f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 26134f727eceSLe Ma //SDMA0_RLC5_MIDCMD_DATA8 26144f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 26154f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 26164f727eceSLe Ma //SDMA0_RLC5_MIDCMD_CNTL 26174f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 26184f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 26194f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 26204f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 26214f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 26224f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 26234f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 26244f727eceSLe Ma #define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 26254f727eceSLe Ma //SDMA0_RLC6_RB_CNTL 26264f727eceSLe Ma #define SDMA0_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 26274f727eceSLe Ma #define SDMA0_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 26284f727eceSLe Ma #define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 26294f727eceSLe Ma #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 26304f727eceSLe Ma #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 26314f727eceSLe Ma #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 26324f727eceSLe Ma #define SDMA0_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 26334f727eceSLe Ma #define SDMA0_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 26344f727eceSLe Ma #define SDMA0_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L 26354f727eceSLe Ma #define SDMA0_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL 26364f727eceSLe Ma #define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 26374f727eceSLe Ma #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 26384f727eceSLe Ma #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 26394f727eceSLe Ma #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 26404f727eceSLe Ma #define SDMA0_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L 26414f727eceSLe Ma #define SDMA0_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L 26424f727eceSLe Ma //SDMA0_RLC6_RB_BASE 26434f727eceSLe Ma #define SDMA0_RLC6_RB_BASE__ADDR__SHIFT 0x0 26444f727eceSLe Ma #define SDMA0_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL 26454f727eceSLe Ma //SDMA0_RLC6_RB_BASE_HI 26464f727eceSLe Ma #define SDMA0_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 26474f727eceSLe Ma #define SDMA0_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 26484f727eceSLe Ma //SDMA0_RLC6_RB_RPTR 26494f727eceSLe Ma #define SDMA0_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 26504f727eceSLe Ma #define SDMA0_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 26514f727eceSLe Ma //SDMA0_RLC6_RB_RPTR_HI 26524f727eceSLe Ma #define SDMA0_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 26534f727eceSLe Ma #define SDMA0_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 26544f727eceSLe Ma //SDMA0_RLC6_RB_WPTR 26554f727eceSLe Ma #define SDMA0_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 26564f727eceSLe Ma #define SDMA0_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 26574f727eceSLe Ma //SDMA0_RLC6_RB_WPTR_HI 26584f727eceSLe Ma #define SDMA0_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 26594f727eceSLe Ma #define SDMA0_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 26604f727eceSLe Ma //SDMA0_RLC6_RB_WPTR_POLL_CNTL 26614f727eceSLe Ma #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 26624f727eceSLe Ma #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 26634f727eceSLe Ma #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 26644f727eceSLe Ma #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 26654f727eceSLe Ma #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 26664f727eceSLe Ma #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 26674f727eceSLe Ma #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 26684f727eceSLe Ma #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 26694f727eceSLe Ma #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 26704f727eceSLe Ma #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 26714f727eceSLe Ma //SDMA0_RLC6_RB_RPTR_ADDR_HI 26724f727eceSLe Ma #define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 26734f727eceSLe Ma #define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 26744f727eceSLe Ma //SDMA0_RLC6_RB_RPTR_ADDR_LO 26754f727eceSLe Ma #define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 26764f727eceSLe Ma #define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 26774f727eceSLe Ma #define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 26784f727eceSLe Ma #define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 26794f727eceSLe Ma //SDMA0_RLC6_IB_CNTL 26804f727eceSLe Ma #define SDMA0_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 26814f727eceSLe Ma #define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 26824f727eceSLe Ma #define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 26834f727eceSLe Ma #define SDMA0_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 26844f727eceSLe Ma #define SDMA0_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L 26854f727eceSLe Ma #define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 26864f727eceSLe Ma #define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 26874f727eceSLe Ma #define SDMA0_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L 26884f727eceSLe Ma //SDMA0_RLC6_IB_RPTR 26894f727eceSLe Ma #define SDMA0_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 26904f727eceSLe Ma #define SDMA0_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL 26914f727eceSLe Ma //SDMA0_RLC6_IB_OFFSET 26924f727eceSLe Ma #define SDMA0_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 26934f727eceSLe Ma #define SDMA0_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 26944f727eceSLe Ma //SDMA0_RLC6_IB_BASE_LO 26954f727eceSLe Ma #define SDMA0_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 26964f727eceSLe Ma #define SDMA0_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 26974f727eceSLe Ma //SDMA0_RLC6_IB_BASE_HI 26984f727eceSLe Ma #define SDMA0_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 26994f727eceSLe Ma #define SDMA0_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 27004f727eceSLe Ma //SDMA0_RLC6_IB_SIZE 27014f727eceSLe Ma #define SDMA0_RLC6_IB_SIZE__SIZE__SHIFT 0x0 27024f727eceSLe Ma #define SDMA0_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL 27034f727eceSLe Ma //SDMA0_RLC6_SKIP_CNTL 27044f727eceSLe Ma #define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 27054f727eceSLe Ma #define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 27064f727eceSLe Ma //SDMA0_RLC6_CONTEXT_STATUS 27074f727eceSLe Ma #define SDMA0_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 27084f727eceSLe Ma #define SDMA0_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 27094f727eceSLe Ma #define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 27104f727eceSLe Ma #define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 27114f727eceSLe Ma #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 27124f727eceSLe Ma #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 27134f727eceSLe Ma #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 27144f727eceSLe Ma #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 27154f727eceSLe Ma #define SDMA0_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 27164f727eceSLe Ma #define SDMA0_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L 27174f727eceSLe Ma #define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 27184f727eceSLe Ma #define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 27194f727eceSLe Ma #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 27204f727eceSLe Ma #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 27214f727eceSLe Ma #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 27224f727eceSLe Ma #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 27234f727eceSLe Ma //SDMA0_RLC6_DOORBELL 27244f727eceSLe Ma #define SDMA0_RLC6_DOORBELL__ENABLE__SHIFT 0x1c 27254f727eceSLe Ma #define SDMA0_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e 27264f727eceSLe Ma #define SDMA0_RLC6_DOORBELL__ENABLE_MASK 0x10000000L 27274f727eceSLe Ma #define SDMA0_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L 27284f727eceSLe Ma //SDMA0_RLC6_STATUS 27294f727eceSLe Ma #define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 27304f727eceSLe Ma #define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 27314f727eceSLe Ma #define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 27324f727eceSLe Ma #define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 27334f727eceSLe Ma //SDMA0_RLC6_DOORBELL_LOG 27344f727eceSLe Ma #define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 27354f727eceSLe Ma #define SDMA0_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 27364f727eceSLe Ma #define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 27374f727eceSLe Ma #define SDMA0_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 27384f727eceSLe Ma //SDMA0_RLC6_WATERMARK 27394f727eceSLe Ma #define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 27404f727eceSLe Ma #define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 27414f727eceSLe Ma #define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 27424f727eceSLe Ma #define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 27434f727eceSLe Ma //SDMA0_RLC6_DOORBELL_OFFSET 27444f727eceSLe Ma #define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 27454f727eceSLe Ma #define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 27464f727eceSLe Ma //SDMA0_RLC6_CSA_ADDR_LO 27474f727eceSLe Ma #define SDMA0_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 27484f727eceSLe Ma #define SDMA0_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 27494f727eceSLe Ma //SDMA0_RLC6_CSA_ADDR_HI 27504f727eceSLe Ma #define SDMA0_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 27514f727eceSLe Ma #define SDMA0_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 27524f727eceSLe Ma //SDMA0_RLC6_IB_SUB_REMAIN 27534f727eceSLe Ma #define SDMA0_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 27544f727eceSLe Ma #define SDMA0_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 27554f727eceSLe Ma //SDMA0_RLC6_PREEMPT 27564f727eceSLe Ma #define SDMA0_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 27574f727eceSLe Ma #define SDMA0_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L 27584f727eceSLe Ma //SDMA0_RLC6_DUMMY_REG 27594f727eceSLe Ma #define SDMA0_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 27604f727eceSLe Ma #define SDMA0_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 27614f727eceSLe Ma //SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI 27624f727eceSLe Ma #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 27634f727eceSLe Ma #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 27644f727eceSLe Ma //SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO 27654f727eceSLe Ma #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 27664f727eceSLe Ma #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 27674f727eceSLe Ma //SDMA0_RLC6_RB_AQL_CNTL 27684f727eceSLe Ma #define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 27694f727eceSLe Ma #define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 27704f727eceSLe Ma #define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 27714f727eceSLe Ma #define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 27724f727eceSLe Ma #define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 27734f727eceSLe Ma #define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 27744f727eceSLe Ma //SDMA0_RLC6_MINOR_PTR_UPDATE 27754f727eceSLe Ma #define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 27764f727eceSLe Ma #define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 27774f727eceSLe Ma //SDMA0_RLC6_MIDCMD_DATA0 27784f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 27794f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 27804f727eceSLe Ma //SDMA0_RLC6_MIDCMD_DATA1 27814f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 27824f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 27834f727eceSLe Ma //SDMA0_RLC6_MIDCMD_DATA2 27844f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 27854f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 27864f727eceSLe Ma //SDMA0_RLC6_MIDCMD_DATA3 27874f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 27884f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 27894f727eceSLe Ma //SDMA0_RLC6_MIDCMD_DATA4 27904f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 27914f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 27924f727eceSLe Ma //SDMA0_RLC6_MIDCMD_DATA5 27934f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 27944f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 27954f727eceSLe Ma //SDMA0_RLC6_MIDCMD_DATA6 27964f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 27974f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 27984f727eceSLe Ma //SDMA0_RLC6_MIDCMD_DATA7 27994f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 28004f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 28014f727eceSLe Ma //SDMA0_RLC6_MIDCMD_DATA8 28024f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 28034f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 28044f727eceSLe Ma //SDMA0_RLC6_MIDCMD_CNTL 28054f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 28064f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 28074f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 28084f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 28094f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 28104f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 28114f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 28124f727eceSLe Ma #define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 28134f727eceSLe Ma //SDMA0_RLC7_RB_CNTL 28144f727eceSLe Ma #define SDMA0_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 28154f727eceSLe Ma #define SDMA0_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 28164f727eceSLe Ma #define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 28174f727eceSLe Ma #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 28184f727eceSLe Ma #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 28194f727eceSLe Ma #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 28204f727eceSLe Ma #define SDMA0_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 28214f727eceSLe Ma #define SDMA0_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 28224f727eceSLe Ma #define SDMA0_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L 28234f727eceSLe Ma #define SDMA0_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL 28244f727eceSLe Ma #define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 28254f727eceSLe Ma #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 28264f727eceSLe Ma #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 28274f727eceSLe Ma #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 28284f727eceSLe Ma #define SDMA0_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L 28294f727eceSLe Ma #define SDMA0_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L 28304f727eceSLe Ma //SDMA0_RLC7_RB_BASE 28314f727eceSLe Ma #define SDMA0_RLC7_RB_BASE__ADDR__SHIFT 0x0 28324f727eceSLe Ma #define SDMA0_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL 28334f727eceSLe Ma //SDMA0_RLC7_RB_BASE_HI 28344f727eceSLe Ma #define SDMA0_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 28354f727eceSLe Ma #define SDMA0_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 28364f727eceSLe Ma //SDMA0_RLC7_RB_RPTR 28374f727eceSLe Ma #define SDMA0_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 28384f727eceSLe Ma #define SDMA0_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 28394f727eceSLe Ma //SDMA0_RLC7_RB_RPTR_HI 28404f727eceSLe Ma #define SDMA0_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 28414f727eceSLe Ma #define SDMA0_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 28424f727eceSLe Ma //SDMA0_RLC7_RB_WPTR 28434f727eceSLe Ma #define SDMA0_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 28444f727eceSLe Ma #define SDMA0_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 28454f727eceSLe Ma //SDMA0_RLC7_RB_WPTR_HI 28464f727eceSLe Ma #define SDMA0_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 28474f727eceSLe Ma #define SDMA0_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 28484f727eceSLe Ma //SDMA0_RLC7_RB_WPTR_POLL_CNTL 28494f727eceSLe Ma #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 28504f727eceSLe Ma #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 28514f727eceSLe Ma #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 28524f727eceSLe Ma #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 28534f727eceSLe Ma #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 28544f727eceSLe Ma #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 28554f727eceSLe Ma #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 28564f727eceSLe Ma #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 28574f727eceSLe Ma #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 28584f727eceSLe Ma #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 28594f727eceSLe Ma //SDMA0_RLC7_RB_RPTR_ADDR_HI 28604f727eceSLe Ma #define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 28614f727eceSLe Ma #define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 28624f727eceSLe Ma //SDMA0_RLC7_RB_RPTR_ADDR_LO 28634f727eceSLe Ma #define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 28644f727eceSLe Ma #define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 28654f727eceSLe Ma #define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 28664f727eceSLe Ma #define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 28674f727eceSLe Ma //SDMA0_RLC7_IB_CNTL 28684f727eceSLe Ma #define SDMA0_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 28694f727eceSLe Ma #define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 28704f727eceSLe Ma #define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 28714f727eceSLe Ma #define SDMA0_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 28724f727eceSLe Ma #define SDMA0_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L 28734f727eceSLe Ma #define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 28744f727eceSLe Ma #define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 28754f727eceSLe Ma #define SDMA0_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L 28764f727eceSLe Ma //SDMA0_RLC7_IB_RPTR 28774f727eceSLe Ma #define SDMA0_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 28784f727eceSLe Ma #define SDMA0_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL 28794f727eceSLe Ma //SDMA0_RLC7_IB_OFFSET 28804f727eceSLe Ma #define SDMA0_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 28814f727eceSLe Ma #define SDMA0_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 28824f727eceSLe Ma //SDMA0_RLC7_IB_BASE_LO 28834f727eceSLe Ma #define SDMA0_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 28844f727eceSLe Ma #define SDMA0_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 28854f727eceSLe Ma //SDMA0_RLC7_IB_BASE_HI 28864f727eceSLe Ma #define SDMA0_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 28874f727eceSLe Ma #define SDMA0_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 28884f727eceSLe Ma //SDMA0_RLC7_IB_SIZE 28894f727eceSLe Ma #define SDMA0_RLC7_IB_SIZE__SIZE__SHIFT 0x0 28904f727eceSLe Ma #define SDMA0_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL 28914f727eceSLe Ma //SDMA0_RLC7_SKIP_CNTL 28924f727eceSLe Ma #define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 28934f727eceSLe Ma #define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 28944f727eceSLe Ma //SDMA0_RLC7_CONTEXT_STATUS 28954f727eceSLe Ma #define SDMA0_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 28964f727eceSLe Ma #define SDMA0_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 28974f727eceSLe Ma #define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 28984f727eceSLe Ma #define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 28994f727eceSLe Ma #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 29004f727eceSLe Ma #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 29014f727eceSLe Ma #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 29024f727eceSLe Ma #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 29034f727eceSLe Ma #define SDMA0_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 29044f727eceSLe Ma #define SDMA0_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L 29054f727eceSLe Ma #define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 29064f727eceSLe Ma #define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 29074f727eceSLe Ma #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 29084f727eceSLe Ma #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 29094f727eceSLe Ma #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 29104f727eceSLe Ma #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 29114f727eceSLe Ma //SDMA0_RLC7_DOORBELL 29124f727eceSLe Ma #define SDMA0_RLC7_DOORBELL__ENABLE__SHIFT 0x1c 29134f727eceSLe Ma #define SDMA0_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e 29144f727eceSLe Ma #define SDMA0_RLC7_DOORBELL__ENABLE_MASK 0x10000000L 29154f727eceSLe Ma #define SDMA0_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L 29164f727eceSLe Ma //SDMA0_RLC7_STATUS 29174f727eceSLe Ma #define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 29184f727eceSLe Ma #define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 29194f727eceSLe Ma #define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 29204f727eceSLe Ma #define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 29214f727eceSLe Ma //SDMA0_RLC7_DOORBELL_LOG 29224f727eceSLe Ma #define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 29234f727eceSLe Ma #define SDMA0_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 29244f727eceSLe Ma #define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 29254f727eceSLe Ma #define SDMA0_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 29264f727eceSLe Ma //SDMA0_RLC7_WATERMARK 29274f727eceSLe Ma #define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 29284f727eceSLe Ma #define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 29294f727eceSLe Ma #define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 29304f727eceSLe Ma #define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 29314f727eceSLe Ma //SDMA0_RLC7_DOORBELL_OFFSET 29324f727eceSLe Ma #define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 29334f727eceSLe Ma #define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 29344f727eceSLe Ma //SDMA0_RLC7_CSA_ADDR_LO 29354f727eceSLe Ma #define SDMA0_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 29364f727eceSLe Ma #define SDMA0_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 29374f727eceSLe Ma //SDMA0_RLC7_CSA_ADDR_HI 29384f727eceSLe Ma #define SDMA0_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 29394f727eceSLe Ma #define SDMA0_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 29404f727eceSLe Ma //SDMA0_RLC7_IB_SUB_REMAIN 29414f727eceSLe Ma #define SDMA0_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 29424f727eceSLe Ma #define SDMA0_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 29434f727eceSLe Ma //SDMA0_RLC7_PREEMPT 29444f727eceSLe Ma #define SDMA0_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 29454f727eceSLe Ma #define SDMA0_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L 29464f727eceSLe Ma //SDMA0_RLC7_DUMMY_REG 29474f727eceSLe Ma #define SDMA0_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 29484f727eceSLe Ma #define SDMA0_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 29494f727eceSLe Ma //SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI 29504f727eceSLe Ma #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 29514f727eceSLe Ma #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 29524f727eceSLe Ma //SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO 29534f727eceSLe Ma #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 29544f727eceSLe Ma #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 29554f727eceSLe Ma //SDMA0_RLC7_RB_AQL_CNTL 29564f727eceSLe Ma #define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 29574f727eceSLe Ma #define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 29584f727eceSLe Ma #define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 29594f727eceSLe Ma #define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 29604f727eceSLe Ma #define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 29614f727eceSLe Ma #define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 29624f727eceSLe Ma //SDMA0_RLC7_MINOR_PTR_UPDATE 29634f727eceSLe Ma #define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 29644f727eceSLe Ma #define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 29654f727eceSLe Ma //SDMA0_RLC7_MIDCMD_DATA0 29664f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 29674f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 29684f727eceSLe Ma //SDMA0_RLC7_MIDCMD_DATA1 29694f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 29704f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 29714f727eceSLe Ma //SDMA0_RLC7_MIDCMD_DATA2 29724f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 29734f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 29744f727eceSLe Ma //SDMA0_RLC7_MIDCMD_DATA3 29754f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 29764f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 29774f727eceSLe Ma //SDMA0_RLC7_MIDCMD_DATA4 29784f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 29794f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 29804f727eceSLe Ma //SDMA0_RLC7_MIDCMD_DATA5 29814f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 29824f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 29834f727eceSLe Ma //SDMA0_RLC7_MIDCMD_DATA6 29844f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 29854f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 29864f727eceSLe Ma //SDMA0_RLC7_MIDCMD_DATA7 29874f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 29884f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 29894f727eceSLe Ma //SDMA0_RLC7_MIDCMD_DATA8 29904f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 29914f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 29924f727eceSLe Ma //SDMA0_RLC7_MIDCMD_CNTL 29934f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 29944f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 29954f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 29964f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 29974f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 29984f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 29994f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 30004f727eceSLe Ma #define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 30014f727eceSLe Ma 30024f727eceSLe Ma #endif 3003