1c62d3cd0SFeifei Xu /* 2c62d3cd0SFeifei Xu * Copyright (C) 2018 Advanced Micro Devices, Inc. 3c62d3cd0SFeifei Xu * 4c62d3cd0SFeifei Xu * Permission is hereby granted, free of charge, to any person obtaining a 5c62d3cd0SFeifei Xu * copy of this software and associated documentation files (the "Software"), 6c62d3cd0SFeifei Xu * to deal in the Software without restriction, including without limitation 7c62d3cd0SFeifei Xu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c62d3cd0SFeifei Xu * and/or sell copies of the Software, and to permit persons to whom the 9c62d3cd0SFeifei Xu * Software is furnished to do so, subject to the following conditions: 10c62d3cd0SFeifei Xu * 11c62d3cd0SFeifei Xu * The above copyright notice and this permission notice shall be included 12c62d3cd0SFeifei Xu * in all copies or substantial portions of the Software. 13c62d3cd0SFeifei Xu * 14c62d3cd0SFeifei Xu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15c62d3cd0SFeifei Xu * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c62d3cd0SFeifei Xu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c62d3cd0SFeifei Xu * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18c62d3cd0SFeifei Xu * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19c62d3cd0SFeifei Xu * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20c62d3cd0SFeifei Xu */ 21c62d3cd0SFeifei Xu #ifndef _sdma0_4_2_0_SH_MASK_HEADER 22c62d3cd0SFeifei Xu #define _sdma0_4_2_0_SH_MASK_HEADER 23c62d3cd0SFeifei Xu 24c62d3cd0SFeifei Xu 25c62d3cd0SFeifei Xu // addressBlock: sdma0_sdma0dec 26c62d3cd0SFeifei Xu //SDMA0_UCODE_ADDR 27c62d3cd0SFeifei Xu #define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 28c62d3cd0SFeifei Xu #define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL 29c62d3cd0SFeifei Xu //SDMA0_UCODE_DATA 30c62d3cd0SFeifei Xu #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 31c62d3cd0SFeifei Xu #define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 32c62d3cd0SFeifei Xu //SDMA0_VM_CNTL 33c62d3cd0SFeifei Xu #define SDMA0_VM_CNTL__CMD__SHIFT 0x0 34c62d3cd0SFeifei Xu #define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL 35c62d3cd0SFeifei Xu //SDMA0_VM_CTX_LO 36c62d3cd0SFeifei Xu #define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 37c62d3cd0SFeifei Xu #define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 38c62d3cd0SFeifei Xu //SDMA0_VM_CTX_HI 39c62d3cd0SFeifei Xu #define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 40c62d3cd0SFeifei Xu #define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 41c62d3cd0SFeifei Xu //SDMA0_ACTIVE_FCN_ID 42c62d3cd0SFeifei Xu #define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 43c62d3cd0SFeifei Xu #define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 44c62d3cd0SFeifei Xu #define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f 45c62d3cd0SFeifei Xu #define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 46c62d3cd0SFeifei Xu #define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 47c62d3cd0SFeifei Xu #define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L 48c62d3cd0SFeifei Xu //SDMA0_VM_CTX_CNTL 49c62d3cd0SFeifei Xu #define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 50c62d3cd0SFeifei Xu #define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 51c62d3cd0SFeifei Xu #define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L 52c62d3cd0SFeifei Xu #define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L 53c62d3cd0SFeifei Xu //SDMA0_VIRT_RESET_REQ 54c62d3cd0SFeifei Xu #define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 55c62d3cd0SFeifei Xu #define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f 56c62d3cd0SFeifei Xu #define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 57c62d3cd0SFeifei Xu #define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L 58c62d3cd0SFeifei Xu //SDMA0_VF_ENABLE 59c62d3cd0SFeifei Xu #define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 60c62d3cd0SFeifei Xu #define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 61c62d3cd0SFeifei Xu //SDMA0_CONTEXT_REG_TYPE0 62c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 63c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 64c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 65c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 66c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 67c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 68c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 69c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 70c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 71c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 72c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa 73c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb 74c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc 75c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd 76c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe 77c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf 78c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 79c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 80c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 81c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 82c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L 83c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L 84c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L 85c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L 86c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L 87c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L 88c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L 89c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 90c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 91c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 92c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L 93c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L 94c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L 95c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L 96c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L 97c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L 98c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L 99c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L 100c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L 101c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L 102c62d3cd0SFeifei Xu //SDMA0_CONTEXT_REG_TYPE1 103c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 104c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 105c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa 106c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb 107c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc 108c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd 109c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 110c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf 111c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 112c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 113c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 114c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 115c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 116c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 117c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 118c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L 119c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L 120c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L 121c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L 122c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L 123c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L 124c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L 125c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L 126c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L 127c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L 128c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 129c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 130c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L 131c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 132c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 133c62d3cd0SFeifei Xu //SDMA0_CONTEXT_REG_TYPE2 134c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 135c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 136c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 137c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 138c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 139c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 140c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 141c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 142c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 143c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 144c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 145c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L 146c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L 147c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L 148c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L 149c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L 150c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L 151c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L 152c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L 153c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L 154c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L 155c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L 156c62d3cd0SFeifei Xu //SDMA0_CONTEXT_REG_TYPE3 157c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 158c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 159c62d3cd0SFeifei Xu //SDMA0_PUB_REG_TYPE0 160c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 161c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 162c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 163c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 164c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 165c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 166c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 167c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 168c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 169c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 170c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb 171c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc 172c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd 173c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe 174c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf 175c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 176c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 177c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 178c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 179c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 180c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 181c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a 182c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b 183c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c 184c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d 185c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e 186c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f 187c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L 188c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L 189c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L 190c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L 191c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L 192c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L 193c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L 194c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L 195c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L 196c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L 197c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L 198c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L 199c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L 200c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L 201c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L 202c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L 203c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L 204c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L 205c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L 206c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L 207c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L 208c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L 209c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L 210c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L 211c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L 212c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L 213c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L 214c62d3cd0SFeifei Xu //SDMA0_PUB_REG_TYPE1 215c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 216c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 217c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 218c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 219c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 220c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 221c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 222c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 223c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 224c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 225c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa 226c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb 227c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc 228c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd 229c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 230c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 231c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 232c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 233c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 234c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 235c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 236c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 237c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 238c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 239c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 240c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 241c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a 242c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b 243c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c 244c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d 245c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e 246c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f 247c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L 248c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 249c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L 250c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L 251c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L 252c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L 253c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L 254c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L 255c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L 256c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L 257c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L 258c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L 259c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L 260c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L 261c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 262c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 263c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 264c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 265c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L 266c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L 267c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L 268c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L 269c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L 270c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L 271c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L 272c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L 273c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L 274c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L 275c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L 276c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L 277c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L 278c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L 279c62d3cd0SFeifei Xu //SDMA0_PUB_REG_TYPE2 280c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 281c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 282c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 283c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 284c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 285c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 286c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 287c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 288c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 289c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 290c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa 291c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb 292c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc 293c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd 294c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe 295c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0xf 296c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 297c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 298c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 299c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 300c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 301c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 302c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 303c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 304c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 305c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a 306c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b 307c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d 308c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e 309c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f 310c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L 311c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L 312c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L 313c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L 314c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L 315c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L 316c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L 317c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L 318c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L 319c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L 320c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L 321c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L 322c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L 323c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L 324c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L 325c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L 326c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L 327c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L 328c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L 329c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L 330c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L 331c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L 332c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L 333c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L 334c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L 335c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L 336c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L 337c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L 338c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L 339c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L 340c62d3cd0SFeifei Xu //SDMA0_PUB_REG_TYPE3 341c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 342c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 343c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 344c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L 345c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 346c62d3cd0SFeifei Xu #define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL 347c62d3cd0SFeifei Xu //SDMA0_MMHUB_CNTL 348c62d3cd0SFeifei Xu #define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 349c62d3cd0SFeifei Xu #define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 350c62d3cd0SFeifei Xu //SDMA0_CONTEXT_GROUP_BOUNDARY 351c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 352c62d3cd0SFeifei Xu #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 353c62d3cd0SFeifei Xu //SDMA0_POWER_CNTL 354c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 355c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 356c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 357c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 358c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 359c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 360c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 361c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 362c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 363c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a 364c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L 365c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L 366c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L 367c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 368c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 369c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 370c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 371c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 372c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 373c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 374c62d3cd0SFeifei Xu //SDMA0_CLK_CTRL 375c62d3cd0SFeifei Xu #define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 376c62d3cd0SFeifei Xu #define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 377c62d3cd0SFeifei Xu #define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc 378c62d3cd0SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 379c62d3cd0SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 380c62d3cd0SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 381c62d3cd0SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 382c62d3cd0SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 383c62d3cd0SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 384c62d3cd0SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 385c62d3cd0SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 386c62d3cd0SFeifei Xu #define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 387c62d3cd0SFeifei Xu #define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 388c62d3cd0SFeifei Xu #define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L 389c62d3cd0SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 390c62d3cd0SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 391c62d3cd0SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 392c62d3cd0SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 393c62d3cd0SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 394c62d3cd0SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 395c62d3cd0SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 396c62d3cd0SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 397c62d3cd0SFeifei Xu //SDMA0_CNTL 398c62d3cd0SFeifei Xu #define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 399c62d3cd0SFeifei Xu #define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 400c62d3cd0SFeifei Xu #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 401c62d3cd0SFeifei Xu #define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 402c62d3cd0SFeifei Xu #define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 403c62d3cd0SFeifei Xu #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 404c62d3cd0SFeifei Xu #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 405c62d3cd0SFeifei Xu #define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 406c62d3cd0SFeifei Xu #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 407c62d3cd0SFeifei Xu #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 408c62d3cd0SFeifei Xu #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 409c62d3cd0SFeifei Xu #define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L 410c62d3cd0SFeifei Xu #define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 411c62d3cd0SFeifei Xu #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 412c62d3cd0SFeifei Xu #define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 413c62d3cd0SFeifei Xu #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 414c62d3cd0SFeifei Xu #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 415c62d3cd0SFeifei Xu #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 416c62d3cd0SFeifei Xu #define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 417c62d3cd0SFeifei Xu #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 418c62d3cd0SFeifei Xu #define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 419c62d3cd0SFeifei Xu #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 420c62d3cd0SFeifei Xu //SDMA0_CHICKEN_BITS 421c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 422c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 423c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 424c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 425c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 426c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 427c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 428c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 429c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 430c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 431c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 432c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 433c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 434c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 435c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 436c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 437c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 438c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 439c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 440c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 441c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 442c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 443c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 444c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L 445c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L 446c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L 447c62d3cd0SFeifei Xu //SDMA0_GB_ADDR_CONFIG 448c62d3cd0SFeifei Xu #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 449c62d3cd0SFeifei Xu #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 450c62d3cd0SFeifei Xu #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 451c62d3cd0SFeifei Xu #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 452c62d3cd0SFeifei Xu #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 453c62d3cd0SFeifei Xu #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 454c62d3cd0SFeifei Xu #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 455c62d3cd0SFeifei Xu #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 456c62d3cd0SFeifei Xu #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 457c62d3cd0SFeifei Xu #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 458c62d3cd0SFeifei Xu //SDMA0_GB_ADDR_CONFIG_READ 459c62d3cd0SFeifei Xu #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 460c62d3cd0SFeifei Xu #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 461c62d3cd0SFeifei Xu #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 462c62d3cd0SFeifei Xu #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 463c62d3cd0SFeifei Xu #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 464c62d3cd0SFeifei Xu #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 465c62d3cd0SFeifei Xu #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 466c62d3cd0SFeifei Xu #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 467c62d3cd0SFeifei Xu #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 468c62d3cd0SFeifei Xu #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 469c62d3cd0SFeifei Xu //SDMA0_RB_RPTR_FETCH_HI 470c62d3cd0SFeifei Xu #define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 471c62d3cd0SFeifei Xu #define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 472c62d3cd0SFeifei Xu //SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 473c62d3cd0SFeifei Xu #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 474c62d3cd0SFeifei Xu #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 475c62d3cd0SFeifei Xu //SDMA0_RB_RPTR_FETCH 476c62d3cd0SFeifei Xu #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 477c62d3cd0SFeifei Xu #define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 478c62d3cd0SFeifei Xu //SDMA0_IB_OFFSET_FETCH 479c62d3cd0SFeifei Xu #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 480c62d3cd0SFeifei Xu #define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 481c62d3cd0SFeifei Xu //SDMA0_PROGRAM 482c62d3cd0SFeifei Xu #define SDMA0_PROGRAM__STREAM__SHIFT 0x0 483c62d3cd0SFeifei Xu #define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL 484c62d3cd0SFeifei Xu //SDMA0_STATUS_REG 485c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 486c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 487c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 488c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 489c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 490c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 491c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 492c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 493c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 494c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 495c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa 496c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 497c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc 498c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 499c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe 500c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 501c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 502c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 503c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 504c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 505c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 506c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 507c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 508c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 509c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a 510c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 511c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 512c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e 513c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 514c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L 515c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L 516c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L 517c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L 518c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 519c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 520c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 521c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 522c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 523c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L 524c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L 525c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 526c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L 527c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 528c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 529c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 530c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 531c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 532c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 533c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 534c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 535c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 536c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 537c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 538c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L 539c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 540c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 541c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L 542c62d3cd0SFeifei Xu #define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 543c62d3cd0SFeifei Xu //SDMA0_STATUS1_REG 544c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 545c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 546c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 547c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 548c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 549c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 550c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 551c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 552c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 553c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 554c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 555c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf 556c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 557c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 558c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 559c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 560c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 561c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 562c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 563c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 564c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 565c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 566c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 567c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 568c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 569c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L 570c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 571c62d3cd0SFeifei Xu #define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 572c62d3cd0SFeifei Xu //SDMA0_RD_BURST_CNTL 573c62d3cd0SFeifei Xu #define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 574c62d3cd0SFeifei Xu #define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 575c62d3cd0SFeifei Xu #define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 576c62d3cd0SFeifei Xu #define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL 577c62d3cd0SFeifei Xu //SDMA0_HBM_PAGE_CONFIG 578c62d3cd0SFeifei Xu #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 579c62d3cd0SFeifei Xu #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L 580c62d3cd0SFeifei Xu //SDMA0_UCODE_CHECKSUM 581c62d3cd0SFeifei Xu #define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 582c62d3cd0SFeifei Xu #define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 583c62d3cd0SFeifei Xu //SDMA0_F32_CNTL 584c62d3cd0SFeifei Xu #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 585c62d3cd0SFeifei Xu #define SDMA0_F32_CNTL__STEP__SHIFT 0x1 586c62d3cd0SFeifei Xu #define SDMA0_F32_CNTL__HALT_MASK 0x00000001L 587c62d3cd0SFeifei Xu #define SDMA0_F32_CNTL__STEP_MASK 0x00000002L 588c62d3cd0SFeifei Xu //SDMA0_FREEZE 589c62d3cd0SFeifei Xu #define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 590c62d3cd0SFeifei Xu #define SDMA0_FREEZE__FREEZE__SHIFT 0x4 591c62d3cd0SFeifei Xu #define SDMA0_FREEZE__FROZEN__SHIFT 0x5 592c62d3cd0SFeifei Xu #define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 593c62d3cd0SFeifei Xu #define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L 594c62d3cd0SFeifei Xu #define SDMA0_FREEZE__FREEZE_MASK 0x00000010L 595c62d3cd0SFeifei Xu #define SDMA0_FREEZE__FROZEN_MASK 0x00000020L 596c62d3cd0SFeifei Xu #define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L 597c62d3cd0SFeifei Xu //SDMA0_PHASE0_QUANTUM 598c62d3cd0SFeifei Xu #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 599c62d3cd0SFeifei Xu #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 600c62d3cd0SFeifei Xu #define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 601c62d3cd0SFeifei Xu #define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 602c62d3cd0SFeifei Xu #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 603c62d3cd0SFeifei Xu #define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 604c62d3cd0SFeifei Xu //SDMA0_PHASE1_QUANTUM 605c62d3cd0SFeifei Xu #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 606c62d3cd0SFeifei Xu #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 607c62d3cd0SFeifei Xu #define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 608c62d3cd0SFeifei Xu #define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 609c62d3cd0SFeifei Xu #define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 610c62d3cd0SFeifei Xu #define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 611c62d3cd0SFeifei Xu //SDMA_POWER_GATING 612c62d3cd0SFeifei Xu #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 613c62d3cd0SFeifei Xu #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 614c62d3cd0SFeifei Xu #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 615c62d3cd0SFeifei Xu #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 616c62d3cd0SFeifei Xu #define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 617c62d3cd0SFeifei Xu #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L 618c62d3cd0SFeifei Xu #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L 619c62d3cd0SFeifei Xu #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L 620c62d3cd0SFeifei Xu #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L 621c62d3cd0SFeifei Xu #define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L 622c62d3cd0SFeifei Xu //SDMA_PGFSM_CONFIG 623c62d3cd0SFeifei Xu #define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 624c62d3cd0SFeifei Xu #define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 625c62d3cd0SFeifei Xu #define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 626c62d3cd0SFeifei Xu #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa 627c62d3cd0SFeifei Xu #define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb 628c62d3cd0SFeifei Xu #define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc 629c62d3cd0SFeifei Xu #define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd 630c62d3cd0SFeifei Xu #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b 631c62d3cd0SFeifei Xu #define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 632c62d3cd0SFeifei Xu #define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL 633c62d3cd0SFeifei Xu #define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L 634c62d3cd0SFeifei Xu #define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L 635c62d3cd0SFeifei Xu #define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L 636c62d3cd0SFeifei Xu #define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L 637c62d3cd0SFeifei Xu #define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L 638c62d3cd0SFeifei Xu #define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L 639c62d3cd0SFeifei Xu #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L 640c62d3cd0SFeifei Xu #define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L 641c62d3cd0SFeifei Xu //SDMA_PGFSM_WRITE 642c62d3cd0SFeifei Xu #define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 643c62d3cd0SFeifei Xu #define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL 644c62d3cd0SFeifei Xu //SDMA_PGFSM_READ 645c62d3cd0SFeifei Xu #define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 646c62d3cd0SFeifei Xu #define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL 647c62d3cd0SFeifei Xu //SDMA0_EDC_CONFIG 648c62d3cd0SFeifei Xu #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 649c62d3cd0SFeifei Xu #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 650c62d3cd0SFeifei Xu #define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 651c62d3cd0SFeifei Xu #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L 652c62d3cd0SFeifei Xu //SDMA0_BA_THRESHOLD 653c62d3cd0SFeifei Xu #define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 654c62d3cd0SFeifei Xu #define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 655c62d3cd0SFeifei Xu #define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 656c62d3cd0SFeifei Xu #define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 657c62d3cd0SFeifei Xu //SDMA0_ID 658c62d3cd0SFeifei Xu #define SDMA0_ID__DEVICE_ID__SHIFT 0x0 659c62d3cd0SFeifei Xu #define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL 660c62d3cd0SFeifei Xu //SDMA0_VERSION 661c62d3cd0SFeifei Xu #define SDMA0_VERSION__MINVER__SHIFT 0x0 662c62d3cd0SFeifei Xu #define SDMA0_VERSION__MAJVER__SHIFT 0x8 663c62d3cd0SFeifei Xu #define SDMA0_VERSION__REV__SHIFT 0x10 664c62d3cd0SFeifei Xu #define SDMA0_VERSION__MINVER_MASK 0x0000007FL 665c62d3cd0SFeifei Xu #define SDMA0_VERSION__MAJVER_MASK 0x00007F00L 666c62d3cd0SFeifei Xu #define SDMA0_VERSION__REV_MASK 0x003F0000L 667c62d3cd0SFeifei Xu //SDMA0_EDC_COUNTER 668c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 669c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 670c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 671c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 672c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 673c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 674c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 675c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 676c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 677c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 678c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb 679c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc 680c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd 681c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 682c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf 683c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 684c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 685c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 686c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 687c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 688c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 689c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 690c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 691c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 692c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L 693c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L 694c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L 695c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L 696c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L 697c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L 698c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L 699c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L 700c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L 701c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L 702c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L 703c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L 704c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L 705c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L 706c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L 707c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L 708c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L 709c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L 710c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L 711c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L 712c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L 713c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L 714c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L 715c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L 716c62d3cd0SFeifei Xu //SDMA0_EDC_COUNTER_CLEAR 717c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 718c62d3cd0SFeifei Xu #define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L 719c62d3cd0SFeifei Xu //SDMA0_STATUS2_REG 720c62d3cd0SFeifei Xu #define SDMA0_STATUS2_REG__ID__SHIFT 0x0 721c62d3cd0SFeifei Xu #define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 722c62d3cd0SFeifei Xu #define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 723c62d3cd0SFeifei Xu #define SDMA0_STATUS2_REG__ID_MASK 0x00000003L 724c62d3cd0SFeifei Xu #define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL 725c62d3cd0SFeifei Xu #define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 726c62d3cd0SFeifei Xu //SDMA0_ATOMIC_CNTL 727c62d3cd0SFeifei Xu #define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 728c62d3cd0SFeifei Xu #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 729c62d3cd0SFeifei Xu #define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 730c62d3cd0SFeifei Xu #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 731c62d3cd0SFeifei Xu //SDMA0_ATOMIC_PREOP_LO 732c62d3cd0SFeifei Xu #define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 733c62d3cd0SFeifei Xu #define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 734c62d3cd0SFeifei Xu //SDMA0_ATOMIC_PREOP_HI 735c62d3cd0SFeifei Xu #define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 736c62d3cd0SFeifei Xu #define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 737c62d3cd0SFeifei Xu //SDMA0_UTCL1_CNTL 738c62d3cd0SFeifei Xu #define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 739c62d3cd0SFeifei Xu #define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 740c62d3cd0SFeifei Xu #define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 741c62d3cd0SFeifei Xu #define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 742c62d3cd0SFeifei Xu #define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 743c62d3cd0SFeifei Xu #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 744c62d3cd0SFeifei Xu #define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 745c62d3cd0SFeifei Xu #define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 746c62d3cd0SFeifei Xu #define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 747c62d3cd0SFeifei Xu #define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 748c62d3cd0SFeifei Xu #define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 749c62d3cd0SFeifei Xu #define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 750c62d3cd0SFeifei Xu //SDMA0_UTCL1_WATERMK 751c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 752c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 753c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 754c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 755c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL 756c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L 757c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L 758c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L 759c62d3cd0SFeifei Xu //SDMA0_UTCL1_RD_STATUS 760c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 761c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 762c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 763c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 764c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 765c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 766c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 767c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 768c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 769c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 770c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 771c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 772c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 773c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 774c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 775c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 776c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 777c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 778c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 779c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 780c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 781c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 782c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 783c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 784c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 785c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 786c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 787c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 788c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 789c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 790c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 791c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 792c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 793c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 794c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 795c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 796c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 797c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 798c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 799c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 800c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 801c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 802c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 803c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 804c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 805c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 806c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 807c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 808c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 809c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 810c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 811c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 812c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 813c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 814c62d3cd0SFeifei Xu //SDMA0_UTCL1_WR_STATUS 815c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 816c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 817c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 818c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 819c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 820c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 821c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 822c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 823c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 824c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 825c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 826c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 827c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 828c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 829c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 830c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 831c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 832c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 833c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 834c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 835c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 836c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 837c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 838c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 839c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 840c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 841c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 842c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 843c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 844c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 845c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 846c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 847c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 848c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 849c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 850c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 851c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 852c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 853c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 854c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 855c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 856c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 857c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 858c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 859c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 860c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 861c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 862c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 863c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 864c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 865c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 866c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 867c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 868c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 869c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 870c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 871c62d3cd0SFeifei Xu //SDMA0_UTCL1_INV0 872c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 873c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 874c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 875c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 876c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 877c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 878c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 879c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 880c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 881c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 882c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 883c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 884c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 885c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 886c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 887c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 888c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 889c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 890c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 891c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 892c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 893c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 894c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 895c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 896c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 897c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 898c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 899c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 900c62d3cd0SFeifei Xu //SDMA0_UTCL1_INV1 901c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 902c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 903c62d3cd0SFeifei Xu //SDMA0_UTCL1_INV2 904c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 905c62d3cd0SFeifei Xu #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 906c62d3cd0SFeifei Xu //SDMA0_UTCL1_RD_XNACK0 907c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 908c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 909c62d3cd0SFeifei Xu //SDMA0_UTCL1_RD_XNACK1 910c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 911c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 912c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 913c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 914c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 915c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 916c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 917c62d3cd0SFeifei Xu #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 918c62d3cd0SFeifei Xu //SDMA0_UTCL1_WR_XNACK0 919c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 920c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 921c62d3cd0SFeifei Xu //SDMA0_UTCL1_WR_XNACK1 922c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 923c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 924c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 925c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 926c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 927c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 928c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 929c62d3cd0SFeifei Xu #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 930c62d3cd0SFeifei Xu //SDMA0_UTCL1_TIMEOUT 931c62d3cd0SFeifei Xu #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 932c62d3cd0SFeifei Xu #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 933c62d3cd0SFeifei Xu #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 934c62d3cd0SFeifei Xu #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 935c62d3cd0SFeifei Xu //SDMA0_UTCL1_PAGE 936c62d3cd0SFeifei Xu #define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 937c62d3cd0SFeifei Xu #define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 938c62d3cd0SFeifei Xu #define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 939c62d3cd0SFeifei Xu #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 940c62d3cd0SFeifei Xu #define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 941c62d3cd0SFeifei Xu #define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 942c62d3cd0SFeifei Xu #define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 943c62d3cd0SFeifei Xu #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 944c62d3cd0SFeifei Xu //SDMA0_POWER_CNTL_IDLE 945c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 946c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 947c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 948c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 949c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 950c62d3cd0SFeifei Xu #define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 951c62d3cd0SFeifei Xu //SDMA0_RELAX_ORDERING_LUT 952c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 953c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 954c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 955c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 956c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 957c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 958c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 959c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 960c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 961c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 962c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 963c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 964c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 965c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 966c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 967c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 968c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 969c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 970c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 971c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 972c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 973c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 974c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 975c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 976c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 977c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 978c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 979c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 980c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 981c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 982c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 983c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 984c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 985c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 986c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 987c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 988c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 989c62d3cd0SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 990c62d3cd0SFeifei Xu //SDMA0_CHICKEN_BITS_2 991c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 992c62d3cd0SFeifei Xu #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 993c62d3cd0SFeifei Xu //SDMA0_STATUS3_REG 994c62d3cd0SFeifei Xu #define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 995c62d3cd0SFeifei Xu #define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 996c62d3cd0SFeifei Xu #define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 997c62d3cd0SFeifei Xu #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 998c62d3cd0SFeifei Xu #define SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 999c62d3cd0SFeifei Xu #define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 1000c62d3cd0SFeifei Xu #define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 1001c62d3cd0SFeifei Xu #define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 1002c62d3cd0SFeifei Xu #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L 1003c62d3cd0SFeifei Xu #define SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L 1004c62d3cd0SFeifei Xu //SDMA0_PHYSICAL_ADDR_LO 1005c62d3cd0SFeifei Xu #define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 1006c62d3cd0SFeifei Xu #define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 1007c62d3cd0SFeifei Xu #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 1008c62d3cd0SFeifei Xu #define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 1009c62d3cd0SFeifei Xu #define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 1010c62d3cd0SFeifei Xu #define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 1011c62d3cd0SFeifei Xu #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 1012c62d3cd0SFeifei Xu #define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 1013c62d3cd0SFeifei Xu //SDMA0_PHYSICAL_ADDR_HI 1014c62d3cd0SFeifei Xu #define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 1015c62d3cd0SFeifei Xu #define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 1016c62d3cd0SFeifei Xu //SDMA0_PHASE2_QUANTUM 1017c62d3cd0SFeifei Xu #define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0 1018c62d3cd0SFeifei Xu #define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8 1019c62d3cd0SFeifei Xu #define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 1020c62d3cd0SFeifei Xu #define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 1021c62d3cd0SFeifei Xu #define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 1022c62d3cd0SFeifei Xu #define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 1023c62d3cd0SFeifei Xu //SDMA0_ERROR_LOG 1024c62d3cd0SFeifei Xu #define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 1025c62d3cd0SFeifei Xu #define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 1026c62d3cd0SFeifei Xu #define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 1027c62d3cd0SFeifei Xu #define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L 1028c62d3cd0SFeifei Xu //SDMA0_PUB_DUMMY_REG0 1029c62d3cd0SFeifei Xu #define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 1030c62d3cd0SFeifei Xu #define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 1031c62d3cd0SFeifei Xu //SDMA0_PUB_DUMMY_REG1 1032c62d3cd0SFeifei Xu #define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 1033c62d3cd0SFeifei Xu #define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 1034c62d3cd0SFeifei Xu //SDMA0_PUB_DUMMY_REG2 1035c62d3cd0SFeifei Xu #define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 1036c62d3cd0SFeifei Xu #define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 1037c62d3cd0SFeifei Xu //SDMA0_PUB_DUMMY_REG3 1038c62d3cd0SFeifei Xu #define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 1039c62d3cd0SFeifei Xu #define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 1040c62d3cd0SFeifei Xu //SDMA0_F32_COUNTER 1041c62d3cd0SFeifei Xu #define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 1042c62d3cd0SFeifei Xu #define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 1043c62d3cd0SFeifei Xu //SDMA0_PERFMON_CNTL 1044c62d3cd0SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 1045c62d3cd0SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 1046c62d3cd0SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 1047c62d3cd0SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 1048c62d3cd0SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 1049c62d3cd0SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 1050c62d3cd0SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 1051c62d3cd0SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 1052c62d3cd0SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 1053c62d3cd0SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 1054c62d3cd0SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 1055c62d3cd0SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 1056c62d3cd0SFeifei Xu //SDMA0_PERFCOUNTER0_RESULT 1057c62d3cd0SFeifei Xu #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 1058c62d3cd0SFeifei Xu #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1059c62d3cd0SFeifei Xu //SDMA0_PERFCOUNTER1_RESULT 1060c62d3cd0SFeifei Xu #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1061c62d3cd0SFeifei Xu #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1062c62d3cd0SFeifei Xu //SDMA0_PERFCOUNTER_TAG_DELAY_RANGE 1063c62d3cd0SFeifei Xu #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 1064c62d3cd0SFeifei Xu #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe 1065c62d3cd0SFeifei Xu #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c 1066c62d3cd0SFeifei Xu #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL 1067c62d3cd0SFeifei Xu #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L 1068c62d3cd0SFeifei Xu #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L 1069c62d3cd0SFeifei Xu //SDMA0_CRD_CNTL 1070c62d3cd0SFeifei Xu #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 1071c62d3cd0SFeifei Xu #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 1072c62d3cd0SFeifei Xu #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 1073c62d3cd0SFeifei Xu #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 1074c62d3cd0SFeifei Xu //SDMA0_GPU_IOV_VIOLATION_LOG 1075c62d3cd0SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1076c62d3cd0SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1077c62d3cd0SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1078c62d3cd0SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 1079c62d3cd0SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 1080c62d3cd0SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 1081c62d3cd0SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 1082c62d3cd0SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1083c62d3cd0SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1084c62d3cd0SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 1085c62d3cd0SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L 1086c62d3cd0SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 1087c62d3cd0SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L 1088c62d3cd0SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 1089c62d3cd0SFeifei Xu //SDMA0_ULV_CNTL 1090c62d3cd0SFeifei Xu #define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 1091c62d3cd0SFeifei Xu #define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b 1092c62d3cd0SFeifei Xu #define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c 1093c62d3cd0SFeifei Xu #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 1094c62d3cd0SFeifei Xu #define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 1095c62d3cd0SFeifei Xu #define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 1096c62d3cd0SFeifei Xu #define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 1097c62d3cd0SFeifei Xu #define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L 1098c62d3cd0SFeifei Xu #define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L 1099c62d3cd0SFeifei Xu #define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 1100c62d3cd0SFeifei Xu #define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 1101c62d3cd0SFeifei Xu #define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 1102c62d3cd0SFeifei Xu //SDMA0_EA_DBIT_ADDR_DATA 1103c62d3cd0SFeifei Xu #define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 1104c62d3cd0SFeifei Xu #define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 1105c62d3cd0SFeifei Xu //SDMA0_EA_DBIT_ADDR_INDEX 1106c62d3cd0SFeifei Xu #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 1107c62d3cd0SFeifei Xu #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 1108c62d3cd0SFeifei Xu //SDMA0_GFX_RB_CNTL 1109c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1110c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1111c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1112c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1113c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1114c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1115c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1116c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1117c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1118c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1119c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1120c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1121c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1122c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1123c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 1124c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 1125c62d3cd0SFeifei Xu //SDMA0_GFX_RB_BASE 1126c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 1127c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1128c62d3cd0SFeifei Xu //SDMA0_GFX_RB_BASE_HI 1129c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1130c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1131c62d3cd0SFeifei Xu //SDMA0_GFX_RB_RPTR 1132c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 1133c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1134c62d3cd0SFeifei Xu //SDMA0_GFX_RB_RPTR_HI 1135c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 1136c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1137c62d3cd0SFeifei Xu //SDMA0_GFX_RB_WPTR 1138c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 1139c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1140c62d3cd0SFeifei Xu //SDMA0_GFX_RB_WPTR_HI 1141c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 1142c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1143c62d3cd0SFeifei Xu //SDMA0_GFX_RB_WPTR_POLL_CNTL 1144c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1145c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1146c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1147c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1148c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1149c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1150c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1151c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1152c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1153c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1154c62d3cd0SFeifei Xu //SDMA0_GFX_RB_RPTR_ADDR_HI 1155c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1156c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1157c62d3cd0SFeifei Xu //SDMA0_GFX_RB_RPTR_ADDR_LO 1158c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1159c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1160c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1161c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1162c62d3cd0SFeifei Xu //SDMA0_GFX_IB_CNTL 1163c62d3cd0SFeifei Xu #define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1164c62d3cd0SFeifei Xu #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1165c62d3cd0SFeifei Xu #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1166c62d3cd0SFeifei Xu #define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1167c62d3cd0SFeifei Xu #define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1168c62d3cd0SFeifei Xu #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1169c62d3cd0SFeifei Xu #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1170c62d3cd0SFeifei Xu #define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1171c62d3cd0SFeifei Xu //SDMA0_GFX_IB_RPTR 1172c62d3cd0SFeifei Xu #define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1173c62d3cd0SFeifei Xu #define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1174c62d3cd0SFeifei Xu //SDMA0_GFX_IB_OFFSET 1175c62d3cd0SFeifei Xu #define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1176c62d3cd0SFeifei Xu #define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1177c62d3cd0SFeifei Xu //SDMA0_GFX_IB_BASE_LO 1178c62d3cd0SFeifei Xu #define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1179c62d3cd0SFeifei Xu #define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1180c62d3cd0SFeifei Xu //SDMA0_GFX_IB_BASE_HI 1181c62d3cd0SFeifei Xu #define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1182c62d3cd0SFeifei Xu #define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1183c62d3cd0SFeifei Xu //SDMA0_GFX_IB_SIZE 1184c62d3cd0SFeifei Xu #define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 1185c62d3cd0SFeifei Xu #define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 1186c62d3cd0SFeifei Xu //SDMA0_GFX_SKIP_CNTL 1187c62d3cd0SFeifei Xu #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1188c62d3cd0SFeifei Xu #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1189c62d3cd0SFeifei Xu //SDMA0_GFX_CONTEXT_STATUS 1190c62d3cd0SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1191c62d3cd0SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1192c62d3cd0SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1193c62d3cd0SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1194c62d3cd0SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1195c62d3cd0SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1196c62d3cd0SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1197c62d3cd0SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1198c62d3cd0SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1199c62d3cd0SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1200c62d3cd0SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1201c62d3cd0SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1202c62d3cd0SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1203c62d3cd0SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1204c62d3cd0SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1205c62d3cd0SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1206c62d3cd0SFeifei Xu //SDMA0_GFX_DOORBELL 1207c62d3cd0SFeifei Xu #define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1208c62d3cd0SFeifei Xu #define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1209c62d3cd0SFeifei Xu #define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L 1210c62d3cd0SFeifei Xu #define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 1211c62d3cd0SFeifei Xu //SDMA0_GFX_CONTEXT_CNTL 1212c62d3cd0SFeifei Xu #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1213c62d3cd0SFeifei Xu #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 1214c62d3cd0SFeifei Xu //SDMA0_GFX_STATUS 1215c62d3cd0SFeifei Xu #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1216c62d3cd0SFeifei Xu #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1217c62d3cd0SFeifei Xu #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1218c62d3cd0SFeifei Xu #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1219c62d3cd0SFeifei Xu //SDMA0_GFX_DOORBELL_LOG 1220c62d3cd0SFeifei Xu #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1221c62d3cd0SFeifei Xu #define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1222c62d3cd0SFeifei Xu #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1223c62d3cd0SFeifei Xu #define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1224c62d3cd0SFeifei Xu //SDMA0_GFX_WATERMARK 1225c62d3cd0SFeifei Xu #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1226c62d3cd0SFeifei Xu #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1227c62d3cd0SFeifei Xu #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1228c62d3cd0SFeifei Xu #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1229c62d3cd0SFeifei Xu //SDMA0_GFX_DOORBELL_OFFSET 1230c62d3cd0SFeifei Xu #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1231c62d3cd0SFeifei Xu #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1232c62d3cd0SFeifei Xu //SDMA0_GFX_CSA_ADDR_LO 1233c62d3cd0SFeifei Xu #define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1234c62d3cd0SFeifei Xu #define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1235c62d3cd0SFeifei Xu //SDMA0_GFX_CSA_ADDR_HI 1236c62d3cd0SFeifei Xu #define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1237c62d3cd0SFeifei Xu #define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1238c62d3cd0SFeifei Xu //SDMA0_GFX_IB_SUB_REMAIN 1239c62d3cd0SFeifei Xu #define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1240c62d3cd0SFeifei Xu #define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1241c62d3cd0SFeifei Xu //SDMA0_GFX_PREEMPT 1242c62d3cd0SFeifei Xu #define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1243c62d3cd0SFeifei Xu #define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1244c62d3cd0SFeifei Xu //SDMA0_GFX_DUMMY_REG 1245c62d3cd0SFeifei Xu #define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1246c62d3cd0SFeifei Xu #define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1247c62d3cd0SFeifei Xu //SDMA0_GFX_RB_WPTR_POLL_ADDR_HI 1248c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1249c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1250c62d3cd0SFeifei Xu //SDMA0_GFX_RB_WPTR_POLL_ADDR_LO 1251c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1252c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1253c62d3cd0SFeifei Xu //SDMA0_GFX_RB_AQL_CNTL 1254c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1255c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1256c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1257c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1258c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1259c62d3cd0SFeifei Xu #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1260c62d3cd0SFeifei Xu //SDMA0_GFX_MINOR_PTR_UPDATE 1261c62d3cd0SFeifei Xu #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1262c62d3cd0SFeifei Xu #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1263c62d3cd0SFeifei Xu //SDMA0_GFX_MIDCMD_DATA0 1264c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1265c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1266c62d3cd0SFeifei Xu //SDMA0_GFX_MIDCMD_DATA1 1267c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1268c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1269c62d3cd0SFeifei Xu //SDMA0_GFX_MIDCMD_DATA2 1270c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1271c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1272c62d3cd0SFeifei Xu //SDMA0_GFX_MIDCMD_DATA3 1273c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1274c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1275c62d3cd0SFeifei Xu //SDMA0_GFX_MIDCMD_DATA4 1276c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1277c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1278c62d3cd0SFeifei Xu //SDMA0_GFX_MIDCMD_DATA5 1279c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1280c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1281c62d3cd0SFeifei Xu //SDMA0_GFX_MIDCMD_DATA6 1282c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1283c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1284c62d3cd0SFeifei Xu //SDMA0_GFX_MIDCMD_DATA7 1285c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1286c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1287c62d3cd0SFeifei Xu //SDMA0_GFX_MIDCMD_DATA8 1288c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1289c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1290c62d3cd0SFeifei Xu //SDMA0_GFX_MIDCMD_CNTL 1291c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1292c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1293c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1294c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1295c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1296c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1297c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1298c62d3cd0SFeifei Xu #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1299c62d3cd0SFeifei Xu //SDMA0_PAGE_RB_CNTL 1300c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 1301c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 1302c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1303c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1304c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1305c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1306c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 1307c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 1308c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1309c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1310c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1311c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1312c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1313c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1314c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 1315c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 1316c62d3cd0SFeifei Xu //SDMA0_PAGE_RB_BASE 1317c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0 1318c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1319c62d3cd0SFeifei Xu //SDMA0_PAGE_RB_BASE_HI 1320c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 1321c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1322c62d3cd0SFeifei Xu //SDMA0_PAGE_RB_RPTR 1323c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 1324c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1325c62d3cd0SFeifei Xu //SDMA0_PAGE_RB_RPTR_HI 1326c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 1327c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1328c62d3cd0SFeifei Xu //SDMA0_PAGE_RB_WPTR 1329c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 1330c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1331c62d3cd0SFeifei Xu //SDMA0_PAGE_RB_WPTR_HI 1332c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 1333c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1334c62d3cd0SFeifei Xu //SDMA0_PAGE_RB_WPTR_POLL_CNTL 1335c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1336c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1337c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1338c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1339c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1340c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1341c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1342c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1343c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1344c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1345c62d3cd0SFeifei Xu //SDMA0_PAGE_RB_RPTR_ADDR_HI 1346c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1347c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1348c62d3cd0SFeifei Xu //SDMA0_PAGE_RB_RPTR_ADDR_LO 1349c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1350c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1351c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1352c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1353c62d3cd0SFeifei Xu //SDMA0_PAGE_IB_CNTL 1354c62d3cd0SFeifei Xu #define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 1355c62d3cd0SFeifei Xu #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1356c62d3cd0SFeifei Xu #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1357c62d3cd0SFeifei Xu #define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 1358c62d3cd0SFeifei Xu #define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1359c62d3cd0SFeifei Xu #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1360c62d3cd0SFeifei Xu #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1361c62d3cd0SFeifei Xu #define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1362c62d3cd0SFeifei Xu //SDMA0_PAGE_IB_RPTR 1363c62d3cd0SFeifei Xu #define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 1364c62d3cd0SFeifei Xu #define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1365c62d3cd0SFeifei Xu //SDMA0_PAGE_IB_OFFSET 1366c62d3cd0SFeifei Xu #define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 1367c62d3cd0SFeifei Xu #define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1368c62d3cd0SFeifei Xu //SDMA0_PAGE_IB_BASE_LO 1369c62d3cd0SFeifei Xu #define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 1370c62d3cd0SFeifei Xu #define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1371c62d3cd0SFeifei Xu //SDMA0_PAGE_IB_BASE_HI 1372c62d3cd0SFeifei Xu #define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 1373c62d3cd0SFeifei Xu #define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1374c62d3cd0SFeifei Xu //SDMA0_PAGE_IB_SIZE 1375c62d3cd0SFeifei Xu #define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0 1376c62d3cd0SFeifei Xu #define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 1377c62d3cd0SFeifei Xu //SDMA0_PAGE_SKIP_CNTL 1378c62d3cd0SFeifei Xu #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1379c62d3cd0SFeifei Xu #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1380c62d3cd0SFeifei Xu //SDMA0_PAGE_CONTEXT_STATUS 1381c62d3cd0SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1382c62d3cd0SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 1383c62d3cd0SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1384c62d3cd0SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1385c62d3cd0SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1386c62d3cd0SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1387c62d3cd0SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1388c62d3cd0SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1389c62d3cd0SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1390c62d3cd0SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1391c62d3cd0SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1392c62d3cd0SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1393c62d3cd0SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1394c62d3cd0SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1395c62d3cd0SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1396c62d3cd0SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1397c62d3cd0SFeifei Xu //SDMA0_PAGE_DOORBELL 1398c62d3cd0SFeifei Xu #define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 1399c62d3cd0SFeifei Xu #define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 1400c62d3cd0SFeifei Xu #define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 1401c62d3cd0SFeifei Xu #define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 1402c62d3cd0SFeifei Xu //SDMA0_PAGE_STATUS 1403c62d3cd0SFeifei Xu #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1404c62d3cd0SFeifei Xu #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1405c62d3cd0SFeifei Xu #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1406c62d3cd0SFeifei Xu #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1407c62d3cd0SFeifei Xu //SDMA0_PAGE_DOORBELL_LOG 1408c62d3cd0SFeifei Xu #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1409c62d3cd0SFeifei Xu #define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 1410c62d3cd0SFeifei Xu #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1411c62d3cd0SFeifei Xu #define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1412c62d3cd0SFeifei Xu //SDMA0_PAGE_WATERMARK 1413c62d3cd0SFeifei Xu #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1414c62d3cd0SFeifei Xu #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1415c62d3cd0SFeifei Xu #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1416c62d3cd0SFeifei Xu #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1417c62d3cd0SFeifei Xu //SDMA0_PAGE_DOORBELL_OFFSET 1418c62d3cd0SFeifei Xu #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1419c62d3cd0SFeifei Xu #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1420c62d3cd0SFeifei Xu //SDMA0_PAGE_CSA_ADDR_LO 1421c62d3cd0SFeifei Xu #define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 1422c62d3cd0SFeifei Xu #define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1423c62d3cd0SFeifei Xu //SDMA0_PAGE_CSA_ADDR_HI 1424c62d3cd0SFeifei Xu #define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 1425c62d3cd0SFeifei Xu #define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1426c62d3cd0SFeifei Xu //SDMA0_PAGE_IB_SUB_REMAIN 1427c62d3cd0SFeifei Xu #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1428c62d3cd0SFeifei Xu #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1429c62d3cd0SFeifei Xu //SDMA0_PAGE_PREEMPT 1430c62d3cd0SFeifei Xu #define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 1431c62d3cd0SFeifei Xu #define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1432c62d3cd0SFeifei Xu //SDMA0_PAGE_DUMMY_REG 1433c62d3cd0SFeifei Xu #define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 1434c62d3cd0SFeifei Xu #define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1435c62d3cd0SFeifei Xu //SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 1436c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1437c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1438c62d3cd0SFeifei Xu //SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 1439c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1440c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1441c62d3cd0SFeifei Xu //SDMA0_PAGE_RB_AQL_CNTL 1442c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1443c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1444c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1445c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1446c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1447c62d3cd0SFeifei Xu #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1448c62d3cd0SFeifei Xu //SDMA0_PAGE_MINOR_PTR_UPDATE 1449c62d3cd0SFeifei Xu #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1450c62d3cd0SFeifei Xu #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1451c62d3cd0SFeifei Xu //SDMA0_PAGE_MIDCMD_DATA0 1452c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 1453c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1454c62d3cd0SFeifei Xu //SDMA0_PAGE_MIDCMD_DATA1 1455c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 1456c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1457c62d3cd0SFeifei Xu //SDMA0_PAGE_MIDCMD_DATA2 1458c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 1459c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1460c62d3cd0SFeifei Xu //SDMA0_PAGE_MIDCMD_DATA3 1461c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 1462c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1463c62d3cd0SFeifei Xu //SDMA0_PAGE_MIDCMD_DATA4 1464c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 1465c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1466c62d3cd0SFeifei Xu //SDMA0_PAGE_MIDCMD_DATA5 1467c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 1468c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1469c62d3cd0SFeifei Xu //SDMA0_PAGE_MIDCMD_DATA6 1470c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 1471c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1472c62d3cd0SFeifei Xu //SDMA0_PAGE_MIDCMD_DATA7 1473c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 1474c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1475c62d3cd0SFeifei Xu //SDMA0_PAGE_MIDCMD_DATA8 1476c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 1477c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1478c62d3cd0SFeifei Xu //SDMA0_PAGE_MIDCMD_CNTL 1479c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1480c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1481c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1482c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1483c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1484c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1485c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1486c62d3cd0SFeifei Xu #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1487c62d3cd0SFeifei Xu //SDMA0_RLC0_RB_CNTL 1488c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1489c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1490c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1491c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1492c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1493c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1494c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1495c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1496c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1497c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1498c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1499c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1500c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1501c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1502c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 1503c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1504c62d3cd0SFeifei Xu //SDMA0_RLC0_RB_BASE 1505c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 1506c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1507c62d3cd0SFeifei Xu //SDMA0_RLC0_RB_BASE_HI 1508c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1509c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1510c62d3cd0SFeifei Xu //SDMA0_RLC0_RB_RPTR 1511c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 1512c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1513c62d3cd0SFeifei Xu //SDMA0_RLC0_RB_RPTR_HI 1514c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1515c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1516c62d3cd0SFeifei Xu //SDMA0_RLC0_RB_WPTR 1517c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 1518c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1519c62d3cd0SFeifei Xu //SDMA0_RLC0_RB_WPTR_HI 1520c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1521c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1522c62d3cd0SFeifei Xu //SDMA0_RLC0_RB_WPTR_POLL_CNTL 1523c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1524c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1525c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1526c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1527c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1528c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1529c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1530c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1531c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1532c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1533c62d3cd0SFeifei Xu //SDMA0_RLC0_RB_RPTR_ADDR_HI 1534c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1535c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1536c62d3cd0SFeifei Xu //SDMA0_RLC0_RB_RPTR_ADDR_LO 1537c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1538c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1539c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1540c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1541c62d3cd0SFeifei Xu //SDMA0_RLC0_IB_CNTL 1542c62d3cd0SFeifei Xu #define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1543c62d3cd0SFeifei Xu #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1544c62d3cd0SFeifei Xu #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1545c62d3cd0SFeifei Xu #define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1546c62d3cd0SFeifei Xu #define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1547c62d3cd0SFeifei Xu #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1548c62d3cd0SFeifei Xu #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1549c62d3cd0SFeifei Xu #define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1550c62d3cd0SFeifei Xu //SDMA0_RLC0_IB_RPTR 1551c62d3cd0SFeifei Xu #define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1552c62d3cd0SFeifei Xu #define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1553c62d3cd0SFeifei Xu //SDMA0_RLC0_IB_OFFSET 1554c62d3cd0SFeifei Xu #define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1555c62d3cd0SFeifei Xu #define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1556c62d3cd0SFeifei Xu //SDMA0_RLC0_IB_BASE_LO 1557c62d3cd0SFeifei Xu #define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1558c62d3cd0SFeifei Xu #define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1559c62d3cd0SFeifei Xu //SDMA0_RLC0_IB_BASE_HI 1560c62d3cd0SFeifei Xu #define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1561c62d3cd0SFeifei Xu #define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1562c62d3cd0SFeifei Xu //SDMA0_RLC0_IB_SIZE 1563c62d3cd0SFeifei Xu #define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1564c62d3cd0SFeifei Xu #define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1565c62d3cd0SFeifei Xu //SDMA0_RLC0_SKIP_CNTL 1566c62d3cd0SFeifei Xu #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1567c62d3cd0SFeifei Xu #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1568c62d3cd0SFeifei Xu //SDMA0_RLC0_CONTEXT_STATUS 1569c62d3cd0SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1570c62d3cd0SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1571c62d3cd0SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1572c62d3cd0SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1573c62d3cd0SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1574c62d3cd0SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1575c62d3cd0SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1576c62d3cd0SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1577c62d3cd0SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1578c62d3cd0SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1579c62d3cd0SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1580c62d3cd0SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1581c62d3cd0SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1582c62d3cd0SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1583c62d3cd0SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1584c62d3cd0SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1585c62d3cd0SFeifei Xu //SDMA0_RLC0_DOORBELL 1586c62d3cd0SFeifei Xu #define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1587c62d3cd0SFeifei Xu #define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1588c62d3cd0SFeifei Xu #define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 1589c62d3cd0SFeifei Xu #define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 1590c62d3cd0SFeifei Xu //SDMA0_RLC0_STATUS 1591c62d3cd0SFeifei Xu #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1592c62d3cd0SFeifei Xu #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1593c62d3cd0SFeifei Xu #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1594c62d3cd0SFeifei Xu #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1595c62d3cd0SFeifei Xu //SDMA0_RLC0_DOORBELL_LOG 1596c62d3cd0SFeifei Xu #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1597c62d3cd0SFeifei Xu #define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1598c62d3cd0SFeifei Xu #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1599c62d3cd0SFeifei Xu #define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1600c62d3cd0SFeifei Xu //SDMA0_RLC0_WATERMARK 1601c62d3cd0SFeifei Xu #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1602c62d3cd0SFeifei Xu #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1603c62d3cd0SFeifei Xu #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1604c62d3cd0SFeifei Xu #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1605c62d3cd0SFeifei Xu //SDMA0_RLC0_DOORBELL_OFFSET 1606c62d3cd0SFeifei Xu #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1607c62d3cd0SFeifei Xu #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1608c62d3cd0SFeifei Xu //SDMA0_RLC0_CSA_ADDR_LO 1609c62d3cd0SFeifei Xu #define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1610c62d3cd0SFeifei Xu #define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1611c62d3cd0SFeifei Xu //SDMA0_RLC0_CSA_ADDR_HI 1612c62d3cd0SFeifei Xu #define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1613c62d3cd0SFeifei Xu #define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1614c62d3cd0SFeifei Xu //SDMA0_RLC0_IB_SUB_REMAIN 1615c62d3cd0SFeifei Xu #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1616c62d3cd0SFeifei Xu #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1617c62d3cd0SFeifei Xu //SDMA0_RLC0_PREEMPT 1618c62d3cd0SFeifei Xu #define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1619c62d3cd0SFeifei Xu #define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1620c62d3cd0SFeifei Xu //SDMA0_RLC0_DUMMY_REG 1621c62d3cd0SFeifei Xu #define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1622c62d3cd0SFeifei Xu #define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1623c62d3cd0SFeifei Xu //SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 1624c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1625c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1626c62d3cd0SFeifei Xu //SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 1627c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1628c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1629c62d3cd0SFeifei Xu //SDMA0_RLC0_RB_AQL_CNTL 1630c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1631c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1632c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1633c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1634c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1635c62d3cd0SFeifei Xu #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1636c62d3cd0SFeifei Xu //SDMA0_RLC0_MINOR_PTR_UPDATE 1637c62d3cd0SFeifei Xu #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1638c62d3cd0SFeifei Xu #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1639c62d3cd0SFeifei Xu //SDMA0_RLC0_MIDCMD_DATA0 1640c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1641c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1642c62d3cd0SFeifei Xu //SDMA0_RLC0_MIDCMD_DATA1 1643c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1644c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1645c62d3cd0SFeifei Xu //SDMA0_RLC0_MIDCMD_DATA2 1646c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1647c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1648c62d3cd0SFeifei Xu //SDMA0_RLC0_MIDCMD_DATA3 1649c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1650c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1651c62d3cd0SFeifei Xu //SDMA0_RLC0_MIDCMD_DATA4 1652c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1653c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1654c62d3cd0SFeifei Xu //SDMA0_RLC0_MIDCMD_DATA5 1655c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1656c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1657c62d3cd0SFeifei Xu //SDMA0_RLC0_MIDCMD_DATA6 1658c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1659c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1660c62d3cd0SFeifei Xu //SDMA0_RLC0_MIDCMD_DATA7 1661c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1662c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1663c62d3cd0SFeifei Xu //SDMA0_RLC0_MIDCMD_DATA8 1664c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1665c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1666c62d3cd0SFeifei Xu //SDMA0_RLC0_MIDCMD_CNTL 1667c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1668c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1669c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1670c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1671c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1672c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1673c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1674c62d3cd0SFeifei Xu #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1675c62d3cd0SFeifei Xu //SDMA0_RLC1_RB_CNTL 1676c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1677c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1678c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1679c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1680c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1681c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1682c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1683c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1684c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1685c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1686c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1687c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1688c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1689c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1690c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 1691c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1692c62d3cd0SFeifei Xu //SDMA0_RLC1_RB_BASE 1693c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 1694c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1695c62d3cd0SFeifei Xu //SDMA0_RLC1_RB_BASE_HI 1696c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1697c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1698c62d3cd0SFeifei Xu //SDMA0_RLC1_RB_RPTR 1699c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 1700c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1701c62d3cd0SFeifei Xu //SDMA0_RLC1_RB_RPTR_HI 1702c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1703c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1704c62d3cd0SFeifei Xu //SDMA0_RLC1_RB_WPTR 1705c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 1706c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1707c62d3cd0SFeifei Xu //SDMA0_RLC1_RB_WPTR_HI 1708c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1709c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1710c62d3cd0SFeifei Xu //SDMA0_RLC1_RB_WPTR_POLL_CNTL 1711c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1712c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1713c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1714c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1715c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1716c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1717c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1718c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1719c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1720c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1721c62d3cd0SFeifei Xu //SDMA0_RLC1_RB_RPTR_ADDR_HI 1722c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1723c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1724c62d3cd0SFeifei Xu //SDMA0_RLC1_RB_RPTR_ADDR_LO 1725c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1726c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1727c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1728c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1729c62d3cd0SFeifei Xu //SDMA0_RLC1_IB_CNTL 1730c62d3cd0SFeifei Xu #define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1731c62d3cd0SFeifei Xu #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1732c62d3cd0SFeifei Xu #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1733c62d3cd0SFeifei Xu #define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1734c62d3cd0SFeifei Xu #define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1735c62d3cd0SFeifei Xu #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1736c62d3cd0SFeifei Xu #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1737c62d3cd0SFeifei Xu #define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1738c62d3cd0SFeifei Xu //SDMA0_RLC1_IB_RPTR 1739c62d3cd0SFeifei Xu #define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1740c62d3cd0SFeifei Xu #define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1741c62d3cd0SFeifei Xu //SDMA0_RLC1_IB_OFFSET 1742c62d3cd0SFeifei Xu #define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1743c62d3cd0SFeifei Xu #define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1744c62d3cd0SFeifei Xu //SDMA0_RLC1_IB_BASE_LO 1745c62d3cd0SFeifei Xu #define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1746c62d3cd0SFeifei Xu #define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1747c62d3cd0SFeifei Xu //SDMA0_RLC1_IB_BASE_HI 1748c62d3cd0SFeifei Xu #define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1749c62d3cd0SFeifei Xu #define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1750c62d3cd0SFeifei Xu //SDMA0_RLC1_IB_SIZE 1751c62d3cd0SFeifei Xu #define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1752c62d3cd0SFeifei Xu #define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1753c62d3cd0SFeifei Xu //SDMA0_RLC1_SKIP_CNTL 1754c62d3cd0SFeifei Xu #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1755c62d3cd0SFeifei Xu #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1756c62d3cd0SFeifei Xu //SDMA0_RLC1_CONTEXT_STATUS 1757c62d3cd0SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1758c62d3cd0SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1759c62d3cd0SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1760c62d3cd0SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1761c62d3cd0SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1762c62d3cd0SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1763c62d3cd0SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1764c62d3cd0SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1765c62d3cd0SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1766c62d3cd0SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1767c62d3cd0SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1768c62d3cd0SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1769c62d3cd0SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1770c62d3cd0SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1771c62d3cd0SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1772c62d3cd0SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1773c62d3cd0SFeifei Xu //SDMA0_RLC1_DOORBELL 1774c62d3cd0SFeifei Xu #define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 1775c62d3cd0SFeifei Xu #define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 1776c62d3cd0SFeifei Xu #define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 1777c62d3cd0SFeifei Xu #define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 1778c62d3cd0SFeifei Xu //SDMA0_RLC1_STATUS 1779c62d3cd0SFeifei Xu #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1780c62d3cd0SFeifei Xu #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1781c62d3cd0SFeifei Xu #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1782c62d3cd0SFeifei Xu #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1783c62d3cd0SFeifei Xu //SDMA0_RLC1_DOORBELL_LOG 1784c62d3cd0SFeifei Xu #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1785c62d3cd0SFeifei Xu #define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 1786c62d3cd0SFeifei Xu #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1787c62d3cd0SFeifei Xu #define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1788c62d3cd0SFeifei Xu //SDMA0_RLC1_WATERMARK 1789c62d3cd0SFeifei Xu #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1790c62d3cd0SFeifei Xu #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1791c62d3cd0SFeifei Xu #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1792c62d3cd0SFeifei Xu #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1793c62d3cd0SFeifei Xu //SDMA0_RLC1_DOORBELL_OFFSET 1794c62d3cd0SFeifei Xu #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1795c62d3cd0SFeifei Xu #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1796c62d3cd0SFeifei Xu //SDMA0_RLC1_CSA_ADDR_LO 1797c62d3cd0SFeifei Xu #define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1798c62d3cd0SFeifei Xu #define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1799c62d3cd0SFeifei Xu //SDMA0_RLC1_CSA_ADDR_HI 1800c62d3cd0SFeifei Xu #define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1801c62d3cd0SFeifei Xu #define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1802c62d3cd0SFeifei Xu //SDMA0_RLC1_IB_SUB_REMAIN 1803c62d3cd0SFeifei Xu #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1804c62d3cd0SFeifei Xu #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1805c62d3cd0SFeifei Xu //SDMA0_RLC1_PREEMPT 1806c62d3cd0SFeifei Xu #define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1807c62d3cd0SFeifei Xu #define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1808c62d3cd0SFeifei Xu //SDMA0_RLC1_DUMMY_REG 1809c62d3cd0SFeifei Xu #define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 1810c62d3cd0SFeifei Xu #define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1811c62d3cd0SFeifei Xu //SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 1812c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1813c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1814c62d3cd0SFeifei Xu //SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 1815c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1816c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1817c62d3cd0SFeifei Xu //SDMA0_RLC1_RB_AQL_CNTL 1818c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1819c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1820c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1821c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1822c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1823c62d3cd0SFeifei Xu #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1824c62d3cd0SFeifei Xu //SDMA0_RLC1_MINOR_PTR_UPDATE 1825c62d3cd0SFeifei Xu #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1826c62d3cd0SFeifei Xu #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1827c62d3cd0SFeifei Xu //SDMA0_RLC1_MIDCMD_DATA0 1828c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1829c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1830c62d3cd0SFeifei Xu //SDMA0_RLC1_MIDCMD_DATA1 1831c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1832c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1833c62d3cd0SFeifei Xu //SDMA0_RLC1_MIDCMD_DATA2 1834c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1835c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1836c62d3cd0SFeifei Xu //SDMA0_RLC1_MIDCMD_DATA3 1837c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1838c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1839c62d3cd0SFeifei Xu //SDMA0_RLC1_MIDCMD_DATA4 1840c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1841c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1842c62d3cd0SFeifei Xu //SDMA0_RLC1_MIDCMD_DATA5 1843c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1844c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1845c62d3cd0SFeifei Xu //SDMA0_RLC1_MIDCMD_DATA6 1846c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1847c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1848c62d3cd0SFeifei Xu //SDMA0_RLC1_MIDCMD_DATA7 1849c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1850c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1851c62d3cd0SFeifei Xu //SDMA0_RLC1_MIDCMD_DATA8 1852c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1853c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1854c62d3cd0SFeifei Xu //SDMA0_RLC1_MIDCMD_CNTL 1855c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1856c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1857c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1858c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1859c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1860c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1861c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1862c62d3cd0SFeifei Xu #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1863c62d3cd0SFeifei Xu //SDMA0_RLC2_RB_CNTL 1864c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 1865c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 1866c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1867c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1868c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1869c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1870c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 1871c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 1872c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1873c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1874c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1875c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1876c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1877c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1878c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L 1879c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L 1880c62d3cd0SFeifei Xu //SDMA0_RLC2_RB_BASE 1881c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_BASE__ADDR__SHIFT 0x0 1882c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1883c62d3cd0SFeifei Xu //SDMA0_RLC2_RB_BASE_HI 1884c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 1885c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1886c62d3cd0SFeifei Xu //SDMA0_RLC2_RB_RPTR 1887c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 1888c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1889c62d3cd0SFeifei Xu //SDMA0_RLC2_RB_RPTR_HI 1890c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 1891c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1892c62d3cd0SFeifei Xu //SDMA0_RLC2_RB_WPTR 1893c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 1894c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1895c62d3cd0SFeifei Xu //SDMA0_RLC2_RB_WPTR_HI 1896c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 1897c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1898c62d3cd0SFeifei Xu //SDMA0_RLC2_RB_WPTR_POLL_CNTL 1899c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1900c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1901c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1902c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1903c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1904c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1905c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1906c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1907c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1908c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1909c62d3cd0SFeifei Xu //SDMA0_RLC2_RB_RPTR_ADDR_HI 1910c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1911c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1912c62d3cd0SFeifei Xu //SDMA0_RLC2_RB_RPTR_ADDR_LO 1913c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1914c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1915c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1916c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1917c62d3cd0SFeifei Xu //SDMA0_RLC2_IB_CNTL 1918c62d3cd0SFeifei Xu #define SDMA0_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 1919c62d3cd0SFeifei Xu #define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1920c62d3cd0SFeifei Xu #define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1921c62d3cd0SFeifei Xu #define SDMA0_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 1922c62d3cd0SFeifei Xu #define SDMA0_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1923c62d3cd0SFeifei Xu #define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1924c62d3cd0SFeifei Xu #define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1925c62d3cd0SFeifei Xu #define SDMA0_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1926c62d3cd0SFeifei Xu //SDMA0_RLC2_IB_RPTR 1927c62d3cd0SFeifei Xu #define SDMA0_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 1928c62d3cd0SFeifei Xu #define SDMA0_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1929c62d3cd0SFeifei Xu //SDMA0_RLC2_IB_OFFSET 1930c62d3cd0SFeifei Xu #define SDMA0_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 1931c62d3cd0SFeifei Xu #define SDMA0_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1932c62d3cd0SFeifei Xu //SDMA0_RLC2_IB_BASE_LO 1933c62d3cd0SFeifei Xu #define SDMA0_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 1934c62d3cd0SFeifei Xu #define SDMA0_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1935c62d3cd0SFeifei Xu //SDMA0_RLC2_IB_BASE_HI 1936c62d3cd0SFeifei Xu #define SDMA0_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 1937c62d3cd0SFeifei Xu #define SDMA0_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1938c62d3cd0SFeifei Xu //SDMA0_RLC2_IB_SIZE 1939c62d3cd0SFeifei Xu #define SDMA0_RLC2_IB_SIZE__SIZE__SHIFT 0x0 1940c62d3cd0SFeifei Xu #define SDMA0_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL 1941c62d3cd0SFeifei Xu //SDMA0_RLC2_SKIP_CNTL 1942c62d3cd0SFeifei Xu #define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1943c62d3cd0SFeifei Xu #define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1944c62d3cd0SFeifei Xu //SDMA0_RLC2_CONTEXT_STATUS 1945c62d3cd0SFeifei Xu #define SDMA0_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1946c62d3cd0SFeifei Xu #define SDMA0_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 1947c62d3cd0SFeifei Xu #define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1948c62d3cd0SFeifei Xu #define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1949c62d3cd0SFeifei Xu #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1950c62d3cd0SFeifei Xu #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1951c62d3cd0SFeifei Xu #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1952c62d3cd0SFeifei Xu #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1953c62d3cd0SFeifei Xu #define SDMA0_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1954c62d3cd0SFeifei Xu #define SDMA0_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1955c62d3cd0SFeifei Xu #define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1956c62d3cd0SFeifei Xu #define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1957c62d3cd0SFeifei Xu #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1958c62d3cd0SFeifei Xu #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1959c62d3cd0SFeifei Xu #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1960c62d3cd0SFeifei Xu #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1961c62d3cd0SFeifei Xu //SDMA0_RLC2_DOORBELL 1962c62d3cd0SFeifei Xu #define SDMA0_RLC2_DOORBELL__ENABLE__SHIFT 0x1c 1963c62d3cd0SFeifei Xu #define SDMA0_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e 1964c62d3cd0SFeifei Xu #define SDMA0_RLC2_DOORBELL__ENABLE_MASK 0x10000000L 1965c62d3cd0SFeifei Xu #define SDMA0_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L 1966c62d3cd0SFeifei Xu //SDMA0_RLC2_STATUS 1967c62d3cd0SFeifei Xu #define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1968c62d3cd0SFeifei Xu #define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1969c62d3cd0SFeifei Xu #define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1970c62d3cd0SFeifei Xu #define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1971c62d3cd0SFeifei Xu //SDMA0_RLC2_DOORBELL_LOG 1972c62d3cd0SFeifei Xu #define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1973c62d3cd0SFeifei Xu #define SDMA0_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 1974c62d3cd0SFeifei Xu #define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1975c62d3cd0SFeifei Xu #define SDMA0_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1976c62d3cd0SFeifei Xu //SDMA0_RLC2_WATERMARK 1977c62d3cd0SFeifei Xu #define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1978c62d3cd0SFeifei Xu #define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1979c62d3cd0SFeifei Xu #define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1980c62d3cd0SFeifei Xu #define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1981c62d3cd0SFeifei Xu //SDMA0_RLC2_DOORBELL_OFFSET 1982c62d3cd0SFeifei Xu #define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1983c62d3cd0SFeifei Xu #define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1984c62d3cd0SFeifei Xu //SDMA0_RLC2_CSA_ADDR_LO 1985c62d3cd0SFeifei Xu #define SDMA0_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 1986c62d3cd0SFeifei Xu #define SDMA0_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1987c62d3cd0SFeifei Xu //SDMA0_RLC2_CSA_ADDR_HI 1988c62d3cd0SFeifei Xu #define SDMA0_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 1989c62d3cd0SFeifei Xu #define SDMA0_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1990c62d3cd0SFeifei Xu //SDMA0_RLC2_IB_SUB_REMAIN 1991c62d3cd0SFeifei Xu #define SDMA0_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1992c62d3cd0SFeifei Xu #define SDMA0_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1993c62d3cd0SFeifei Xu //SDMA0_RLC2_PREEMPT 1994c62d3cd0SFeifei Xu #define SDMA0_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 1995c62d3cd0SFeifei Xu #define SDMA0_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1996c62d3cd0SFeifei Xu //SDMA0_RLC2_DUMMY_REG 1997c62d3cd0SFeifei Xu #define SDMA0_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 1998c62d3cd0SFeifei Xu #define SDMA0_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1999c62d3cd0SFeifei Xu //SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI 2000c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2001c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2002c62d3cd0SFeifei Xu //SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO 2003c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2004c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2005c62d3cd0SFeifei Xu //SDMA0_RLC2_RB_AQL_CNTL 2006c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2007c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2008c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2009c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2010c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2011c62d3cd0SFeifei Xu #define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2012c62d3cd0SFeifei Xu //SDMA0_RLC2_MINOR_PTR_UPDATE 2013c62d3cd0SFeifei Xu #define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2014c62d3cd0SFeifei Xu #define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2015c62d3cd0SFeifei Xu //SDMA0_RLC2_MIDCMD_DATA0 2016c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 2017c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2018c62d3cd0SFeifei Xu //SDMA0_RLC2_MIDCMD_DATA1 2019c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 2020c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2021c62d3cd0SFeifei Xu //SDMA0_RLC2_MIDCMD_DATA2 2022c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 2023c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2024c62d3cd0SFeifei Xu //SDMA0_RLC2_MIDCMD_DATA3 2025c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 2026c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2027c62d3cd0SFeifei Xu //SDMA0_RLC2_MIDCMD_DATA4 2028c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 2029c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2030c62d3cd0SFeifei Xu //SDMA0_RLC2_MIDCMD_DATA5 2031c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 2032c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2033c62d3cd0SFeifei Xu //SDMA0_RLC2_MIDCMD_DATA6 2034c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 2035c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2036c62d3cd0SFeifei Xu //SDMA0_RLC2_MIDCMD_DATA7 2037c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 2038c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2039c62d3cd0SFeifei Xu //SDMA0_RLC2_MIDCMD_DATA8 2040c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 2041c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2042c62d3cd0SFeifei Xu //SDMA0_RLC2_MIDCMD_CNTL 2043c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2044c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2045c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2046c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2047c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2048c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2049c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2050c62d3cd0SFeifei Xu #define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2051c62d3cd0SFeifei Xu //SDMA0_RLC3_RB_CNTL 2052c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 2053c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 2054c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2055c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2056c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2057c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2058c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 2059c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 2060c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2061c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2062c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2063c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2064c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2065c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2066c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L 2067c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L 2068c62d3cd0SFeifei Xu //SDMA0_RLC3_RB_BASE 2069c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_BASE__ADDR__SHIFT 0x0 2070c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2071c62d3cd0SFeifei Xu //SDMA0_RLC3_RB_BASE_HI 2072c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 2073c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2074c62d3cd0SFeifei Xu //SDMA0_RLC3_RB_RPTR 2075c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 2076c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2077c62d3cd0SFeifei Xu //SDMA0_RLC3_RB_RPTR_HI 2078c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 2079c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2080c62d3cd0SFeifei Xu //SDMA0_RLC3_RB_WPTR 2081c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 2082c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2083c62d3cd0SFeifei Xu //SDMA0_RLC3_RB_WPTR_HI 2084c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 2085c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2086c62d3cd0SFeifei Xu //SDMA0_RLC3_RB_WPTR_POLL_CNTL 2087c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2088c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2089c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2090c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2091c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2092c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2093c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2094c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2095c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2096c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2097c62d3cd0SFeifei Xu //SDMA0_RLC3_RB_RPTR_ADDR_HI 2098c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2099c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2100c62d3cd0SFeifei Xu //SDMA0_RLC3_RB_RPTR_ADDR_LO 2101c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2102c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2103c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2104c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2105c62d3cd0SFeifei Xu //SDMA0_RLC3_IB_CNTL 2106c62d3cd0SFeifei Xu #define SDMA0_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 2107c62d3cd0SFeifei Xu #define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2108c62d3cd0SFeifei Xu #define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2109c62d3cd0SFeifei Xu #define SDMA0_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 2110c62d3cd0SFeifei Xu #define SDMA0_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2111c62d3cd0SFeifei Xu #define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2112c62d3cd0SFeifei Xu #define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2113c62d3cd0SFeifei Xu #define SDMA0_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2114c62d3cd0SFeifei Xu //SDMA0_RLC3_IB_RPTR 2115c62d3cd0SFeifei Xu #define SDMA0_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 2116c62d3cd0SFeifei Xu #define SDMA0_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2117c62d3cd0SFeifei Xu //SDMA0_RLC3_IB_OFFSET 2118c62d3cd0SFeifei Xu #define SDMA0_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 2119c62d3cd0SFeifei Xu #define SDMA0_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2120c62d3cd0SFeifei Xu //SDMA0_RLC3_IB_BASE_LO 2121c62d3cd0SFeifei Xu #define SDMA0_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 2122c62d3cd0SFeifei Xu #define SDMA0_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2123c62d3cd0SFeifei Xu //SDMA0_RLC3_IB_BASE_HI 2124c62d3cd0SFeifei Xu #define SDMA0_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 2125c62d3cd0SFeifei Xu #define SDMA0_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2126c62d3cd0SFeifei Xu //SDMA0_RLC3_IB_SIZE 2127c62d3cd0SFeifei Xu #define SDMA0_RLC3_IB_SIZE__SIZE__SHIFT 0x0 2128c62d3cd0SFeifei Xu #define SDMA0_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL 2129c62d3cd0SFeifei Xu //SDMA0_RLC3_SKIP_CNTL 2130c62d3cd0SFeifei Xu #define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2131c62d3cd0SFeifei Xu #define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2132c62d3cd0SFeifei Xu //SDMA0_RLC3_CONTEXT_STATUS 2133c62d3cd0SFeifei Xu #define SDMA0_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2134c62d3cd0SFeifei Xu #define SDMA0_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 2135c62d3cd0SFeifei Xu #define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2136c62d3cd0SFeifei Xu #define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2137c62d3cd0SFeifei Xu #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2138c62d3cd0SFeifei Xu #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2139c62d3cd0SFeifei Xu #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2140c62d3cd0SFeifei Xu #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2141c62d3cd0SFeifei Xu #define SDMA0_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2142c62d3cd0SFeifei Xu #define SDMA0_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2143c62d3cd0SFeifei Xu #define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2144c62d3cd0SFeifei Xu #define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2145c62d3cd0SFeifei Xu #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2146c62d3cd0SFeifei Xu #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2147c62d3cd0SFeifei Xu #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2148c62d3cd0SFeifei Xu #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2149c62d3cd0SFeifei Xu //SDMA0_RLC3_DOORBELL 2150c62d3cd0SFeifei Xu #define SDMA0_RLC3_DOORBELL__ENABLE__SHIFT 0x1c 2151c62d3cd0SFeifei Xu #define SDMA0_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e 2152c62d3cd0SFeifei Xu #define SDMA0_RLC3_DOORBELL__ENABLE_MASK 0x10000000L 2153c62d3cd0SFeifei Xu #define SDMA0_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L 2154c62d3cd0SFeifei Xu //SDMA0_RLC3_STATUS 2155c62d3cd0SFeifei Xu #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2156c62d3cd0SFeifei Xu #define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2157c62d3cd0SFeifei Xu #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2158c62d3cd0SFeifei Xu #define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2159c62d3cd0SFeifei Xu //SDMA0_RLC3_DOORBELL_LOG 2160c62d3cd0SFeifei Xu #define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2161c62d3cd0SFeifei Xu #define SDMA0_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 2162c62d3cd0SFeifei Xu #define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2163c62d3cd0SFeifei Xu #define SDMA0_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2164c62d3cd0SFeifei Xu //SDMA0_RLC3_WATERMARK 2165c62d3cd0SFeifei Xu #define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2166c62d3cd0SFeifei Xu #define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2167c62d3cd0SFeifei Xu #define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2168c62d3cd0SFeifei Xu #define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2169c62d3cd0SFeifei Xu //SDMA0_RLC3_DOORBELL_OFFSET 2170c62d3cd0SFeifei Xu #define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2171c62d3cd0SFeifei Xu #define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2172c62d3cd0SFeifei Xu //SDMA0_RLC3_CSA_ADDR_LO 2173c62d3cd0SFeifei Xu #define SDMA0_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 2174c62d3cd0SFeifei Xu #define SDMA0_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2175c62d3cd0SFeifei Xu //SDMA0_RLC3_CSA_ADDR_HI 2176c62d3cd0SFeifei Xu #define SDMA0_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 2177c62d3cd0SFeifei Xu #define SDMA0_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2178c62d3cd0SFeifei Xu //SDMA0_RLC3_IB_SUB_REMAIN 2179c62d3cd0SFeifei Xu #define SDMA0_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2180c62d3cd0SFeifei Xu #define SDMA0_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2181c62d3cd0SFeifei Xu //SDMA0_RLC3_PREEMPT 2182c62d3cd0SFeifei Xu #define SDMA0_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 2183c62d3cd0SFeifei Xu #define SDMA0_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2184c62d3cd0SFeifei Xu //SDMA0_RLC3_DUMMY_REG 2185c62d3cd0SFeifei Xu #define SDMA0_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 2186c62d3cd0SFeifei Xu #define SDMA0_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2187c62d3cd0SFeifei Xu //SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI 2188c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2189c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2190c62d3cd0SFeifei Xu //SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO 2191c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2192c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2193c62d3cd0SFeifei Xu //SDMA0_RLC3_RB_AQL_CNTL 2194c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2195c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2196c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2197c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2198c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2199c62d3cd0SFeifei Xu #define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2200c62d3cd0SFeifei Xu //SDMA0_RLC3_MINOR_PTR_UPDATE 2201c62d3cd0SFeifei Xu #define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2202c62d3cd0SFeifei Xu #define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2203c62d3cd0SFeifei Xu //SDMA0_RLC3_MIDCMD_DATA0 2204c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 2205c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2206c62d3cd0SFeifei Xu //SDMA0_RLC3_MIDCMD_DATA1 2207c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 2208c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2209c62d3cd0SFeifei Xu //SDMA0_RLC3_MIDCMD_DATA2 2210c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 2211c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2212c62d3cd0SFeifei Xu //SDMA0_RLC3_MIDCMD_DATA3 2213c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 2214c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2215c62d3cd0SFeifei Xu //SDMA0_RLC3_MIDCMD_DATA4 2216c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 2217c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2218c62d3cd0SFeifei Xu //SDMA0_RLC3_MIDCMD_DATA5 2219c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 2220c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2221c62d3cd0SFeifei Xu //SDMA0_RLC3_MIDCMD_DATA6 2222c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 2223c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2224c62d3cd0SFeifei Xu //SDMA0_RLC3_MIDCMD_DATA7 2225c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 2226c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2227c62d3cd0SFeifei Xu //SDMA0_RLC3_MIDCMD_DATA8 2228c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 2229c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2230c62d3cd0SFeifei Xu //SDMA0_RLC3_MIDCMD_CNTL 2231c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2232c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2233c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2234c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2235c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2236c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2237c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2238c62d3cd0SFeifei Xu #define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2239c62d3cd0SFeifei Xu //SDMA0_RLC4_RB_CNTL 2240c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 2241c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 2242c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2243c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2244c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2245c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2246c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 2247c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 2248c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2249c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2250c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2251c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2252c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2253c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2254c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L 2255c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L 2256c62d3cd0SFeifei Xu //SDMA0_RLC4_RB_BASE 2257c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_BASE__ADDR__SHIFT 0x0 2258c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2259c62d3cd0SFeifei Xu //SDMA0_RLC4_RB_BASE_HI 2260c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 2261c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2262c62d3cd0SFeifei Xu //SDMA0_RLC4_RB_RPTR 2263c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 2264c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2265c62d3cd0SFeifei Xu //SDMA0_RLC4_RB_RPTR_HI 2266c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 2267c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2268c62d3cd0SFeifei Xu //SDMA0_RLC4_RB_WPTR 2269c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 2270c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2271c62d3cd0SFeifei Xu //SDMA0_RLC4_RB_WPTR_HI 2272c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 2273c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2274c62d3cd0SFeifei Xu //SDMA0_RLC4_RB_WPTR_POLL_CNTL 2275c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2276c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2277c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2278c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2279c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2280c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2281c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2282c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2283c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2284c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2285c62d3cd0SFeifei Xu //SDMA0_RLC4_RB_RPTR_ADDR_HI 2286c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2287c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2288c62d3cd0SFeifei Xu //SDMA0_RLC4_RB_RPTR_ADDR_LO 2289c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2290c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2291c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2292c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2293c62d3cd0SFeifei Xu //SDMA0_RLC4_IB_CNTL 2294c62d3cd0SFeifei Xu #define SDMA0_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 2295c62d3cd0SFeifei Xu #define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2296c62d3cd0SFeifei Xu #define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2297c62d3cd0SFeifei Xu #define SDMA0_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 2298c62d3cd0SFeifei Xu #define SDMA0_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2299c62d3cd0SFeifei Xu #define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2300c62d3cd0SFeifei Xu #define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2301c62d3cd0SFeifei Xu #define SDMA0_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2302c62d3cd0SFeifei Xu //SDMA0_RLC4_IB_RPTR 2303c62d3cd0SFeifei Xu #define SDMA0_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 2304c62d3cd0SFeifei Xu #define SDMA0_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2305c62d3cd0SFeifei Xu //SDMA0_RLC4_IB_OFFSET 2306c62d3cd0SFeifei Xu #define SDMA0_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 2307c62d3cd0SFeifei Xu #define SDMA0_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2308c62d3cd0SFeifei Xu //SDMA0_RLC4_IB_BASE_LO 2309c62d3cd0SFeifei Xu #define SDMA0_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 2310c62d3cd0SFeifei Xu #define SDMA0_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2311c62d3cd0SFeifei Xu //SDMA0_RLC4_IB_BASE_HI 2312c62d3cd0SFeifei Xu #define SDMA0_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 2313c62d3cd0SFeifei Xu #define SDMA0_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2314c62d3cd0SFeifei Xu //SDMA0_RLC4_IB_SIZE 2315c62d3cd0SFeifei Xu #define SDMA0_RLC4_IB_SIZE__SIZE__SHIFT 0x0 2316c62d3cd0SFeifei Xu #define SDMA0_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL 2317c62d3cd0SFeifei Xu //SDMA0_RLC4_SKIP_CNTL 2318c62d3cd0SFeifei Xu #define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2319c62d3cd0SFeifei Xu #define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2320c62d3cd0SFeifei Xu //SDMA0_RLC4_CONTEXT_STATUS 2321c62d3cd0SFeifei Xu #define SDMA0_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2322c62d3cd0SFeifei Xu #define SDMA0_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 2323c62d3cd0SFeifei Xu #define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2324c62d3cd0SFeifei Xu #define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2325c62d3cd0SFeifei Xu #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2326c62d3cd0SFeifei Xu #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2327c62d3cd0SFeifei Xu #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2328c62d3cd0SFeifei Xu #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2329c62d3cd0SFeifei Xu #define SDMA0_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2330c62d3cd0SFeifei Xu #define SDMA0_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2331c62d3cd0SFeifei Xu #define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2332c62d3cd0SFeifei Xu #define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2333c62d3cd0SFeifei Xu #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2334c62d3cd0SFeifei Xu #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2335c62d3cd0SFeifei Xu #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2336c62d3cd0SFeifei Xu #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2337c62d3cd0SFeifei Xu //SDMA0_RLC4_DOORBELL 2338c62d3cd0SFeifei Xu #define SDMA0_RLC4_DOORBELL__ENABLE__SHIFT 0x1c 2339c62d3cd0SFeifei Xu #define SDMA0_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e 2340c62d3cd0SFeifei Xu #define SDMA0_RLC4_DOORBELL__ENABLE_MASK 0x10000000L 2341c62d3cd0SFeifei Xu #define SDMA0_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L 2342c62d3cd0SFeifei Xu //SDMA0_RLC4_STATUS 2343c62d3cd0SFeifei Xu #define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2344c62d3cd0SFeifei Xu #define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2345c62d3cd0SFeifei Xu #define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2346c62d3cd0SFeifei Xu #define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2347c62d3cd0SFeifei Xu //SDMA0_RLC4_DOORBELL_LOG 2348c62d3cd0SFeifei Xu #define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2349c62d3cd0SFeifei Xu #define SDMA0_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 2350c62d3cd0SFeifei Xu #define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2351c62d3cd0SFeifei Xu #define SDMA0_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2352c62d3cd0SFeifei Xu //SDMA0_RLC4_WATERMARK 2353c62d3cd0SFeifei Xu #define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2354c62d3cd0SFeifei Xu #define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2355c62d3cd0SFeifei Xu #define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2356c62d3cd0SFeifei Xu #define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2357c62d3cd0SFeifei Xu //SDMA0_RLC4_DOORBELL_OFFSET 2358c62d3cd0SFeifei Xu #define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2359c62d3cd0SFeifei Xu #define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2360c62d3cd0SFeifei Xu //SDMA0_RLC4_CSA_ADDR_LO 2361c62d3cd0SFeifei Xu #define SDMA0_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 2362c62d3cd0SFeifei Xu #define SDMA0_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2363c62d3cd0SFeifei Xu //SDMA0_RLC4_CSA_ADDR_HI 2364c62d3cd0SFeifei Xu #define SDMA0_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 2365c62d3cd0SFeifei Xu #define SDMA0_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2366c62d3cd0SFeifei Xu //SDMA0_RLC4_IB_SUB_REMAIN 2367c62d3cd0SFeifei Xu #define SDMA0_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2368c62d3cd0SFeifei Xu #define SDMA0_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2369c62d3cd0SFeifei Xu //SDMA0_RLC4_PREEMPT 2370c62d3cd0SFeifei Xu #define SDMA0_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 2371c62d3cd0SFeifei Xu #define SDMA0_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2372c62d3cd0SFeifei Xu //SDMA0_RLC4_DUMMY_REG 2373c62d3cd0SFeifei Xu #define SDMA0_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 2374c62d3cd0SFeifei Xu #define SDMA0_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2375c62d3cd0SFeifei Xu //SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI 2376c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2377c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2378c62d3cd0SFeifei Xu //SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO 2379c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2380c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2381c62d3cd0SFeifei Xu //SDMA0_RLC4_RB_AQL_CNTL 2382c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2383c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2384c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2385c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2386c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2387c62d3cd0SFeifei Xu #define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2388c62d3cd0SFeifei Xu //SDMA0_RLC4_MINOR_PTR_UPDATE 2389c62d3cd0SFeifei Xu #define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2390c62d3cd0SFeifei Xu #define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2391c62d3cd0SFeifei Xu //SDMA0_RLC4_MIDCMD_DATA0 2392c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 2393c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2394c62d3cd0SFeifei Xu //SDMA0_RLC4_MIDCMD_DATA1 2395c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 2396c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2397c62d3cd0SFeifei Xu //SDMA0_RLC4_MIDCMD_DATA2 2398c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 2399c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2400c62d3cd0SFeifei Xu //SDMA0_RLC4_MIDCMD_DATA3 2401c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 2402c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2403c62d3cd0SFeifei Xu //SDMA0_RLC4_MIDCMD_DATA4 2404c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 2405c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2406c62d3cd0SFeifei Xu //SDMA0_RLC4_MIDCMD_DATA5 2407c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 2408c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2409c62d3cd0SFeifei Xu //SDMA0_RLC4_MIDCMD_DATA6 2410c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 2411c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2412c62d3cd0SFeifei Xu //SDMA0_RLC4_MIDCMD_DATA7 2413c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 2414c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2415c62d3cd0SFeifei Xu //SDMA0_RLC4_MIDCMD_DATA8 2416c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 2417c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2418c62d3cd0SFeifei Xu //SDMA0_RLC4_MIDCMD_CNTL 2419c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2420c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2421c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2422c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2423c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2424c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2425c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2426c62d3cd0SFeifei Xu #define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2427c62d3cd0SFeifei Xu //SDMA0_RLC5_RB_CNTL 2428c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 2429c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 2430c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2431c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2432c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2433c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2434c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 2435c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 2436c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2437c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2438c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2439c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2440c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2441c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2442c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L 2443c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L 2444c62d3cd0SFeifei Xu //SDMA0_RLC5_RB_BASE 2445c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_BASE__ADDR__SHIFT 0x0 2446c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2447c62d3cd0SFeifei Xu //SDMA0_RLC5_RB_BASE_HI 2448c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 2449c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2450c62d3cd0SFeifei Xu //SDMA0_RLC5_RB_RPTR 2451c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 2452c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2453c62d3cd0SFeifei Xu //SDMA0_RLC5_RB_RPTR_HI 2454c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 2455c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2456c62d3cd0SFeifei Xu //SDMA0_RLC5_RB_WPTR 2457c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 2458c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2459c62d3cd0SFeifei Xu //SDMA0_RLC5_RB_WPTR_HI 2460c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 2461c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2462c62d3cd0SFeifei Xu //SDMA0_RLC5_RB_WPTR_POLL_CNTL 2463c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2464c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2465c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2466c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2467c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2468c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2469c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2470c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2471c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2472c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2473c62d3cd0SFeifei Xu //SDMA0_RLC5_RB_RPTR_ADDR_HI 2474c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2475c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2476c62d3cd0SFeifei Xu //SDMA0_RLC5_RB_RPTR_ADDR_LO 2477c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2478c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2479c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2480c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2481c62d3cd0SFeifei Xu //SDMA0_RLC5_IB_CNTL 2482c62d3cd0SFeifei Xu #define SDMA0_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 2483c62d3cd0SFeifei Xu #define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2484c62d3cd0SFeifei Xu #define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2485c62d3cd0SFeifei Xu #define SDMA0_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 2486c62d3cd0SFeifei Xu #define SDMA0_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2487c62d3cd0SFeifei Xu #define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2488c62d3cd0SFeifei Xu #define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2489c62d3cd0SFeifei Xu #define SDMA0_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2490c62d3cd0SFeifei Xu //SDMA0_RLC5_IB_RPTR 2491c62d3cd0SFeifei Xu #define SDMA0_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 2492c62d3cd0SFeifei Xu #define SDMA0_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2493c62d3cd0SFeifei Xu //SDMA0_RLC5_IB_OFFSET 2494c62d3cd0SFeifei Xu #define SDMA0_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 2495c62d3cd0SFeifei Xu #define SDMA0_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2496c62d3cd0SFeifei Xu //SDMA0_RLC5_IB_BASE_LO 2497c62d3cd0SFeifei Xu #define SDMA0_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 2498c62d3cd0SFeifei Xu #define SDMA0_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2499c62d3cd0SFeifei Xu //SDMA0_RLC5_IB_BASE_HI 2500c62d3cd0SFeifei Xu #define SDMA0_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 2501c62d3cd0SFeifei Xu #define SDMA0_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2502c62d3cd0SFeifei Xu //SDMA0_RLC5_IB_SIZE 2503c62d3cd0SFeifei Xu #define SDMA0_RLC5_IB_SIZE__SIZE__SHIFT 0x0 2504c62d3cd0SFeifei Xu #define SDMA0_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL 2505c62d3cd0SFeifei Xu //SDMA0_RLC5_SKIP_CNTL 2506c62d3cd0SFeifei Xu #define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2507c62d3cd0SFeifei Xu #define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2508c62d3cd0SFeifei Xu //SDMA0_RLC5_CONTEXT_STATUS 2509c62d3cd0SFeifei Xu #define SDMA0_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2510c62d3cd0SFeifei Xu #define SDMA0_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 2511c62d3cd0SFeifei Xu #define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2512c62d3cd0SFeifei Xu #define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2513c62d3cd0SFeifei Xu #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2514c62d3cd0SFeifei Xu #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2515c62d3cd0SFeifei Xu #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2516c62d3cd0SFeifei Xu #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2517c62d3cd0SFeifei Xu #define SDMA0_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2518c62d3cd0SFeifei Xu #define SDMA0_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2519c62d3cd0SFeifei Xu #define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2520c62d3cd0SFeifei Xu #define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2521c62d3cd0SFeifei Xu #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2522c62d3cd0SFeifei Xu #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2523c62d3cd0SFeifei Xu #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2524c62d3cd0SFeifei Xu #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2525c62d3cd0SFeifei Xu //SDMA0_RLC5_DOORBELL 2526c62d3cd0SFeifei Xu #define SDMA0_RLC5_DOORBELL__ENABLE__SHIFT 0x1c 2527c62d3cd0SFeifei Xu #define SDMA0_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e 2528c62d3cd0SFeifei Xu #define SDMA0_RLC5_DOORBELL__ENABLE_MASK 0x10000000L 2529c62d3cd0SFeifei Xu #define SDMA0_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L 2530c62d3cd0SFeifei Xu //SDMA0_RLC5_STATUS 2531c62d3cd0SFeifei Xu #define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2532c62d3cd0SFeifei Xu #define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2533c62d3cd0SFeifei Xu #define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2534c62d3cd0SFeifei Xu #define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2535c62d3cd0SFeifei Xu //SDMA0_RLC5_DOORBELL_LOG 2536c62d3cd0SFeifei Xu #define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2537c62d3cd0SFeifei Xu #define SDMA0_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 2538c62d3cd0SFeifei Xu #define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2539c62d3cd0SFeifei Xu #define SDMA0_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2540c62d3cd0SFeifei Xu //SDMA0_RLC5_WATERMARK 2541c62d3cd0SFeifei Xu #define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2542c62d3cd0SFeifei Xu #define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2543c62d3cd0SFeifei Xu #define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2544c62d3cd0SFeifei Xu #define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2545c62d3cd0SFeifei Xu //SDMA0_RLC5_DOORBELL_OFFSET 2546c62d3cd0SFeifei Xu #define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2547c62d3cd0SFeifei Xu #define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2548c62d3cd0SFeifei Xu //SDMA0_RLC5_CSA_ADDR_LO 2549c62d3cd0SFeifei Xu #define SDMA0_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 2550c62d3cd0SFeifei Xu #define SDMA0_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2551c62d3cd0SFeifei Xu //SDMA0_RLC5_CSA_ADDR_HI 2552c62d3cd0SFeifei Xu #define SDMA0_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 2553c62d3cd0SFeifei Xu #define SDMA0_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2554c62d3cd0SFeifei Xu //SDMA0_RLC5_IB_SUB_REMAIN 2555c62d3cd0SFeifei Xu #define SDMA0_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2556c62d3cd0SFeifei Xu #define SDMA0_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2557c62d3cd0SFeifei Xu //SDMA0_RLC5_PREEMPT 2558c62d3cd0SFeifei Xu #define SDMA0_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 2559c62d3cd0SFeifei Xu #define SDMA0_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2560c62d3cd0SFeifei Xu //SDMA0_RLC5_DUMMY_REG 2561c62d3cd0SFeifei Xu #define SDMA0_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 2562c62d3cd0SFeifei Xu #define SDMA0_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2563c62d3cd0SFeifei Xu //SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI 2564c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2565c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2566c62d3cd0SFeifei Xu //SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO 2567c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2568c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2569c62d3cd0SFeifei Xu //SDMA0_RLC5_RB_AQL_CNTL 2570c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2571c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2572c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2573c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2574c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2575c62d3cd0SFeifei Xu #define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2576c62d3cd0SFeifei Xu //SDMA0_RLC5_MINOR_PTR_UPDATE 2577c62d3cd0SFeifei Xu #define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2578c62d3cd0SFeifei Xu #define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2579c62d3cd0SFeifei Xu //SDMA0_RLC5_MIDCMD_DATA0 2580c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 2581c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2582c62d3cd0SFeifei Xu //SDMA0_RLC5_MIDCMD_DATA1 2583c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 2584c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2585c62d3cd0SFeifei Xu //SDMA0_RLC5_MIDCMD_DATA2 2586c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 2587c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2588c62d3cd0SFeifei Xu //SDMA0_RLC5_MIDCMD_DATA3 2589c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 2590c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2591c62d3cd0SFeifei Xu //SDMA0_RLC5_MIDCMD_DATA4 2592c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 2593c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2594c62d3cd0SFeifei Xu //SDMA0_RLC5_MIDCMD_DATA5 2595c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 2596c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2597c62d3cd0SFeifei Xu //SDMA0_RLC5_MIDCMD_DATA6 2598c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 2599c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2600c62d3cd0SFeifei Xu //SDMA0_RLC5_MIDCMD_DATA7 2601c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 2602c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2603c62d3cd0SFeifei Xu //SDMA0_RLC5_MIDCMD_DATA8 2604c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 2605c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2606c62d3cd0SFeifei Xu //SDMA0_RLC5_MIDCMD_CNTL 2607c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2608c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2609c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2610c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2611c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2612c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2613c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2614c62d3cd0SFeifei Xu #define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2615c62d3cd0SFeifei Xu //SDMA0_RLC6_RB_CNTL 2616c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 2617c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 2618c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2619c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2620c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2621c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2622c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 2623c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 2624c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2625c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2626c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2627c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2628c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2629c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2630c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L 2631c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L 2632c62d3cd0SFeifei Xu //SDMA0_RLC6_RB_BASE 2633c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_BASE__ADDR__SHIFT 0x0 2634c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2635c62d3cd0SFeifei Xu //SDMA0_RLC6_RB_BASE_HI 2636c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 2637c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2638c62d3cd0SFeifei Xu //SDMA0_RLC6_RB_RPTR 2639c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 2640c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2641c62d3cd0SFeifei Xu //SDMA0_RLC6_RB_RPTR_HI 2642c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 2643c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2644c62d3cd0SFeifei Xu //SDMA0_RLC6_RB_WPTR 2645c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 2646c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2647c62d3cd0SFeifei Xu //SDMA0_RLC6_RB_WPTR_HI 2648c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 2649c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2650c62d3cd0SFeifei Xu //SDMA0_RLC6_RB_WPTR_POLL_CNTL 2651c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2652c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2653c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2654c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2655c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2656c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2657c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2658c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2659c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2660c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2661c62d3cd0SFeifei Xu //SDMA0_RLC6_RB_RPTR_ADDR_HI 2662c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2663c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2664c62d3cd0SFeifei Xu //SDMA0_RLC6_RB_RPTR_ADDR_LO 2665c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2666c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2667c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2668c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2669c62d3cd0SFeifei Xu //SDMA0_RLC6_IB_CNTL 2670c62d3cd0SFeifei Xu #define SDMA0_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 2671c62d3cd0SFeifei Xu #define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2672c62d3cd0SFeifei Xu #define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2673c62d3cd0SFeifei Xu #define SDMA0_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 2674c62d3cd0SFeifei Xu #define SDMA0_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2675c62d3cd0SFeifei Xu #define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2676c62d3cd0SFeifei Xu #define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2677c62d3cd0SFeifei Xu #define SDMA0_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2678c62d3cd0SFeifei Xu //SDMA0_RLC6_IB_RPTR 2679c62d3cd0SFeifei Xu #define SDMA0_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 2680c62d3cd0SFeifei Xu #define SDMA0_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2681c62d3cd0SFeifei Xu //SDMA0_RLC6_IB_OFFSET 2682c62d3cd0SFeifei Xu #define SDMA0_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 2683c62d3cd0SFeifei Xu #define SDMA0_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2684c62d3cd0SFeifei Xu //SDMA0_RLC6_IB_BASE_LO 2685c62d3cd0SFeifei Xu #define SDMA0_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 2686c62d3cd0SFeifei Xu #define SDMA0_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2687c62d3cd0SFeifei Xu //SDMA0_RLC6_IB_BASE_HI 2688c62d3cd0SFeifei Xu #define SDMA0_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 2689c62d3cd0SFeifei Xu #define SDMA0_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2690c62d3cd0SFeifei Xu //SDMA0_RLC6_IB_SIZE 2691c62d3cd0SFeifei Xu #define SDMA0_RLC6_IB_SIZE__SIZE__SHIFT 0x0 2692c62d3cd0SFeifei Xu #define SDMA0_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL 2693c62d3cd0SFeifei Xu //SDMA0_RLC6_SKIP_CNTL 2694c62d3cd0SFeifei Xu #define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2695c62d3cd0SFeifei Xu #define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2696c62d3cd0SFeifei Xu //SDMA0_RLC6_CONTEXT_STATUS 2697c62d3cd0SFeifei Xu #define SDMA0_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2698c62d3cd0SFeifei Xu #define SDMA0_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 2699c62d3cd0SFeifei Xu #define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2700c62d3cd0SFeifei Xu #define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2701c62d3cd0SFeifei Xu #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2702c62d3cd0SFeifei Xu #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2703c62d3cd0SFeifei Xu #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2704c62d3cd0SFeifei Xu #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2705c62d3cd0SFeifei Xu #define SDMA0_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2706c62d3cd0SFeifei Xu #define SDMA0_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2707c62d3cd0SFeifei Xu #define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2708c62d3cd0SFeifei Xu #define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2709c62d3cd0SFeifei Xu #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2710c62d3cd0SFeifei Xu #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2711c62d3cd0SFeifei Xu #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2712c62d3cd0SFeifei Xu #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2713c62d3cd0SFeifei Xu //SDMA0_RLC6_DOORBELL 2714c62d3cd0SFeifei Xu #define SDMA0_RLC6_DOORBELL__ENABLE__SHIFT 0x1c 2715c62d3cd0SFeifei Xu #define SDMA0_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e 2716c62d3cd0SFeifei Xu #define SDMA0_RLC6_DOORBELL__ENABLE_MASK 0x10000000L 2717c62d3cd0SFeifei Xu #define SDMA0_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L 2718c62d3cd0SFeifei Xu //SDMA0_RLC6_STATUS 2719c62d3cd0SFeifei Xu #define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2720c62d3cd0SFeifei Xu #define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2721c62d3cd0SFeifei Xu #define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2722c62d3cd0SFeifei Xu #define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2723c62d3cd0SFeifei Xu //SDMA0_RLC6_DOORBELL_LOG 2724c62d3cd0SFeifei Xu #define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2725c62d3cd0SFeifei Xu #define SDMA0_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 2726c62d3cd0SFeifei Xu #define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2727c62d3cd0SFeifei Xu #define SDMA0_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2728c62d3cd0SFeifei Xu //SDMA0_RLC6_WATERMARK 2729c62d3cd0SFeifei Xu #define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2730c62d3cd0SFeifei Xu #define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2731c62d3cd0SFeifei Xu #define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2732c62d3cd0SFeifei Xu #define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2733c62d3cd0SFeifei Xu //SDMA0_RLC6_DOORBELL_OFFSET 2734c62d3cd0SFeifei Xu #define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2735c62d3cd0SFeifei Xu #define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2736c62d3cd0SFeifei Xu //SDMA0_RLC6_CSA_ADDR_LO 2737c62d3cd0SFeifei Xu #define SDMA0_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 2738c62d3cd0SFeifei Xu #define SDMA0_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2739c62d3cd0SFeifei Xu //SDMA0_RLC6_CSA_ADDR_HI 2740c62d3cd0SFeifei Xu #define SDMA0_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 2741c62d3cd0SFeifei Xu #define SDMA0_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2742c62d3cd0SFeifei Xu //SDMA0_RLC6_IB_SUB_REMAIN 2743c62d3cd0SFeifei Xu #define SDMA0_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2744c62d3cd0SFeifei Xu #define SDMA0_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2745c62d3cd0SFeifei Xu //SDMA0_RLC6_PREEMPT 2746c62d3cd0SFeifei Xu #define SDMA0_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 2747c62d3cd0SFeifei Xu #define SDMA0_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2748c62d3cd0SFeifei Xu //SDMA0_RLC6_DUMMY_REG 2749c62d3cd0SFeifei Xu #define SDMA0_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 2750c62d3cd0SFeifei Xu #define SDMA0_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2751c62d3cd0SFeifei Xu //SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI 2752c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2753c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2754c62d3cd0SFeifei Xu //SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO 2755c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2756c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2757c62d3cd0SFeifei Xu //SDMA0_RLC6_RB_AQL_CNTL 2758c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2759c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2760c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2761c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2762c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2763c62d3cd0SFeifei Xu #define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2764c62d3cd0SFeifei Xu //SDMA0_RLC6_MINOR_PTR_UPDATE 2765c62d3cd0SFeifei Xu #define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2766c62d3cd0SFeifei Xu #define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2767c62d3cd0SFeifei Xu //SDMA0_RLC6_MIDCMD_DATA0 2768c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 2769c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2770c62d3cd0SFeifei Xu //SDMA0_RLC6_MIDCMD_DATA1 2771c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 2772c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2773c62d3cd0SFeifei Xu //SDMA0_RLC6_MIDCMD_DATA2 2774c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 2775c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2776c62d3cd0SFeifei Xu //SDMA0_RLC6_MIDCMD_DATA3 2777c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 2778c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2779c62d3cd0SFeifei Xu //SDMA0_RLC6_MIDCMD_DATA4 2780c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 2781c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2782c62d3cd0SFeifei Xu //SDMA0_RLC6_MIDCMD_DATA5 2783c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 2784c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2785c62d3cd0SFeifei Xu //SDMA0_RLC6_MIDCMD_DATA6 2786c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 2787c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2788c62d3cd0SFeifei Xu //SDMA0_RLC6_MIDCMD_DATA7 2789c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 2790c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2791c62d3cd0SFeifei Xu //SDMA0_RLC6_MIDCMD_DATA8 2792c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 2793c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2794c62d3cd0SFeifei Xu //SDMA0_RLC6_MIDCMD_CNTL 2795c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2796c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2797c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2798c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2799c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2800c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2801c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2802c62d3cd0SFeifei Xu #define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2803c62d3cd0SFeifei Xu //SDMA0_RLC7_RB_CNTL 2804c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 2805c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 2806c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 2807c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 2808c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 2809c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 2810c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 2811c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 2812c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L 2813c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL 2814c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 2815c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 2816c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 2817c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 2818c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L 2819c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L 2820c62d3cd0SFeifei Xu //SDMA0_RLC7_RB_BASE 2821c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_BASE__ADDR__SHIFT 0x0 2822c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL 2823c62d3cd0SFeifei Xu //SDMA0_RLC7_RB_BASE_HI 2824c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 2825c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 2826c62d3cd0SFeifei Xu //SDMA0_RLC7_RB_RPTR 2827c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 2828c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 2829c62d3cd0SFeifei Xu //SDMA0_RLC7_RB_RPTR_HI 2830c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 2831c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2832c62d3cd0SFeifei Xu //SDMA0_RLC7_RB_WPTR 2833c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 2834c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 2835c62d3cd0SFeifei Xu //SDMA0_RLC7_RB_WPTR_HI 2836c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 2837c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 2838c62d3cd0SFeifei Xu //SDMA0_RLC7_RB_WPTR_POLL_CNTL 2839c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 2840c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 2841c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 2842c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 2843c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2844c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 2845c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 2846c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 2847c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 2848c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2849c62d3cd0SFeifei Xu //SDMA0_RLC7_RB_RPTR_ADDR_HI 2850c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 2851c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2852c62d3cd0SFeifei Xu //SDMA0_RLC7_RB_RPTR_ADDR_LO 2853c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 2854c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 2855c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 2856c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2857c62d3cd0SFeifei Xu //SDMA0_RLC7_IB_CNTL 2858c62d3cd0SFeifei Xu #define SDMA0_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 2859c62d3cd0SFeifei Xu #define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 2860c62d3cd0SFeifei Xu #define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 2861c62d3cd0SFeifei Xu #define SDMA0_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 2862c62d3cd0SFeifei Xu #define SDMA0_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L 2863c62d3cd0SFeifei Xu #define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 2864c62d3cd0SFeifei Xu #define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 2865c62d3cd0SFeifei Xu #define SDMA0_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L 2866c62d3cd0SFeifei Xu //SDMA0_RLC7_IB_RPTR 2867c62d3cd0SFeifei Xu #define SDMA0_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 2868c62d3cd0SFeifei Xu #define SDMA0_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL 2869c62d3cd0SFeifei Xu //SDMA0_RLC7_IB_OFFSET 2870c62d3cd0SFeifei Xu #define SDMA0_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 2871c62d3cd0SFeifei Xu #define SDMA0_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 2872c62d3cd0SFeifei Xu //SDMA0_RLC7_IB_BASE_LO 2873c62d3cd0SFeifei Xu #define SDMA0_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 2874c62d3cd0SFeifei Xu #define SDMA0_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 2875c62d3cd0SFeifei Xu //SDMA0_RLC7_IB_BASE_HI 2876c62d3cd0SFeifei Xu #define SDMA0_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 2877c62d3cd0SFeifei Xu #define SDMA0_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 2878c62d3cd0SFeifei Xu //SDMA0_RLC7_IB_SIZE 2879c62d3cd0SFeifei Xu #define SDMA0_RLC7_IB_SIZE__SIZE__SHIFT 0x0 2880c62d3cd0SFeifei Xu #define SDMA0_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL 2881c62d3cd0SFeifei Xu //SDMA0_RLC7_SKIP_CNTL 2882c62d3cd0SFeifei Xu #define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 2883c62d3cd0SFeifei Xu #define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 2884c62d3cd0SFeifei Xu //SDMA0_RLC7_CONTEXT_STATUS 2885c62d3cd0SFeifei Xu #define SDMA0_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 2886c62d3cd0SFeifei Xu #define SDMA0_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 2887c62d3cd0SFeifei Xu #define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 2888c62d3cd0SFeifei Xu #define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 2889c62d3cd0SFeifei Xu #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 2890c62d3cd0SFeifei Xu #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 2891c62d3cd0SFeifei Xu #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 2892c62d3cd0SFeifei Xu #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 2893c62d3cd0SFeifei Xu #define SDMA0_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 2894c62d3cd0SFeifei Xu #define SDMA0_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L 2895c62d3cd0SFeifei Xu #define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 2896c62d3cd0SFeifei Xu #define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 2897c62d3cd0SFeifei Xu #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 2898c62d3cd0SFeifei Xu #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 2899c62d3cd0SFeifei Xu #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 2900c62d3cd0SFeifei Xu #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 2901c62d3cd0SFeifei Xu //SDMA0_RLC7_DOORBELL 2902c62d3cd0SFeifei Xu #define SDMA0_RLC7_DOORBELL__ENABLE__SHIFT 0x1c 2903c62d3cd0SFeifei Xu #define SDMA0_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e 2904c62d3cd0SFeifei Xu #define SDMA0_RLC7_DOORBELL__ENABLE_MASK 0x10000000L 2905c62d3cd0SFeifei Xu #define SDMA0_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L 2906c62d3cd0SFeifei Xu //SDMA0_RLC7_STATUS 2907c62d3cd0SFeifei Xu #define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 2908c62d3cd0SFeifei Xu #define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 2909c62d3cd0SFeifei Xu #define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 2910c62d3cd0SFeifei Xu #define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 2911c62d3cd0SFeifei Xu //SDMA0_RLC7_DOORBELL_LOG 2912c62d3cd0SFeifei Xu #define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 2913c62d3cd0SFeifei Xu #define SDMA0_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 2914c62d3cd0SFeifei Xu #define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 2915c62d3cd0SFeifei Xu #define SDMA0_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 2916c62d3cd0SFeifei Xu //SDMA0_RLC7_WATERMARK 2917c62d3cd0SFeifei Xu #define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 2918c62d3cd0SFeifei Xu #define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 2919c62d3cd0SFeifei Xu #define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 2920c62d3cd0SFeifei Xu #define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 2921c62d3cd0SFeifei Xu //SDMA0_RLC7_DOORBELL_OFFSET 2922c62d3cd0SFeifei Xu #define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 2923c62d3cd0SFeifei Xu #define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 2924c62d3cd0SFeifei Xu //SDMA0_RLC7_CSA_ADDR_LO 2925c62d3cd0SFeifei Xu #define SDMA0_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 2926c62d3cd0SFeifei Xu #define SDMA0_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2927c62d3cd0SFeifei Xu //SDMA0_RLC7_CSA_ADDR_HI 2928c62d3cd0SFeifei Xu #define SDMA0_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 2929c62d3cd0SFeifei Xu #define SDMA0_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2930c62d3cd0SFeifei Xu //SDMA0_RLC7_IB_SUB_REMAIN 2931c62d3cd0SFeifei Xu #define SDMA0_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 2932c62d3cd0SFeifei Xu #define SDMA0_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 2933c62d3cd0SFeifei Xu //SDMA0_RLC7_PREEMPT 2934c62d3cd0SFeifei Xu #define SDMA0_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 2935c62d3cd0SFeifei Xu #define SDMA0_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L 2936c62d3cd0SFeifei Xu //SDMA0_RLC7_DUMMY_REG 2937c62d3cd0SFeifei Xu #define SDMA0_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 2938c62d3cd0SFeifei Xu #define SDMA0_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 2939c62d3cd0SFeifei Xu //SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI 2940c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 2941c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 2942c62d3cd0SFeifei Xu //SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO 2943c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 2944c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 2945c62d3cd0SFeifei Xu //SDMA0_RLC7_RB_AQL_CNTL 2946c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 2947c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 2948c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 2949c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 2950c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 2951c62d3cd0SFeifei Xu #define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 2952c62d3cd0SFeifei Xu //SDMA0_RLC7_MINOR_PTR_UPDATE 2953c62d3cd0SFeifei Xu #define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 2954c62d3cd0SFeifei Xu #define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 2955c62d3cd0SFeifei Xu //SDMA0_RLC7_MIDCMD_DATA0 2956c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 2957c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 2958c62d3cd0SFeifei Xu //SDMA0_RLC7_MIDCMD_DATA1 2959c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 2960c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 2961c62d3cd0SFeifei Xu //SDMA0_RLC7_MIDCMD_DATA2 2962c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 2963c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 2964c62d3cd0SFeifei Xu //SDMA0_RLC7_MIDCMD_DATA3 2965c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 2966c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 2967c62d3cd0SFeifei Xu //SDMA0_RLC7_MIDCMD_DATA4 2968c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 2969c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 2970c62d3cd0SFeifei Xu //SDMA0_RLC7_MIDCMD_DATA5 2971c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 2972c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 2973c62d3cd0SFeifei Xu //SDMA0_RLC7_MIDCMD_DATA6 2974c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 2975c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 2976c62d3cd0SFeifei Xu //SDMA0_RLC7_MIDCMD_DATA7 2977c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 2978c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 2979c62d3cd0SFeifei Xu //SDMA0_RLC7_MIDCMD_DATA8 2980c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 2981c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 2982c62d3cd0SFeifei Xu //SDMA0_RLC7_MIDCMD_CNTL 2983c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 2984c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 2985c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 2986c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 2987c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 2988c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 2989c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 2990c62d3cd0SFeifei Xu #define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 2991c62d3cd0SFeifei Xu 2992c62d3cd0SFeifei Xu #endif 2993