1812f77b7SFeifei Xu /* 2812f77b7SFeifei Xu * Copyright (C) 2017 Advanced Micro Devices, Inc. 3812f77b7SFeifei Xu * 4812f77b7SFeifei Xu * Permission is hereby granted, free of charge, to any person obtaining a 5812f77b7SFeifei Xu * copy of this software and associated documentation files (the "Software"), 6812f77b7SFeifei Xu * to deal in the Software without restriction, including without limitation 7812f77b7SFeifei Xu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8812f77b7SFeifei Xu * and/or sell copies of the Software, and to permit persons to whom the 9812f77b7SFeifei Xu * Software is furnished to do so, subject to the following conditions: 10812f77b7SFeifei Xu * 11812f77b7SFeifei Xu * The above copyright notice and this permission notice shall be included 12812f77b7SFeifei Xu * in all copies or substantial portions of the Software. 13812f77b7SFeifei Xu * 14812f77b7SFeifei Xu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15812f77b7SFeifei Xu * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16812f77b7SFeifei Xu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17812f77b7SFeifei Xu * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18812f77b7SFeifei Xu * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19812f77b7SFeifei Xu * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20812f77b7SFeifei Xu */ 21812f77b7SFeifei Xu #ifndef _sdma0_4_0_SH_MASK_HEADER 22812f77b7SFeifei Xu #define _sdma0_4_0_SH_MASK_HEADER 23812f77b7SFeifei Xu 24812f77b7SFeifei Xu 25812f77b7SFeifei Xu // addressBlock: sdma0_sdma0dec 26812f77b7SFeifei Xu //SDMA0_UCODE_ADDR 27812f77b7SFeifei Xu #define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 28812f77b7SFeifei Xu #define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL 29812f77b7SFeifei Xu //SDMA0_UCODE_DATA 30812f77b7SFeifei Xu #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 31812f77b7SFeifei Xu #define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 32812f77b7SFeifei Xu //SDMA0_VM_CNTL 33812f77b7SFeifei Xu #define SDMA0_VM_CNTL__CMD__SHIFT 0x0 34812f77b7SFeifei Xu #define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL 35812f77b7SFeifei Xu //SDMA0_VM_CTX_LO 36812f77b7SFeifei Xu #define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 37812f77b7SFeifei Xu #define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 38812f77b7SFeifei Xu //SDMA0_VM_CTX_HI 39812f77b7SFeifei Xu #define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 40812f77b7SFeifei Xu #define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 41812f77b7SFeifei Xu //SDMA0_ACTIVE_FCN_ID 42812f77b7SFeifei Xu #define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 43812f77b7SFeifei Xu #define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 44812f77b7SFeifei Xu #define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f 45812f77b7SFeifei Xu #define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 46812f77b7SFeifei Xu #define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 47812f77b7SFeifei Xu #define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L 48812f77b7SFeifei Xu //SDMA0_VM_CTX_CNTL 49812f77b7SFeifei Xu #define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 50812f77b7SFeifei Xu #define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 51812f77b7SFeifei Xu #define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L 52812f77b7SFeifei Xu #define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L 53812f77b7SFeifei Xu //SDMA0_VIRT_RESET_REQ 54812f77b7SFeifei Xu #define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 55812f77b7SFeifei Xu #define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f 56812f77b7SFeifei Xu #define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 57812f77b7SFeifei Xu #define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L 58812f77b7SFeifei Xu //SDMA0_VF_ENABLE 59812f77b7SFeifei Xu #define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 60812f77b7SFeifei Xu #define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 61812f77b7SFeifei Xu //SDMA0_CONTEXT_REG_TYPE0 62812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 63812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 64812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 65812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 66812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 67812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 68812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 69812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 70812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 71812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 72812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa 73812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb 74812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc 75812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd 76812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe 77812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf 78812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 79812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 80812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 81812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 82812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L 83812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L 84812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L 85812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L 86812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L 87812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L 88812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L 89812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 90812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 91812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 92812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L 93812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L 94812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L 95812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L 96812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L 97812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L 98812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L 99812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L 100812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L 101812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L 102812f77b7SFeifei Xu //SDMA0_CONTEXT_REG_TYPE1 103812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 104812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 105812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa 106812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb 107812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc 108812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd 109812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 110812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf 111812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 112812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 113812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 114812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 115812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 116812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 117812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 118812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L 119812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L 120812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L 121812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L 122812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L 123812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L 124812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L 125812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L 126812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L 127812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L 128812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 129812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 130812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L 131812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 132812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 133812f77b7SFeifei Xu //SDMA0_CONTEXT_REG_TYPE2 134812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 135812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 136812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 137812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 138812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 139812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 140812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 141812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 142812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 143812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 144812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 145812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L 146812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L 147812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L 148812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L 149812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L 150812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L 151812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L 152812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L 153812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L 154812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L 155812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L 156812f77b7SFeifei Xu //SDMA0_CONTEXT_REG_TYPE3 157812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 158812f77b7SFeifei Xu #define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 159812f77b7SFeifei Xu //SDMA0_PUB_REG_TYPE0 160812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 161812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 162812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 163812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 164812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 165812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 166812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 167812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 168812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 169812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 170812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb 171812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc 172812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd 173812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe 174812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf 175812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 176812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 177812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 178812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 179812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 180812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 181812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a 182812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b 183812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c 184812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d 185812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e 186812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f 187812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L 188812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L 189812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L 190812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L 191812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L 192812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L 193812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L 194812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L 195812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L 196812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L 197812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L 198812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L 199812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L 200812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L 201812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L 202812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L 203812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L 204812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L 205812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L 206812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L 207812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L 208812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L 209812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L 210812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L 211812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L 212812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L 213812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L 214812f77b7SFeifei Xu //SDMA0_PUB_REG_TYPE1 215812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 216812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 217812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 218812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 219812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 220812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 221812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 222812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 223812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 224812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 225812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa 226812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb 227812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc 228812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd 229812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 230812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 231812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 232812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 233812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 234812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 235812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 236812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 237812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 238812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 239812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 240812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 241812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a 242812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b 243812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c 244812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d 245812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e 246812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f 247812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L 248812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 249812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L 250812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L 251812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L 252812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L 253812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L 254812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L 255812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L 256812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L 257812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L 258812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L 259812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L 260812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L 261812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 262812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 263812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 264812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 265812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L 266812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L 267812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L 268812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L 269812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L 270812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L 271812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L 272812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L 273812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L 274812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L 275812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L 276812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L 277812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L 278812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L 279812f77b7SFeifei Xu //SDMA0_PUB_REG_TYPE2 280812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 281812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 282812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 283812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 284812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 285812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 286812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 287812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 288812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 289812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 290812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa 291812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb 292812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc 293812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd 294812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe 295812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0xf 296812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 297812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 298812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 299812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 300812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 301812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 302812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16 303812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 304812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 305812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 306812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a 307812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b 308812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL__SHIFT 0x1c 309812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d 310812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e 311812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f 312812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L 313812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L 314812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L 315812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L 316812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L 317812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L 318812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L 319812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L 320812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L 321812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L 322812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L 323812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L 324812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L 325812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L 326812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L 327812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L 328812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L 329812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L 330812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L 331812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L 332812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L 333812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L 334812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L 335812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L 336812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L 337812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L 338812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L 339812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L 340812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL_MASK 0x10000000L 341812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L 342812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L 343812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L 344812f77b7SFeifei Xu //SDMA0_PUB_REG_TYPE3 345812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 346812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 347812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 348812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L 349812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 350812f77b7SFeifei Xu #define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL 351812f77b7SFeifei Xu //SDMA0_MMHUB_CNTL 352812f77b7SFeifei Xu #define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 353812f77b7SFeifei Xu #define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 354812f77b7SFeifei Xu //SDMA0_CONTEXT_GROUP_BOUNDARY 355812f77b7SFeifei Xu #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 356812f77b7SFeifei Xu #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 357812f77b7SFeifei Xu //SDMA0_POWER_CNTL 358812f77b7SFeifei Xu #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 359812f77b7SFeifei Xu #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 360812f77b7SFeifei Xu #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 361812f77b7SFeifei Xu #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 362812f77b7SFeifei Xu #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 363812f77b7SFeifei Xu #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 364812f77b7SFeifei Xu #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 365812f77b7SFeifei Xu #define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 366812f77b7SFeifei Xu #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L 367812f77b7SFeifei Xu #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L 368812f77b7SFeifei Xu #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L 369812f77b7SFeifei Xu #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 370812f77b7SFeifei Xu #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 371812f77b7SFeifei Xu #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 372812f77b7SFeifei Xu #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 373812f77b7SFeifei Xu #define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 374812f77b7SFeifei Xu //SDMA0_CLK_CTRL 375812f77b7SFeifei Xu #define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 376812f77b7SFeifei Xu #define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 377812f77b7SFeifei Xu #define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc 378812f77b7SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 379812f77b7SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 380812f77b7SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 381812f77b7SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 382812f77b7SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 383812f77b7SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 384812f77b7SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 385812f77b7SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 386812f77b7SFeifei Xu #define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 387812f77b7SFeifei Xu #define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 388812f77b7SFeifei Xu #define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L 389812f77b7SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 390812f77b7SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 391812f77b7SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 392812f77b7SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 393812f77b7SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 394812f77b7SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 395812f77b7SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 396812f77b7SFeifei Xu #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 397812f77b7SFeifei Xu //SDMA0_CNTL 398812f77b7SFeifei Xu #define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 399812f77b7SFeifei Xu #define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 400812f77b7SFeifei Xu #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 401812f77b7SFeifei Xu #define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 402812f77b7SFeifei Xu #define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 403812f77b7SFeifei Xu #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 404812f77b7SFeifei Xu #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 405812f77b7SFeifei Xu #define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 406812f77b7SFeifei Xu #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 407812f77b7SFeifei Xu #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 408812f77b7SFeifei Xu #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 409812f77b7SFeifei Xu #define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L 410812f77b7SFeifei Xu #define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 411812f77b7SFeifei Xu #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 412812f77b7SFeifei Xu #define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 413812f77b7SFeifei Xu #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 414812f77b7SFeifei Xu #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 415812f77b7SFeifei Xu #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 416812f77b7SFeifei Xu #define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 417812f77b7SFeifei Xu #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 418812f77b7SFeifei Xu #define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 419812f77b7SFeifei Xu #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 420812f77b7SFeifei Xu //SDMA0_CHICKEN_BITS 421812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 422812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 423812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 424812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 425812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 426812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 427812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 428812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 429812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 430812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 431812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 432812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 433812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 434812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 435812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 436812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 437812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 438812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 439812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 440812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 441812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 442812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 443812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 444812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L 445812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L 446812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L 447812f77b7SFeifei Xu //SDMA0_GB_ADDR_CONFIG 448812f77b7SFeifei Xu #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 449812f77b7SFeifei Xu #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 450812f77b7SFeifei Xu #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 451812f77b7SFeifei Xu #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 452812f77b7SFeifei Xu #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 453812f77b7SFeifei Xu #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 454812f77b7SFeifei Xu #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 455812f77b7SFeifei Xu #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 456812f77b7SFeifei Xu #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 457812f77b7SFeifei Xu #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 458812f77b7SFeifei Xu //SDMA0_GB_ADDR_CONFIG_READ 459812f77b7SFeifei Xu #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 460812f77b7SFeifei Xu #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 461812f77b7SFeifei Xu #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 462812f77b7SFeifei Xu #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 463812f77b7SFeifei Xu #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 464812f77b7SFeifei Xu #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 465812f77b7SFeifei Xu #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 466812f77b7SFeifei Xu #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 467812f77b7SFeifei Xu #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 468812f77b7SFeifei Xu #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 469812f77b7SFeifei Xu //SDMA0_RB_RPTR_FETCH_HI 470812f77b7SFeifei Xu #define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 471812f77b7SFeifei Xu #define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 472812f77b7SFeifei Xu //SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 473812f77b7SFeifei Xu #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 474812f77b7SFeifei Xu #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 475812f77b7SFeifei Xu //SDMA0_RB_RPTR_FETCH 476812f77b7SFeifei Xu #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 477812f77b7SFeifei Xu #define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 478812f77b7SFeifei Xu //SDMA0_IB_OFFSET_FETCH 479812f77b7SFeifei Xu #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 480812f77b7SFeifei Xu #define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 481812f77b7SFeifei Xu //SDMA0_PROGRAM 482812f77b7SFeifei Xu #define SDMA0_PROGRAM__STREAM__SHIFT 0x0 483812f77b7SFeifei Xu #define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL 484812f77b7SFeifei Xu //SDMA0_STATUS_REG 485812f77b7SFeifei Xu #define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 486812f77b7SFeifei Xu #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 487812f77b7SFeifei Xu #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 488812f77b7SFeifei Xu #define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 489812f77b7SFeifei Xu #define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 490812f77b7SFeifei Xu #define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 491812f77b7SFeifei Xu #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 492812f77b7SFeifei Xu #define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 493812f77b7SFeifei Xu #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 494812f77b7SFeifei Xu #define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 495812f77b7SFeifei Xu #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa 496812f77b7SFeifei Xu #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 497812f77b7SFeifei Xu #define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc 498812f77b7SFeifei Xu #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 499812f77b7SFeifei Xu #define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe 500812f77b7SFeifei Xu #define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 501812f77b7SFeifei Xu #define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 502812f77b7SFeifei Xu #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 503812f77b7SFeifei Xu #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 504812f77b7SFeifei Xu #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 505812f77b7SFeifei Xu #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 506812f77b7SFeifei Xu #define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 507812f77b7SFeifei Xu #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 508812f77b7SFeifei Xu #define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 509812f77b7SFeifei Xu #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a 510812f77b7SFeifei Xu #define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 511812f77b7SFeifei Xu #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 512812f77b7SFeifei Xu #define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e 513812f77b7SFeifei Xu #define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 514812f77b7SFeifei Xu #define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L 515812f77b7SFeifei Xu #define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L 516812f77b7SFeifei Xu #define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L 517812f77b7SFeifei Xu #define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L 518812f77b7SFeifei Xu #define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 519812f77b7SFeifei Xu #define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 520812f77b7SFeifei Xu #define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 521812f77b7SFeifei Xu #define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 522812f77b7SFeifei Xu #define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 523812f77b7SFeifei Xu #define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L 524812f77b7SFeifei Xu #define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L 525812f77b7SFeifei Xu #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 526812f77b7SFeifei Xu #define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L 527812f77b7SFeifei Xu #define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 528812f77b7SFeifei Xu #define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 529812f77b7SFeifei Xu #define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 530812f77b7SFeifei Xu #define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 531812f77b7SFeifei Xu #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 532812f77b7SFeifei Xu #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 533812f77b7SFeifei Xu #define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 534812f77b7SFeifei Xu #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 535812f77b7SFeifei Xu #define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 536812f77b7SFeifei Xu #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 537812f77b7SFeifei Xu #define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 538812f77b7SFeifei Xu #define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L 539812f77b7SFeifei Xu #define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 540812f77b7SFeifei Xu #define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 541812f77b7SFeifei Xu #define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L 542812f77b7SFeifei Xu #define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 543812f77b7SFeifei Xu //SDMA0_STATUS1_REG 544812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 545812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 546812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 547812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 548812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 549812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 550812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 551812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 552812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 553812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 554812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 555812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf 556812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 557812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 558812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 559812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 560812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 561812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 562812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 563812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 564812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 565812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 566812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 567812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 568812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 569812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L 570812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 571812f77b7SFeifei Xu #define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 572812f77b7SFeifei Xu //SDMA0_RD_BURST_CNTL 573812f77b7SFeifei Xu #define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 574812f77b7SFeifei Xu #define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 575812f77b7SFeifei Xu //SDMA0_HBM_PAGE_CONFIG 576812f77b7SFeifei Xu #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 577812f77b7SFeifei Xu #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L 578812f77b7SFeifei Xu //SDMA0_UCODE_CHECKSUM 579812f77b7SFeifei Xu #define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 580812f77b7SFeifei Xu #define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 581812f77b7SFeifei Xu //SDMA0_F32_CNTL 582812f77b7SFeifei Xu #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 583812f77b7SFeifei Xu #define SDMA0_F32_CNTL__STEP__SHIFT 0x1 584812f77b7SFeifei Xu #define SDMA0_F32_CNTL__HALT_MASK 0x00000001L 585812f77b7SFeifei Xu #define SDMA0_F32_CNTL__STEP_MASK 0x00000002L 586812f77b7SFeifei Xu //SDMA0_FREEZE 587812f77b7SFeifei Xu #define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 588812f77b7SFeifei Xu #define SDMA0_FREEZE__FREEZE__SHIFT 0x4 589812f77b7SFeifei Xu #define SDMA0_FREEZE__FROZEN__SHIFT 0x5 590812f77b7SFeifei Xu #define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 591812f77b7SFeifei Xu #define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L 592812f77b7SFeifei Xu #define SDMA0_FREEZE__FREEZE_MASK 0x00000010L 593812f77b7SFeifei Xu #define SDMA0_FREEZE__FROZEN_MASK 0x00000020L 594812f77b7SFeifei Xu #define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L 595812f77b7SFeifei Xu //SDMA0_PHASE0_QUANTUM 596812f77b7SFeifei Xu #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 597812f77b7SFeifei Xu #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 598812f77b7SFeifei Xu #define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 599812f77b7SFeifei Xu #define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 600812f77b7SFeifei Xu #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 601812f77b7SFeifei Xu #define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 602812f77b7SFeifei Xu //SDMA0_PHASE1_QUANTUM 603812f77b7SFeifei Xu #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 604812f77b7SFeifei Xu #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 605812f77b7SFeifei Xu #define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 606812f77b7SFeifei Xu #define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 607812f77b7SFeifei Xu #define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 608812f77b7SFeifei Xu #define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 609812f77b7SFeifei Xu //SDMA_POWER_GATING 610812f77b7SFeifei Xu #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 611812f77b7SFeifei Xu #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 612812f77b7SFeifei Xu #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 613812f77b7SFeifei Xu #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 614812f77b7SFeifei Xu #define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 615812f77b7SFeifei Xu #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L 616812f77b7SFeifei Xu #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L 617812f77b7SFeifei Xu #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L 618812f77b7SFeifei Xu #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L 619812f77b7SFeifei Xu #define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L 620812f77b7SFeifei Xu //SDMA_PGFSM_CONFIG 621812f77b7SFeifei Xu #define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 622812f77b7SFeifei Xu #define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 623812f77b7SFeifei Xu #define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 624812f77b7SFeifei Xu #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa 625812f77b7SFeifei Xu #define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb 626812f77b7SFeifei Xu #define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc 627812f77b7SFeifei Xu #define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd 628812f77b7SFeifei Xu #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b 629812f77b7SFeifei Xu #define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 630812f77b7SFeifei Xu #define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL 631812f77b7SFeifei Xu #define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L 632812f77b7SFeifei Xu #define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L 633812f77b7SFeifei Xu #define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L 634812f77b7SFeifei Xu #define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L 635812f77b7SFeifei Xu #define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L 636812f77b7SFeifei Xu #define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L 637812f77b7SFeifei Xu #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L 638812f77b7SFeifei Xu #define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L 639812f77b7SFeifei Xu //SDMA_PGFSM_WRITE 640812f77b7SFeifei Xu #define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 641812f77b7SFeifei Xu #define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL 642812f77b7SFeifei Xu //SDMA_PGFSM_READ 643812f77b7SFeifei Xu #define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 644812f77b7SFeifei Xu #define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL 645812f77b7SFeifei Xu //SDMA0_EDC_CONFIG 646812f77b7SFeifei Xu #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 647812f77b7SFeifei Xu #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 648812f77b7SFeifei Xu #define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 649812f77b7SFeifei Xu #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L 650812f77b7SFeifei Xu //SDMA0_BA_THRESHOLD 651812f77b7SFeifei Xu #define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 652812f77b7SFeifei Xu #define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 653812f77b7SFeifei Xu #define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 654812f77b7SFeifei Xu #define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 655812f77b7SFeifei Xu //SDMA0_ID 656812f77b7SFeifei Xu #define SDMA0_ID__DEVICE_ID__SHIFT 0x0 657812f77b7SFeifei Xu #define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL 658812f77b7SFeifei Xu //SDMA0_VERSION 659812f77b7SFeifei Xu #define SDMA0_VERSION__MINVER__SHIFT 0x0 660812f77b7SFeifei Xu #define SDMA0_VERSION__MAJVER__SHIFT 0x8 661812f77b7SFeifei Xu #define SDMA0_VERSION__REV__SHIFT 0x10 662812f77b7SFeifei Xu #define SDMA0_VERSION__MINVER_MASK 0x0000007FL 663812f77b7SFeifei Xu #define SDMA0_VERSION__MAJVER_MASK 0x00007F00L 664812f77b7SFeifei Xu #define SDMA0_VERSION__REV_MASK 0x003F0000L 665812f77b7SFeifei Xu //SDMA0_EDC_COUNTER 666812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 667812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 668812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 669812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 670812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 671812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 672812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 673812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 674812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 675812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 676812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 677812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb 678812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc 679812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd 680812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 681812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf 682812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 683812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L 684812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L 685812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L 686812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L 687812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L 688812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L 689812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L 690812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L 691812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L 692812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L 693812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L 694812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L 695812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L 696812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L 697812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L 698812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L 699812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L 700812f77b7SFeifei Xu //SDMA0_EDC_COUNTER_CLEAR 701812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 702812f77b7SFeifei Xu #define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L 703812f77b7SFeifei Xu //SDMA0_STATUS2_REG 704812f77b7SFeifei Xu #define SDMA0_STATUS2_REG__ID__SHIFT 0x0 705812f77b7SFeifei Xu #define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 706812f77b7SFeifei Xu #define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 707812f77b7SFeifei Xu #define SDMA0_STATUS2_REG__ID_MASK 0x00000003L 708812f77b7SFeifei Xu #define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL 709812f77b7SFeifei Xu #define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 710812f77b7SFeifei Xu //SDMA0_ATOMIC_CNTL 711812f77b7SFeifei Xu #define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 712812f77b7SFeifei Xu #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 713812f77b7SFeifei Xu #define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 714812f77b7SFeifei Xu #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 715812f77b7SFeifei Xu //SDMA0_ATOMIC_PREOP_LO 716812f77b7SFeifei Xu #define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 717812f77b7SFeifei Xu #define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 718812f77b7SFeifei Xu //SDMA0_ATOMIC_PREOP_HI 719812f77b7SFeifei Xu #define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 720812f77b7SFeifei Xu #define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 721812f77b7SFeifei Xu //SDMA0_UTCL1_CNTL 722812f77b7SFeifei Xu #define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 723812f77b7SFeifei Xu #define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 724812f77b7SFeifei Xu #define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 725812f77b7SFeifei Xu #define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 726812f77b7SFeifei Xu #define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 727812f77b7SFeifei Xu #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 728812f77b7SFeifei Xu #define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 729812f77b7SFeifei Xu #define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 730812f77b7SFeifei Xu #define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 731812f77b7SFeifei Xu #define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 732812f77b7SFeifei Xu #define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 733812f77b7SFeifei Xu #define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 734812f77b7SFeifei Xu //SDMA0_UTCL1_WATERMK 735812f77b7SFeifei Xu #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 736812f77b7SFeifei Xu #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa 737812f77b7SFeifei Xu #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 738812f77b7SFeifei Xu #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a 739812f77b7SFeifei Xu #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL 740812f77b7SFeifei Xu #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L 741812f77b7SFeifei Xu #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L 742812f77b7SFeifei Xu #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L 743812f77b7SFeifei Xu //SDMA0_UTCL1_RD_STATUS 744812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 745812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 746812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 747812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 748812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 749812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 750812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 751812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 752812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 753812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 754812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 755812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 756812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 757812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 758812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 759812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 760812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 761812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 762812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 763812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 764812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 765812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 766812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 767812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 768812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 769812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 770812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 771812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 772812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 773812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 774812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 775812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 776812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 777812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 778812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 779812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 780812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 781812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 782812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 783812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 784812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 785812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 786812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 787812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 788812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 789812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 790812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 791812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 792812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 793812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 794812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 795812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 796812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 797812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 798812f77b7SFeifei Xu //SDMA0_UTCL1_WR_STATUS 799812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 800812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 801812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 802812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 803812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 804812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 805812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 806812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 807812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 808812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 809812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 810812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 811812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 812812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 813812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 814812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 815812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 816812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 817812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 818812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 819812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 820812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 821812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 822812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 823812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 824812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 825812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 826812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 827812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 828812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 829812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 830812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 831812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 832812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 833812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 834812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 835812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 836812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 837812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 838812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 839812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 840812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 841812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 842812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 843812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 844812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 845812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 846812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 847812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 848812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 849812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 850812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 851812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 852812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 853812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 854812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 855812f77b7SFeifei Xu //SDMA0_UTCL1_INV0 856812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 857812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 858812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 859812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 860812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 861812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 862812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 863812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 864812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 865812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 866812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 867812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 868812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 869812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 870812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 871812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 872812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 873812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 874812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 875812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 876812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 877812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 878812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 879812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 880812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 881812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 882812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 883812f77b7SFeifei Xu #define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 884812f77b7SFeifei Xu //SDMA0_UTCL1_INV1 885812f77b7SFeifei Xu #define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 886812f77b7SFeifei Xu #define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 887812f77b7SFeifei Xu //SDMA0_UTCL1_INV2 888812f77b7SFeifei Xu #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 889812f77b7SFeifei Xu #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 890812f77b7SFeifei Xu //SDMA0_UTCL1_RD_XNACK0 891812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 892812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 893812f77b7SFeifei Xu //SDMA0_UTCL1_RD_XNACK1 894812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 895812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 896812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 897812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 898812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 899812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 900812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 901812f77b7SFeifei Xu #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 902812f77b7SFeifei Xu //SDMA0_UTCL1_WR_XNACK0 903812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 904812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 905812f77b7SFeifei Xu //SDMA0_UTCL1_WR_XNACK1 906812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 907812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 908812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 909812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 910812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 911812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 912812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 913812f77b7SFeifei Xu #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 914812f77b7SFeifei Xu //SDMA0_UTCL1_TIMEOUT 915812f77b7SFeifei Xu #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 916812f77b7SFeifei Xu #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 917812f77b7SFeifei Xu #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 918812f77b7SFeifei Xu #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 919812f77b7SFeifei Xu //SDMA0_UTCL1_PAGE 920812f77b7SFeifei Xu #define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 921812f77b7SFeifei Xu #define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 922812f77b7SFeifei Xu #define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 923812f77b7SFeifei Xu #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 924812f77b7SFeifei Xu #define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 925812f77b7SFeifei Xu #define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 926812f77b7SFeifei Xu #define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 927812f77b7SFeifei Xu #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 928812f77b7SFeifei Xu //SDMA0_POWER_CNTL_IDLE 929812f77b7SFeifei Xu #define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 930812f77b7SFeifei Xu #define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 931812f77b7SFeifei Xu #define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 932812f77b7SFeifei Xu #define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 933812f77b7SFeifei Xu #define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 934812f77b7SFeifei Xu #define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 935812f77b7SFeifei Xu //SDMA0_RELAX_ORDERING_LUT 936812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 937812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 938812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 939812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 940812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 941812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 942812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 943812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 944812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 945812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 946812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 947812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 948812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 949812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 950812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 951812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 952812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 953812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 954812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 955812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 956812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 957812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 958812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 959812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 960812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 961812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 962812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 963812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 964812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 965812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 966812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 967812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 968812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 969812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 970812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 971812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 972812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 973812f77b7SFeifei Xu #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 974812f77b7SFeifei Xu //SDMA0_CHICKEN_BITS_2 975812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 976812f77b7SFeifei Xu #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 977812f77b7SFeifei Xu //SDMA0_STATUS3_REG 978812f77b7SFeifei Xu #define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 979812f77b7SFeifei Xu #define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 980812f77b7SFeifei Xu #define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 981812f77b7SFeifei Xu #define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 982812f77b7SFeifei Xu #define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 983812f77b7SFeifei Xu #define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 984812f77b7SFeifei Xu //SDMA0_PHYSICAL_ADDR_LO 985812f77b7SFeifei Xu #define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 986812f77b7SFeifei Xu #define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 987812f77b7SFeifei Xu #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 988812f77b7SFeifei Xu #define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 989812f77b7SFeifei Xu #define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 990812f77b7SFeifei Xu #define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 991812f77b7SFeifei Xu #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 992812f77b7SFeifei Xu #define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 993812f77b7SFeifei Xu //SDMA0_PHYSICAL_ADDR_HI 994812f77b7SFeifei Xu #define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 995812f77b7SFeifei Xu #define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 996812f77b7SFeifei Xu //SDMA0_PHASE2_QUANTUM 997812f77b7SFeifei Xu #define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0 998812f77b7SFeifei Xu #define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8 999812f77b7SFeifei Xu #define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 1000812f77b7SFeifei Xu #define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 1001812f77b7SFeifei Xu #define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 1002812f77b7SFeifei Xu #define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 1003812f77b7SFeifei Xu //SDMA0_ERROR_LOG 1004812f77b7SFeifei Xu #define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 1005812f77b7SFeifei Xu #define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 1006812f77b7SFeifei Xu #define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 1007812f77b7SFeifei Xu #define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L 1008812f77b7SFeifei Xu //SDMA0_PUB_DUMMY_REG0 1009812f77b7SFeifei Xu #define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 1010812f77b7SFeifei Xu #define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 1011812f77b7SFeifei Xu //SDMA0_PUB_DUMMY_REG1 1012812f77b7SFeifei Xu #define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 1013812f77b7SFeifei Xu #define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 1014812f77b7SFeifei Xu //SDMA0_PUB_DUMMY_REG2 1015812f77b7SFeifei Xu #define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 1016812f77b7SFeifei Xu #define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 1017812f77b7SFeifei Xu //SDMA0_PUB_DUMMY_REG3 1018812f77b7SFeifei Xu #define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 1019812f77b7SFeifei Xu #define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 1020812f77b7SFeifei Xu //SDMA0_F32_COUNTER 1021812f77b7SFeifei Xu #define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 1022812f77b7SFeifei Xu #define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 1023812f77b7SFeifei Xu //SDMA0_UNBREAKABLE 1024812f77b7SFeifei Xu #define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0 1025812f77b7SFeifei Xu #define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L 1026812f77b7SFeifei Xu //SDMA0_PERFMON_CNTL 1027812f77b7SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 1028812f77b7SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 1029812f77b7SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 1030812f77b7SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 1031812f77b7SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 1032812f77b7SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 1033812f77b7SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 1034812f77b7SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 1035812f77b7SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 1036812f77b7SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 1037812f77b7SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 1038812f77b7SFeifei Xu #define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 1039812f77b7SFeifei Xu //SDMA0_PERFCOUNTER0_RESULT 1040812f77b7SFeifei Xu #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 1041812f77b7SFeifei Xu #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1042812f77b7SFeifei Xu //SDMA0_PERFCOUNTER1_RESULT 1043812f77b7SFeifei Xu #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1044812f77b7SFeifei Xu #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1045812f77b7SFeifei Xu //SDMA0_PERFCOUNTER_TAG_DELAY_RANGE 1046812f77b7SFeifei Xu #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 1047812f77b7SFeifei Xu #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe 1048812f77b7SFeifei Xu #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c 1049812f77b7SFeifei Xu #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL 1050812f77b7SFeifei Xu #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L 1051812f77b7SFeifei Xu #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L 1052812f77b7SFeifei Xu //SDMA0_CRD_CNTL 1053812f77b7SFeifei Xu #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 1054812f77b7SFeifei Xu #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 1055812f77b7SFeifei Xu #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 1056812f77b7SFeifei Xu #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 1057812f77b7SFeifei Xu //SDMA0_MMHUB_TRUSTLVL 1058812f77b7SFeifei Xu #define SDMA0_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0 1059812f77b7SFeifei Xu #define SDMA0_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3 1060812f77b7SFeifei Xu #define SDMA0_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6 1061812f77b7SFeifei Xu #define SDMA0_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9 1062812f77b7SFeifei Xu #define SDMA0_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc 1063812f77b7SFeifei Xu #define SDMA0_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf 1064812f77b7SFeifei Xu #define SDMA0_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12 1065812f77b7SFeifei Xu #define SDMA0_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15 1066812f77b7SFeifei Xu #define SDMA0_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L 1067812f77b7SFeifei Xu #define SDMA0_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L 1068812f77b7SFeifei Xu #define SDMA0_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L 1069812f77b7SFeifei Xu #define SDMA0_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L 1070812f77b7SFeifei Xu #define SDMA0_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L 1071812f77b7SFeifei Xu #define SDMA0_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L 1072812f77b7SFeifei Xu #define SDMA0_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L 1073812f77b7SFeifei Xu #define SDMA0_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L 1074812f77b7SFeifei Xu //SDMA0_GPU_IOV_VIOLATION_LOG 1075812f77b7SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1076812f77b7SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1077812f77b7SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1078812f77b7SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 1079812f77b7SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 1080812f77b7SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 1081812f77b7SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 1082812f77b7SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1083812f77b7SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1084812f77b7SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 1085812f77b7SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L 1086812f77b7SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 1087812f77b7SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L 1088812f77b7SFeifei Xu #define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 1089812f77b7SFeifei Xu //SDMA0_ULV_CNTL 1090812f77b7SFeifei Xu #define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 1091812f77b7SFeifei Xu #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 1092812f77b7SFeifei Xu #define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 1093812f77b7SFeifei Xu #define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 1094812f77b7SFeifei Xu #define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 1095812f77b7SFeifei Xu #define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 1096812f77b7SFeifei Xu #define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 1097812f77b7SFeifei Xu #define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 1098812f77b7SFeifei Xu //SDMA0_EA_DBIT_ADDR_DATA 1099812f77b7SFeifei Xu #define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 1100812f77b7SFeifei Xu #define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 1101812f77b7SFeifei Xu //SDMA0_EA_DBIT_ADDR_INDEX 1102812f77b7SFeifei Xu #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 1103812f77b7SFeifei Xu #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 1104812f77b7SFeifei Xu //SDMA0_GFX_RB_CNTL 1105812f77b7SFeifei Xu #define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1106812f77b7SFeifei Xu #define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1107812f77b7SFeifei Xu #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1108812f77b7SFeifei Xu #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1109812f77b7SFeifei Xu #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1110812f77b7SFeifei Xu #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1111812f77b7SFeifei Xu #define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1112812f77b7SFeifei Xu #define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1113812f77b7SFeifei Xu #define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1114812f77b7SFeifei Xu #define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1115812f77b7SFeifei Xu #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1116812f77b7SFeifei Xu #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1117812f77b7SFeifei Xu #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1118812f77b7SFeifei Xu #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1119812f77b7SFeifei Xu #define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 1120812f77b7SFeifei Xu #define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 1121812f77b7SFeifei Xu //SDMA0_GFX_RB_BASE 1122812f77b7SFeifei Xu #define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 1123812f77b7SFeifei Xu #define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1124812f77b7SFeifei Xu //SDMA0_GFX_RB_BASE_HI 1125812f77b7SFeifei Xu #define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1126812f77b7SFeifei Xu #define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1127812f77b7SFeifei Xu //SDMA0_GFX_RB_RPTR 1128812f77b7SFeifei Xu #define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 1129812f77b7SFeifei Xu #define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1130812f77b7SFeifei Xu //SDMA0_GFX_RB_RPTR_HI 1131812f77b7SFeifei Xu #define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 1132812f77b7SFeifei Xu #define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1133812f77b7SFeifei Xu //SDMA0_GFX_RB_WPTR 1134812f77b7SFeifei Xu #define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 1135812f77b7SFeifei Xu #define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1136812f77b7SFeifei Xu //SDMA0_GFX_RB_WPTR_HI 1137812f77b7SFeifei Xu #define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 1138812f77b7SFeifei Xu #define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1139812f77b7SFeifei Xu //SDMA0_GFX_RB_WPTR_POLL_CNTL 1140812f77b7SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1141812f77b7SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1142812f77b7SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1143812f77b7SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1144812f77b7SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1145812f77b7SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1146812f77b7SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1147812f77b7SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1148812f77b7SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1149812f77b7SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1150812f77b7SFeifei Xu //SDMA0_GFX_RB_RPTR_ADDR_HI 1151812f77b7SFeifei Xu #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1152812f77b7SFeifei Xu #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1153812f77b7SFeifei Xu //SDMA0_GFX_RB_RPTR_ADDR_LO 1154812f77b7SFeifei Xu #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1155812f77b7SFeifei Xu #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1156812f77b7SFeifei Xu //SDMA0_GFX_IB_CNTL 1157812f77b7SFeifei Xu #define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1158812f77b7SFeifei Xu #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1159812f77b7SFeifei Xu #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1160812f77b7SFeifei Xu #define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1161812f77b7SFeifei Xu #define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1162812f77b7SFeifei Xu #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1163812f77b7SFeifei Xu #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1164812f77b7SFeifei Xu #define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1165812f77b7SFeifei Xu //SDMA0_GFX_IB_RPTR 1166812f77b7SFeifei Xu #define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1167812f77b7SFeifei Xu #define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1168812f77b7SFeifei Xu //SDMA0_GFX_IB_OFFSET 1169812f77b7SFeifei Xu #define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1170812f77b7SFeifei Xu #define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1171812f77b7SFeifei Xu //SDMA0_GFX_IB_BASE_LO 1172812f77b7SFeifei Xu #define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1173812f77b7SFeifei Xu #define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1174812f77b7SFeifei Xu //SDMA0_GFX_IB_BASE_HI 1175812f77b7SFeifei Xu #define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1176812f77b7SFeifei Xu #define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1177812f77b7SFeifei Xu //SDMA0_GFX_IB_SIZE 1178812f77b7SFeifei Xu #define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 1179812f77b7SFeifei Xu #define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 1180812f77b7SFeifei Xu //SDMA0_GFX_SKIP_CNTL 1181812f77b7SFeifei Xu #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1182812f77b7SFeifei Xu #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1183812f77b7SFeifei Xu //SDMA0_GFX_CONTEXT_STATUS 1184812f77b7SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1185812f77b7SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1186812f77b7SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1187812f77b7SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1188812f77b7SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1189812f77b7SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1190812f77b7SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1191812f77b7SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1192812f77b7SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1193812f77b7SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1194812f77b7SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1195812f77b7SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1196812f77b7SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1197812f77b7SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1198812f77b7SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1199812f77b7SFeifei Xu #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1200812f77b7SFeifei Xu //SDMA0_GFX_DOORBELL 1201812f77b7SFeifei Xu #define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1202812f77b7SFeifei Xu #define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1203812f77b7SFeifei Xu #define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L 1204812f77b7SFeifei Xu #define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 1205812f77b7SFeifei Xu //SDMA0_GFX_CONTEXT_CNTL 1206812f77b7SFeifei Xu #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1207812f77b7SFeifei Xu #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 1208812f77b7SFeifei Xu //SDMA0_GFX_STATUS 1209812f77b7SFeifei Xu #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1210812f77b7SFeifei Xu #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1211812f77b7SFeifei Xu #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1212812f77b7SFeifei Xu #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1213812f77b7SFeifei Xu //SDMA0_GFX_DOORBELL_LOG 1214812f77b7SFeifei Xu #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1215812f77b7SFeifei Xu #define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1216812f77b7SFeifei Xu #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1217812f77b7SFeifei Xu #define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1218812f77b7SFeifei Xu //SDMA0_GFX_WATERMARK 1219812f77b7SFeifei Xu #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1220812f77b7SFeifei Xu #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1221812f77b7SFeifei Xu #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1222812f77b7SFeifei Xu #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1223812f77b7SFeifei Xu //SDMA0_GFX_DOORBELL_OFFSET 1224812f77b7SFeifei Xu #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1225812f77b7SFeifei Xu #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1226812f77b7SFeifei Xu //SDMA0_GFX_CSA_ADDR_LO 1227812f77b7SFeifei Xu #define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1228812f77b7SFeifei Xu #define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1229812f77b7SFeifei Xu //SDMA0_GFX_CSA_ADDR_HI 1230812f77b7SFeifei Xu #define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1231812f77b7SFeifei Xu #define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1232812f77b7SFeifei Xu //SDMA0_GFX_IB_SUB_REMAIN 1233812f77b7SFeifei Xu #define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1234812f77b7SFeifei Xu #define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1235812f77b7SFeifei Xu //SDMA0_GFX_PREEMPT 1236812f77b7SFeifei Xu #define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1237812f77b7SFeifei Xu #define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1238812f77b7SFeifei Xu //SDMA0_GFX_DUMMY_REG 1239812f77b7SFeifei Xu #define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1240812f77b7SFeifei Xu #define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1241812f77b7SFeifei Xu //SDMA0_GFX_RB_WPTR_POLL_ADDR_HI 1242812f77b7SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1243812f77b7SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1244812f77b7SFeifei Xu //SDMA0_GFX_RB_WPTR_POLL_ADDR_LO 1245812f77b7SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1246812f77b7SFeifei Xu #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1247812f77b7SFeifei Xu //SDMA0_GFX_RB_AQL_CNTL 1248812f77b7SFeifei Xu #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1249812f77b7SFeifei Xu #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1250812f77b7SFeifei Xu #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1251812f77b7SFeifei Xu #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1252812f77b7SFeifei Xu #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1253812f77b7SFeifei Xu #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1254812f77b7SFeifei Xu //SDMA0_GFX_MINOR_PTR_UPDATE 1255812f77b7SFeifei Xu #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1256812f77b7SFeifei Xu #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1257812f77b7SFeifei Xu //SDMA0_GFX_MIDCMD_DATA0 1258812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1259812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1260812f77b7SFeifei Xu //SDMA0_GFX_MIDCMD_DATA1 1261812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1262812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1263812f77b7SFeifei Xu //SDMA0_GFX_MIDCMD_DATA2 1264812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1265812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1266812f77b7SFeifei Xu //SDMA0_GFX_MIDCMD_DATA3 1267812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1268812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1269812f77b7SFeifei Xu //SDMA0_GFX_MIDCMD_DATA4 1270812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1271812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1272812f77b7SFeifei Xu //SDMA0_GFX_MIDCMD_DATA5 1273812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1274812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1275812f77b7SFeifei Xu //SDMA0_GFX_MIDCMD_DATA6 1276812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1277812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1278812f77b7SFeifei Xu //SDMA0_GFX_MIDCMD_DATA7 1279812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1280812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1281812f77b7SFeifei Xu //SDMA0_GFX_MIDCMD_DATA8 1282812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1283812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1284812f77b7SFeifei Xu //SDMA0_GFX_MIDCMD_CNTL 1285812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1286812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1287812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1288812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1289812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1290812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1291812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1292812f77b7SFeifei Xu #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1293812f77b7SFeifei Xu //SDMA0_PAGE_RB_CNTL 1294812f77b7SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 1295812f77b7SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 1296812f77b7SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1297812f77b7SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1298812f77b7SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1299812f77b7SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1300812f77b7SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 1301812f77b7SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 1302812f77b7SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1303812f77b7SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1304812f77b7SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1305812f77b7SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1306812f77b7SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1307812f77b7SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1308812f77b7SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 1309812f77b7SFeifei Xu #define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 1310812f77b7SFeifei Xu //SDMA0_PAGE_RB_BASE 1311812f77b7SFeifei Xu #define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0 1312812f77b7SFeifei Xu #define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1313812f77b7SFeifei Xu //SDMA0_PAGE_RB_BASE_HI 1314812f77b7SFeifei Xu #define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 1315812f77b7SFeifei Xu #define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1316812f77b7SFeifei Xu //SDMA0_PAGE_RB_RPTR 1317812f77b7SFeifei Xu #define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 1318812f77b7SFeifei Xu #define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1319812f77b7SFeifei Xu //SDMA0_PAGE_RB_RPTR_HI 1320812f77b7SFeifei Xu #define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 1321812f77b7SFeifei Xu #define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1322812f77b7SFeifei Xu //SDMA0_PAGE_RB_WPTR 1323812f77b7SFeifei Xu #define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 1324812f77b7SFeifei Xu #define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1325812f77b7SFeifei Xu //SDMA0_PAGE_RB_WPTR_HI 1326812f77b7SFeifei Xu #define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 1327812f77b7SFeifei Xu #define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1328812f77b7SFeifei Xu //SDMA0_PAGE_RB_WPTR_POLL_CNTL 1329812f77b7SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1330812f77b7SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1331812f77b7SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1332812f77b7SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1333812f77b7SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1334812f77b7SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1335812f77b7SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1336812f77b7SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1337812f77b7SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1338812f77b7SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1339812f77b7SFeifei Xu //SDMA0_PAGE_RB_RPTR_ADDR_HI 1340812f77b7SFeifei Xu #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1341812f77b7SFeifei Xu #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1342812f77b7SFeifei Xu //SDMA0_PAGE_RB_RPTR_ADDR_LO 1343812f77b7SFeifei Xu #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1344812f77b7SFeifei Xu #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1345812f77b7SFeifei Xu //SDMA0_PAGE_IB_CNTL 1346812f77b7SFeifei Xu #define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 1347812f77b7SFeifei Xu #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1348812f77b7SFeifei Xu #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1349812f77b7SFeifei Xu #define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 1350812f77b7SFeifei Xu #define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1351812f77b7SFeifei Xu #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1352812f77b7SFeifei Xu #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1353812f77b7SFeifei Xu #define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1354812f77b7SFeifei Xu //SDMA0_PAGE_IB_RPTR 1355812f77b7SFeifei Xu #define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 1356812f77b7SFeifei Xu #define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1357812f77b7SFeifei Xu //SDMA0_PAGE_IB_OFFSET 1358812f77b7SFeifei Xu #define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 1359812f77b7SFeifei Xu #define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1360812f77b7SFeifei Xu //SDMA0_PAGE_IB_BASE_LO 1361812f77b7SFeifei Xu #define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 1362812f77b7SFeifei Xu #define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1363812f77b7SFeifei Xu //SDMA0_PAGE_IB_BASE_HI 1364812f77b7SFeifei Xu #define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 1365812f77b7SFeifei Xu #define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1366812f77b7SFeifei Xu //SDMA0_PAGE_IB_SIZE 1367812f77b7SFeifei Xu #define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0 1368812f77b7SFeifei Xu #define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 1369812f77b7SFeifei Xu //SDMA0_PAGE_SKIP_CNTL 1370812f77b7SFeifei Xu #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1371812f77b7SFeifei Xu #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1372812f77b7SFeifei Xu //SDMA0_PAGE_CONTEXT_STATUS 1373812f77b7SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1374812f77b7SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 1375812f77b7SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1376812f77b7SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1377812f77b7SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1378812f77b7SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1379812f77b7SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1380812f77b7SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1381812f77b7SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1382812f77b7SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1383812f77b7SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1384812f77b7SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1385812f77b7SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1386812f77b7SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1387812f77b7SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1388812f77b7SFeifei Xu #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1389812f77b7SFeifei Xu //SDMA0_PAGE_DOORBELL 1390812f77b7SFeifei Xu #define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 1391812f77b7SFeifei Xu #define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 1392812f77b7SFeifei Xu #define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 1393812f77b7SFeifei Xu #define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 1394812f77b7SFeifei Xu //SDMA0_PAGE_STATUS 1395812f77b7SFeifei Xu #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1396812f77b7SFeifei Xu #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1397812f77b7SFeifei Xu #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1398812f77b7SFeifei Xu #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1399812f77b7SFeifei Xu //SDMA0_PAGE_DOORBELL_LOG 1400812f77b7SFeifei Xu #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1401812f77b7SFeifei Xu #define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 1402812f77b7SFeifei Xu #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1403812f77b7SFeifei Xu #define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1404812f77b7SFeifei Xu //SDMA0_PAGE_WATERMARK 1405812f77b7SFeifei Xu #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1406812f77b7SFeifei Xu #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1407812f77b7SFeifei Xu #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1408812f77b7SFeifei Xu #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1409812f77b7SFeifei Xu //SDMA0_PAGE_DOORBELL_OFFSET 1410812f77b7SFeifei Xu #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1411812f77b7SFeifei Xu #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1412812f77b7SFeifei Xu //SDMA0_PAGE_CSA_ADDR_LO 1413812f77b7SFeifei Xu #define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 1414812f77b7SFeifei Xu #define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1415812f77b7SFeifei Xu //SDMA0_PAGE_CSA_ADDR_HI 1416812f77b7SFeifei Xu #define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 1417812f77b7SFeifei Xu #define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1418812f77b7SFeifei Xu //SDMA0_PAGE_IB_SUB_REMAIN 1419812f77b7SFeifei Xu #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1420812f77b7SFeifei Xu #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1421812f77b7SFeifei Xu //SDMA0_PAGE_PREEMPT 1422812f77b7SFeifei Xu #define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 1423812f77b7SFeifei Xu #define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1424812f77b7SFeifei Xu //SDMA0_PAGE_DUMMY_REG 1425812f77b7SFeifei Xu #define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 1426812f77b7SFeifei Xu #define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1427812f77b7SFeifei Xu //SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 1428812f77b7SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1429812f77b7SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1430812f77b7SFeifei Xu //SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 1431812f77b7SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1432812f77b7SFeifei Xu #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1433812f77b7SFeifei Xu //SDMA0_PAGE_RB_AQL_CNTL 1434812f77b7SFeifei Xu #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1435812f77b7SFeifei Xu #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1436812f77b7SFeifei Xu #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1437812f77b7SFeifei Xu #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1438812f77b7SFeifei Xu #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1439812f77b7SFeifei Xu #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1440812f77b7SFeifei Xu //SDMA0_PAGE_MINOR_PTR_UPDATE 1441812f77b7SFeifei Xu #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1442812f77b7SFeifei Xu #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1443812f77b7SFeifei Xu //SDMA0_PAGE_MIDCMD_DATA0 1444812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 1445812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1446812f77b7SFeifei Xu //SDMA0_PAGE_MIDCMD_DATA1 1447812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 1448812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1449812f77b7SFeifei Xu //SDMA0_PAGE_MIDCMD_DATA2 1450812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 1451812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1452812f77b7SFeifei Xu //SDMA0_PAGE_MIDCMD_DATA3 1453812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 1454812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1455812f77b7SFeifei Xu //SDMA0_PAGE_MIDCMD_DATA4 1456812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 1457812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1458812f77b7SFeifei Xu //SDMA0_PAGE_MIDCMD_DATA5 1459812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 1460812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1461812f77b7SFeifei Xu //SDMA0_PAGE_MIDCMD_DATA6 1462812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 1463812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1464812f77b7SFeifei Xu //SDMA0_PAGE_MIDCMD_DATA7 1465812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 1466812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1467812f77b7SFeifei Xu //SDMA0_PAGE_MIDCMD_DATA8 1468812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 1469812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1470812f77b7SFeifei Xu //SDMA0_PAGE_MIDCMD_CNTL 1471812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1472812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1473812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1474812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1475812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1476812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1477812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1478812f77b7SFeifei Xu #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1479812f77b7SFeifei Xu //SDMA0_RLC0_RB_CNTL 1480812f77b7SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1481812f77b7SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1482812f77b7SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1483812f77b7SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1484812f77b7SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1485812f77b7SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1486812f77b7SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1487812f77b7SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1488812f77b7SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1489812f77b7SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1490812f77b7SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1491812f77b7SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1492812f77b7SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1493812f77b7SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1494812f77b7SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 1495812f77b7SFeifei Xu #define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1496812f77b7SFeifei Xu //SDMA0_RLC0_RB_BASE 1497812f77b7SFeifei Xu #define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 1498812f77b7SFeifei Xu #define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1499812f77b7SFeifei Xu //SDMA0_RLC0_RB_BASE_HI 1500812f77b7SFeifei Xu #define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1501812f77b7SFeifei Xu #define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1502812f77b7SFeifei Xu //SDMA0_RLC0_RB_RPTR 1503812f77b7SFeifei Xu #define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 1504812f77b7SFeifei Xu #define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1505812f77b7SFeifei Xu //SDMA0_RLC0_RB_RPTR_HI 1506812f77b7SFeifei Xu #define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1507812f77b7SFeifei Xu #define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1508812f77b7SFeifei Xu //SDMA0_RLC0_RB_WPTR 1509812f77b7SFeifei Xu #define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 1510812f77b7SFeifei Xu #define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1511812f77b7SFeifei Xu //SDMA0_RLC0_RB_WPTR_HI 1512812f77b7SFeifei Xu #define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1513812f77b7SFeifei Xu #define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1514812f77b7SFeifei Xu //SDMA0_RLC0_RB_WPTR_POLL_CNTL 1515812f77b7SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1516812f77b7SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1517812f77b7SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1518812f77b7SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1519812f77b7SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1520812f77b7SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1521812f77b7SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1522812f77b7SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1523812f77b7SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1524812f77b7SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1525812f77b7SFeifei Xu //SDMA0_RLC0_RB_RPTR_ADDR_HI 1526812f77b7SFeifei Xu #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1527812f77b7SFeifei Xu #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1528812f77b7SFeifei Xu //SDMA0_RLC0_RB_RPTR_ADDR_LO 1529812f77b7SFeifei Xu #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1530812f77b7SFeifei Xu #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1531812f77b7SFeifei Xu //SDMA0_RLC0_IB_CNTL 1532812f77b7SFeifei Xu #define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1533812f77b7SFeifei Xu #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1534812f77b7SFeifei Xu #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1535812f77b7SFeifei Xu #define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1536812f77b7SFeifei Xu #define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1537812f77b7SFeifei Xu #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1538812f77b7SFeifei Xu #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1539812f77b7SFeifei Xu #define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1540812f77b7SFeifei Xu //SDMA0_RLC0_IB_RPTR 1541812f77b7SFeifei Xu #define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1542812f77b7SFeifei Xu #define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1543812f77b7SFeifei Xu //SDMA0_RLC0_IB_OFFSET 1544812f77b7SFeifei Xu #define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1545812f77b7SFeifei Xu #define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1546812f77b7SFeifei Xu //SDMA0_RLC0_IB_BASE_LO 1547812f77b7SFeifei Xu #define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1548812f77b7SFeifei Xu #define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1549812f77b7SFeifei Xu //SDMA0_RLC0_IB_BASE_HI 1550812f77b7SFeifei Xu #define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1551812f77b7SFeifei Xu #define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1552812f77b7SFeifei Xu //SDMA0_RLC0_IB_SIZE 1553812f77b7SFeifei Xu #define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1554812f77b7SFeifei Xu #define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1555812f77b7SFeifei Xu //SDMA0_RLC0_SKIP_CNTL 1556812f77b7SFeifei Xu #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1557812f77b7SFeifei Xu #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1558812f77b7SFeifei Xu //SDMA0_RLC0_CONTEXT_STATUS 1559812f77b7SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1560812f77b7SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1561812f77b7SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1562812f77b7SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1563812f77b7SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1564812f77b7SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1565812f77b7SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1566812f77b7SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1567812f77b7SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1568812f77b7SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1569812f77b7SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1570812f77b7SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1571812f77b7SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1572812f77b7SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1573812f77b7SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1574812f77b7SFeifei Xu #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1575812f77b7SFeifei Xu //SDMA0_RLC0_DOORBELL 1576812f77b7SFeifei Xu #define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1577812f77b7SFeifei Xu #define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1578812f77b7SFeifei Xu #define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 1579812f77b7SFeifei Xu #define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 1580812f77b7SFeifei Xu //SDMA0_RLC0_STATUS 1581812f77b7SFeifei Xu #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1582812f77b7SFeifei Xu #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1583812f77b7SFeifei Xu #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1584812f77b7SFeifei Xu #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1585812f77b7SFeifei Xu //SDMA0_RLC0_DOORBELL_LOG 1586812f77b7SFeifei Xu #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1587812f77b7SFeifei Xu #define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1588812f77b7SFeifei Xu #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1589812f77b7SFeifei Xu #define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1590812f77b7SFeifei Xu //SDMA0_RLC0_WATERMARK 1591812f77b7SFeifei Xu #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1592812f77b7SFeifei Xu #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1593812f77b7SFeifei Xu #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1594812f77b7SFeifei Xu #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1595812f77b7SFeifei Xu //SDMA0_RLC0_DOORBELL_OFFSET 1596812f77b7SFeifei Xu #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1597812f77b7SFeifei Xu #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1598812f77b7SFeifei Xu //SDMA0_RLC0_CSA_ADDR_LO 1599812f77b7SFeifei Xu #define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1600812f77b7SFeifei Xu #define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1601812f77b7SFeifei Xu //SDMA0_RLC0_CSA_ADDR_HI 1602812f77b7SFeifei Xu #define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1603812f77b7SFeifei Xu #define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1604812f77b7SFeifei Xu //SDMA0_RLC0_IB_SUB_REMAIN 1605812f77b7SFeifei Xu #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1606812f77b7SFeifei Xu #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1607812f77b7SFeifei Xu //SDMA0_RLC0_PREEMPT 1608812f77b7SFeifei Xu #define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1609812f77b7SFeifei Xu #define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1610812f77b7SFeifei Xu //SDMA0_RLC0_DUMMY_REG 1611812f77b7SFeifei Xu #define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1612812f77b7SFeifei Xu #define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1613812f77b7SFeifei Xu //SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 1614812f77b7SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1615812f77b7SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1616812f77b7SFeifei Xu //SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 1617812f77b7SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1618812f77b7SFeifei Xu #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1619812f77b7SFeifei Xu //SDMA0_RLC0_RB_AQL_CNTL 1620812f77b7SFeifei Xu #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1621812f77b7SFeifei Xu #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1622812f77b7SFeifei Xu #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1623812f77b7SFeifei Xu #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1624812f77b7SFeifei Xu #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1625812f77b7SFeifei Xu #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1626812f77b7SFeifei Xu //SDMA0_RLC0_MINOR_PTR_UPDATE 1627812f77b7SFeifei Xu #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1628812f77b7SFeifei Xu #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1629812f77b7SFeifei Xu //SDMA0_RLC0_MIDCMD_DATA0 1630812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1631812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1632812f77b7SFeifei Xu //SDMA0_RLC0_MIDCMD_DATA1 1633812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1634812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1635812f77b7SFeifei Xu //SDMA0_RLC0_MIDCMD_DATA2 1636812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1637812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1638812f77b7SFeifei Xu //SDMA0_RLC0_MIDCMD_DATA3 1639812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1640812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1641812f77b7SFeifei Xu //SDMA0_RLC0_MIDCMD_DATA4 1642812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1643812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1644812f77b7SFeifei Xu //SDMA0_RLC0_MIDCMD_DATA5 1645812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1646812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1647812f77b7SFeifei Xu //SDMA0_RLC0_MIDCMD_DATA6 1648812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1649812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1650812f77b7SFeifei Xu //SDMA0_RLC0_MIDCMD_DATA7 1651812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1652812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1653812f77b7SFeifei Xu //SDMA0_RLC0_MIDCMD_DATA8 1654812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1655812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1656812f77b7SFeifei Xu //SDMA0_RLC0_MIDCMD_CNTL 1657812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1658812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1659812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1660812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1661812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1662812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1663812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1664812f77b7SFeifei Xu #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1665812f77b7SFeifei Xu //SDMA0_RLC1_RB_CNTL 1666812f77b7SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1667812f77b7SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1668812f77b7SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1669812f77b7SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1670812f77b7SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1671812f77b7SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1672812f77b7SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1673812f77b7SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1674812f77b7SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1675812f77b7SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1676812f77b7SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1677812f77b7SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1678812f77b7SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1679812f77b7SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1680812f77b7SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 1681812f77b7SFeifei Xu #define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1682812f77b7SFeifei Xu //SDMA0_RLC1_RB_BASE 1683812f77b7SFeifei Xu #define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 1684812f77b7SFeifei Xu #define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1685812f77b7SFeifei Xu //SDMA0_RLC1_RB_BASE_HI 1686812f77b7SFeifei Xu #define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1687812f77b7SFeifei Xu #define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1688812f77b7SFeifei Xu //SDMA0_RLC1_RB_RPTR 1689812f77b7SFeifei Xu #define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 1690812f77b7SFeifei Xu #define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1691812f77b7SFeifei Xu //SDMA0_RLC1_RB_RPTR_HI 1692812f77b7SFeifei Xu #define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1693812f77b7SFeifei Xu #define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1694812f77b7SFeifei Xu //SDMA0_RLC1_RB_WPTR 1695812f77b7SFeifei Xu #define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 1696812f77b7SFeifei Xu #define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1697812f77b7SFeifei Xu //SDMA0_RLC1_RB_WPTR_HI 1698812f77b7SFeifei Xu #define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1699812f77b7SFeifei Xu #define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1700812f77b7SFeifei Xu //SDMA0_RLC1_RB_WPTR_POLL_CNTL 1701812f77b7SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1702812f77b7SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1703812f77b7SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1704812f77b7SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1705812f77b7SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1706812f77b7SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1707812f77b7SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1708812f77b7SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1709812f77b7SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1710812f77b7SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1711812f77b7SFeifei Xu //SDMA0_RLC1_RB_RPTR_ADDR_HI 1712812f77b7SFeifei Xu #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1713812f77b7SFeifei Xu #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1714812f77b7SFeifei Xu //SDMA0_RLC1_RB_RPTR_ADDR_LO 1715812f77b7SFeifei Xu #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1716812f77b7SFeifei Xu #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1717812f77b7SFeifei Xu //SDMA0_RLC1_IB_CNTL 1718812f77b7SFeifei Xu #define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1719812f77b7SFeifei Xu #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1720812f77b7SFeifei Xu #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1721812f77b7SFeifei Xu #define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1722812f77b7SFeifei Xu #define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1723812f77b7SFeifei Xu #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1724812f77b7SFeifei Xu #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1725812f77b7SFeifei Xu #define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1726812f77b7SFeifei Xu //SDMA0_RLC1_IB_RPTR 1727812f77b7SFeifei Xu #define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1728812f77b7SFeifei Xu #define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1729812f77b7SFeifei Xu //SDMA0_RLC1_IB_OFFSET 1730812f77b7SFeifei Xu #define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1731812f77b7SFeifei Xu #define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1732812f77b7SFeifei Xu //SDMA0_RLC1_IB_BASE_LO 1733812f77b7SFeifei Xu #define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1734812f77b7SFeifei Xu #define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1735812f77b7SFeifei Xu //SDMA0_RLC1_IB_BASE_HI 1736812f77b7SFeifei Xu #define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1737812f77b7SFeifei Xu #define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1738812f77b7SFeifei Xu //SDMA0_RLC1_IB_SIZE 1739812f77b7SFeifei Xu #define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1740812f77b7SFeifei Xu #define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1741812f77b7SFeifei Xu //SDMA0_RLC1_SKIP_CNTL 1742812f77b7SFeifei Xu #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1743812f77b7SFeifei Xu #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1744812f77b7SFeifei Xu //SDMA0_RLC1_CONTEXT_STATUS 1745812f77b7SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1746812f77b7SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1747812f77b7SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1748812f77b7SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1749812f77b7SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1750812f77b7SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1751812f77b7SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1752812f77b7SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1753812f77b7SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1754812f77b7SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1755812f77b7SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1756812f77b7SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1757812f77b7SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1758812f77b7SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1759812f77b7SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1760812f77b7SFeifei Xu #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1761812f77b7SFeifei Xu //SDMA0_RLC1_DOORBELL 1762812f77b7SFeifei Xu #define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 1763812f77b7SFeifei Xu #define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 1764812f77b7SFeifei Xu #define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 1765812f77b7SFeifei Xu #define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 1766812f77b7SFeifei Xu //SDMA0_RLC1_STATUS 1767812f77b7SFeifei Xu #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1768812f77b7SFeifei Xu #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1769812f77b7SFeifei Xu #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1770812f77b7SFeifei Xu #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1771812f77b7SFeifei Xu //SDMA0_RLC1_DOORBELL_LOG 1772812f77b7SFeifei Xu #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1773812f77b7SFeifei Xu #define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 1774812f77b7SFeifei Xu #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1775812f77b7SFeifei Xu #define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1776812f77b7SFeifei Xu //SDMA0_RLC1_WATERMARK 1777812f77b7SFeifei Xu #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1778812f77b7SFeifei Xu #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1779812f77b7SFeifei Xu #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1780812f77b7SFeifei Xu #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1781812f77b7SFeifei Xu //SDMA0_RLC1_DOORBELL_OFFSET 1782812f77b7SFeifei Xu #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1783812f77b7SFeifei Xu #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1784812f77b7SFeifei Xu //SDMA0_RLC1_CSA_ADDR_LO 1785812f77b7SFeifei Xu #define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1786812f77b7SFeifei Xu #define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1787812f77b7SFeifei Xu //SDMA0_RLC1_CSA_ADDR_HI 1788812f77b7SFeifei Xu #define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1789812f77b7SFeifei Xu #define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1790812f77b7SFeifei Xu //SDMA0_RLC1_IB_SUB_REMAIN 1791812f77b7SFeifei Xu #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1792812f77b7SFeifei Xu #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1793812f77b7SFeifei Xu //SDMA0_RLC1_PREEMPT 1794812f77b7SFeifei Xu #define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1795812f77b7SFeifei Xu #define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1796812f77b7SFeifei Xu //SDMA0_RLC1_DUMMY_REG 1797812f77b7SFeifei Xu #define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 1798812f77b7SFeifei Xu #define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1799812f77b7SFeifei Xu //SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 1800812f77b7SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1801812f77b7SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1802812f77b7SFeifei Xu //SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 1803812f77b7SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1804812f77b7SFeifei Xu #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1805812f77b7SFeifei Xu //SDMA0_RLC1_RB_AQL_CNTL 1806812f77b7SFeifei Xu #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1807812f77b7SFeifei Xu #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1808812f77b7SFeifei Xu #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1809812f77b7SFeifei Xu #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1810812f77b7SFeifei Xu #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1811812f77b7SFeifei Xu #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1812812f77b7SFeifei Xu //SDMA0_RLC1_MINOR_PTR_UPDATE 1813812f77b7SFeifei Xu #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1814812f77b7SFeifei Xu #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1815812f77b7SFeifei Xu //SDMA0_RLC1_MIDCMD_DATA0 1816812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1817812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1818812f77b7SFeifei Xu //SDMA0_RLC1_MIDCMD_DATA1 1819812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1820812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1821812f77b7SFeifei Xu //SDMA0_RLC1_MIDCMD_DATA2 1822812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1823812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1824812f77b7SFeifei Xu //SDMA0_RLC1_MIDCMD_DATA3 1825812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1826812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1827812f77b7SFeifei Xu //SDMA0_RLC1_MIDCMD_DATA4 1828812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1829812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1830812f77b7SFeifei Xu //SDMA0_RLC1_MIDCMD_DATA5 1831812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1832812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1833812f77b7SFeifei Xu //SDMA0_RLC1_MIDCMD_DATA6 1834812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1835812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1836812f77b7SFeifei Xu //SDMA0_RLC1_MIDCMD_DATA7 1837812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1838812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1839812f77b7SFeifei Xu //SDMA0_RLC1_MIDCMD_DATA8 1840812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1841812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1842812f77b7SFeifei Xu //SDMA0_RLC1_MIDCMD_CNTL 1843812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1844812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1845812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1846812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1847812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1848812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1849812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1850812f77b7SFeifei Xu #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1851812f77b7SFeifei Xu 1852812f77b7SFeifei Xu #endif 1853