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Searched refs:SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_sh_mask.h1321 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT … macro
H A Dsdma0_4_0_sh_mask.h1515 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 macro
H A Dsdma0_4_2_sh_mask.h1523 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT … macro
H A Dsdma0_4_2_2_sh_mask.h1533 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_sh_mask.h1302 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 macro
H A Doss_2_0_sh_mask.h1182 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 macro
H A Doss_3_0_1_sh_mask.h1750 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 macro
H A Doss_3_0_sh_mask.h2066 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_sh_mask.h1317 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_sh_mask.h1307 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h1336 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT … macro