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Searched refs:SDMA0_PHASE0_QUANTUM__VALUE_MASK (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dcik_sdma.c350 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> in cik_ctx_switch_enable()
357 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> in cik_ctx_switch_enable()
H A Dsdma_v3_0.c557 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> in sdma_v3_0_ctx_switch_enable()
564 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> in sdma_v3_0_ctx_switch_enable()
H A Dsdma_v5_2.c420 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> in sdma_v5_2_ctx_switch_enable()
427 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> in sdma_v5_2_ctx_switch_enable()
H A Dsdma_v5_0.c603 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> in sdma_v5_0_ctx_switch_enable()
610 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> in sdma_v5_0_ctx_switch_enable()
H A Dsdma_v4_0.c945 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> in sdma_v4_0_ctx_switch_enable()
952 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> in sdma_v4_0_ctx_switch_enable()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_sh_mask.h599 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK … macro
H A Dsdma0_4_0_sh_mask.h600 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L macro
H A Dsdma0_4_2_sh_mask.h602 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK … macro
H A Dsdma0_4_2_2_sh_mask.h608 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_sh_mask.h1103 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00 macro
H A Doss_2_0_sh_mask.h1013 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00 macro
H A Doss_3_0_1_sh_mask.h1123 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00 macro
H A Doss_3_0_sh_mask.h1629 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_sh_mask.h295 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_sh_mask.h314 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK … macro
H A Dgc_10_3_0_sh_mask.h315 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK … macro