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Searched refs:SDMA0_F32_CNTL__HALT__SHIFT (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_sh_mask.h581 #define SDMA0_F32_CNTL__HALT__SHIFT … macro
H A Dsdma0_4_0_sh_mask.h582 #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 macro
H A Dsdma0_4_2_2_sh_mask.h590 #define SDMA0_F32_CNTL__HALT__SHIFT … macro
H A Dsdma0_4_2_sh_mask.h584 #define SDMA0_F32_CNTL__HALT__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_0_sh_mask.h1004 #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 macro
H A Doss_2_4_sh_mask.h1090 #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 macro
H A Doss_3_0_1_sh_mask.h1110 #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 macro
H A Doss_3_0_sh_mask.h1616 #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_sh_mask.h275 #define SDMA0_F32_CNTL__HALT__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_sh_mask.h5103 #define SDMA0_F32_CNTL__HALT__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h290 #define SDMA0_F32_CNTL__HALT__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h5591 #define SDMA0_F32_CNTL__HALT__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h291 #define SDMA0_F32_CNTL__HALT__SHIFT … macro