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Searched refs:Rd (Results 1 – 24 of 24) sorted by relevance

/openbmc/linux/arch/arm64/net/
H A Dbpf_jit.h170 #define A64_MOV(sf, Rd, Rn) A64_ADD_I(sf, Rd, Rn, 0) argument
192 #define A64_UXTH(sf, Rd, Rn) A64_UBFM(sf, Rd, Rn, 0, 15) argument
193 #define A64_UXTW(sf, Rd, Rn) A64_UBFM(sf, Rd, Rn, 0, 31) argument
196 #define A64_SXTB(sf, Rd, Rn) A64_SBFM(sf, Rd, Rn, 0, 7) argument
197 #define A64_SXTH(sf, Rd, Rn) A64_SBFM(sf, Rd, Rn, 0, 15) argument
198 #define A64_SXTW(sf, Rd, Rn) A64_SBFM(sf, Rd, Rn, 0, 31) argument
220 #define A64_NEG(sf, Rd, Rm) A64_SUB(sf, Rd, A64_ZR, Rm) argument
228 #define A64_REV16(sf, Rd, Rn) A64_DATA1(sf, Rd, Rn, REVERSE_16) argument
229 #define A64_REV32(sf, Rd, Rn) A64_DATA1(sf, Rd, Rn, REVERSE_32) argument
230 #define A64_REV64(Rd, Rn) A64_DATA1(1, Rd, Rn, REVERSE_64) argument
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/openbmc/qemu/target/avr/
H A Dtranslate.c609 tcg_gen_xor_tl(Rd, Rd, Rr); in trans_EOR()
627 tcg_gen_xori_tl(Rd, Rd, 0xff); in trans_COM()
671 tcg_gen_addi_tl(Rd, Rd, 1); in trans_INC()
672 tcg_gen_andi_tl(Rd, Rd, 0xff); in trans_INC()
693 tcg_gen_subi_tl(Rd, Rd, 1); /* Rd = Rd - 1 */ in trans_DEC()
2326 tcg_gen_shri_tl(Rd, Rd, 1); in trans_LSR()
2355 tcg_gen_shri_tl(Rd, Rd, 1); in trans_ROR()
2356 tcg_gen_or_tl(Rd, Rd, t0); in trans_ROR()
2379 tcg_gen_shri_tl(Rd, Rd, 1); in trans_ASR()
2380 tcg_gen_or_tl(Rd, Rd, t0); in trans_ASR()
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/openbmc/linux/Documentation/i2c/
H A Di2c-protocol.rst14 Rd/Wr (1 bit) Read/Write bit. Rd equals 1, Wr equals 0.
38 S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P
50 S Addr Rd [A] [Data] NA S Addr Wr [A] Data [A] P
70 In a combined transaction, no 'S Addr Wr/Rd [A]' is generated at some
74 S Addr Rd [A] [Data] NA Data [A] P
87 This toggles the Rd/Wr flag. That is, if you want to do a write, but
88 need to emit an Rd instead of a Wr, or vice versa, you set this
91 S Addr Rd [A] Data [A] Data [A] ... [A] Data [A] P
H A Dsmbus-protocol.rst42 Rd/Wr (1 bit) Read/Write bit. Rd equals 1, Wr equals 0.
60 This sends a single bit to the device, at the place of the Rd/Wr bit::
62 S Addr Rd/Wr [A] P
77 S Addr Rd [A] [Data] NA P
105 S Addr Wr [A] Comm [A] Sr Addr Rd [A] [Data] NA P
119 S Addr Wr [A] Comm [A] Sr Addr Rd [A] [DataLow] A [DataHigh] NA P
169 Sr Addr Rd [A] [DataLow] A [DataHigh] NA P
186 Sr Addr Rd [A] [Count] A [Data] A [Data] A ... A [Data] NA P
217 Sr Addr Rd [A] [Count] A [Data] ... A P
305 Sr Addr Rd [A] [Data] A [Data] A ... A [Data] NA P
/openbmc/linux/arch/arm/kernel/
H A Dphys2virt.S84 @ MOVW | 1 1 1 1 0 | i | 1 0 0 1 0 0 | imm4 || 0 | imm3 | Rd | imm8 |
99 @ MOV | 1 1 1 1 0 | i | 0 0 0 1 0 0 1 1 1 1 || 0 | imm3 | Rd | imm8 |
100 @ MVN | 1 1 1 1 0 | i | 0 0 0 1 1 0 1 1 1 1 || 0 | imm3 | Rd | imm8 |
124 and ip, #0xf00 @ clear everything except Rd field
163 @ ADD | cond | 0 0 1 0 1 0 0 0 | Rn | Rd | imm12 |
164 @ SUB | cond | 0 0 1 0 0 1 0 0 | Rn | Rd | imm12 |
165 @ MOV | cond | 0 0 1 1 1 0 1 0 | Rn | Rd | imm12 |
166 @ MVN | cond | 0 0 1 1 1 1 1 0 | Rn | Rd | imm12 |
179 @ MOVW | cond | 0 0 1 1 0 0 0 0 | imm4 | Rd | imm12 |
/openbmc/qemu/target/hexagon/
H A Darch.h32 int arch_sf_recip_common(float32 *Rs, float32 *Rt, float32 *Rd,
34 int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, int *adjust,
H A Darch.c238 int arch_sf_recip_common(float32 *Rs, float32 *Rt, float32 *Rd, int *adjust, in arch_sf_recip_common() argument
329 *Rd = RdV; in arch_sf_recip_common()
334 int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, int *adjust, in arch_sf_invsqrt_common() argument
371 *Rd = RdV; in arch_sf_invsqrt_common()
/openbmc/linux/Documentation/translations/zh_CN/arch/loongarch/
H A Dintroduction.rst181 2R Opcode + Rj + Rd
182 3R Opcode + Rk + Rj + Rd
183 4R Opcode + Ra + Rk + Rj + Rd
184 2RI8 Opcode + I8 + Rj + Rd
185 2RI12 Opcode + I12 + Rj + Rd
186 2RI14 Opcode + I14 + Rj + Rd
187 2RI16 Opcode + I16 + Rj + Rd
192 Opcode是指令操作码，Rj和Rk是源操作数（寄存器），Rd是目标操作数（寄存器），Ra是
/openbmc/qemu/tests/tcg/cris/bare/
H A Dcheck_addcv17.s5 .macro addc Rs Rd inc=0
7 .word (\Rd << 12) | \Rs | (\inc << 10) | 0x09a0
/openbmc/qemu/target/hexagon/imported/
H A Dencode_pp.def755 DEF_FIELDROW_DESC32( ICLASS_CR" 1010 -------- PP------ --------","[#10] Rd=Cs ")
818 DEF_FIELDROW_DESC32(ICLASS_M" 0000 -------- PP------ --------","[#0] Rd=(Rs,#u8)")
966 DEF_FIELDROW_DESC32(ICLASS_M" 1001 -------- PP------ --------","[#9] Rd=(Rss,Rtt)")
1056 DEF_FIELDROW_DESC32(ICLASS_M" 1100 -------- PP------ --------","[#12] Rd=(Rs,Rt)")
1065 DEF_FIELDROW_DESC32(ICLASS_M" 1101 -------- PP------ --------","[#13] Rd=(Rs,Rt)")
1653 DEF_FIELDROW_DESC32(ICLASS_S2op" 1011 -------- PP------ --------","[#11] Rd=(Rs)")
1785 DEF_FIELDROW_DESC32(ICLASS_S3op" 0101 -------- PP------ --------","[#5] Rd=(Rss,Rt)")
1792 DEF_FIELDROW_DESC32(ICLASS_S3op" 0110 -------- PP------ --------","[#6] Rd=(Rs,Rt)")
1835 DEF_FIELDROW_DESC32(ICLASS_S3op" 1001 -------- PP------ --------","[#9] Rd=(Rs,Rtt)")
2065 DEF_FIELDROW_DESC32(ICLASS_ALU64" 0110 -------- PP------ --------","[#6] Rd=#u10 ")
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H A Dshift.idef27 /* NOTE: Rd[d] = Rs[s] *right* shifts with saturation don't make sense */
59 RSHIFTTYPES(r,Rd,Rs,4_8,,,fECHO,,)
91 RSATSHIFTTYPES(r_sat,Rd,Rs,4_8)
138 ISHIFTTYPES(r,5,Rd,Rs,4_4,,,fECHO,,)
153 ISHIFTTYPES_ONLY_ASL(r_sat,5,Rd,Rs,4_8,,,fSAT,:sat)
/openbmc/linux/Documentation/arch/arm/nwfpe/
H A Dnetwinder-fpe.rst51 FLT{cond}<S,D,E>{P,M,Z} Fn, Rd Convert integer to floating point
52 FIX{cond}{P,M,Z} Rd, Fn Convert floating point to integer
53 WFS{cond} Rd Write floating point status register
54 RFS{cond} Rd Read floating point status register
55 WFC{cond} Rd Write floating point control register
56 RFC{cond} Rd Read floating point control register
/openbmc/linux/Documentation/arch/loongarch/
H A Dintroduction.rst212 2R Opcode + Rj + Rd
213 3R Opcode + Rk + Rj + Rd
214 4R Opcode + Ra + Rk + Rj + Rd
215 2RI8 Opcode + I8 + Rj + Rd
216 2RI12 Opcode + I12 + Rj + Rd
217 2RI14 Opcode + I14 + Rj + Rd
218 2RI16 Opcode + I16 + Rj + Rd
223 Rd is the destination register operand, while Rj, Rk and Ra ("a" stands for
/openbmc/linux/arch/arm64/lib/
H A Dinsn.c1414 enum aarch64_insn_register Rd, in aarch64_insn_gen_logical_immediate() argument
1437 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, Rd); in aarch64_insn_gen_logical_immediate()
1445 enum aarch64_insn_register Rd, in aarch64_insn_gen_extr() argument
1469 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, Rd); in aarch64_insn_gen_extr()
/openbmc/linux/arch/arm64/include/asm/
H A Dinsn.h647 enum aarch64_insn_register Rd,
652 enum aarch64_insn_register Rd,
/openbmc/linux/tools/arch/x86/lib/
H A Dx86-opcode-map.txt372 20: MOV Rd,Cd
373 21: MOV Rd,Dd
374 22: MOV Cd,Rd
375 23: MOV Dd,Rd
839 14: vpextrb Rd/Mb,Vdq,Ib (66),(v1)
840 15: vpextrw Rd/Mw,Vdq,Ib (66),(v1)
1131 6: XSAVEOPT | clwb (66) | mfence (11B) | TPAUSE Rd (66),(11B) | UMONITOR Rv (F3),(11B) | UMWAIT Rd …
/openbmc/linux/arch/x86/lib/
H A Dx86-opcode-map.txt372 20: MOV Rd,Cd
373 21: MOV Rd,Dd
374 22: MOV Cd,Rd
375 23: MOV Dd,Rd
839 14: vpextrb Rd/Mb,Vdq,Ib (66),(v1)
840 15: vpextrw Rd/Mw,Vdq,Ib (66),(v1)
1131 6: XSAVEOPT | clwb (66) | mfence (11B) | TPAUSE Rd (66),(11B) | UMONITOR Rv (F3),(11B) | UMWAIT Rd …
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp135f-dk.dts81 * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
H A Dstm32mp15xx-dkx.dtsi105 * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
/openbmc/qemu/target/cris/
H A Dtranslate_v10.c.inc1047 * Instruction format: ADDC [Rs],Rd
1050 * |Destination(Rd)| 1 0 0 1 1 0 1 0 | Source(Rs)|
1053 * Instruction format: ADDC [Rs+],Rd
1056 * |Destination(Rd)| 1 1 0 1 1 0 1 0 | Source(Rs)|
/openbmc/openbmc/meta-openembedded/meta-oe/licenses/
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/openbmc/linux/
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/openbmc/qemu/target/hexagon/imported/mmvec/
H A Dencode_ext.def24 DEF_ENC(V6_extractw, ICLASS_LD" 001 0 000sssss PP0uuuuu --1ddddd") /* coproc insn, returns Rd */
/openbmc/qemu/target/mips/tcg/
H A Dmsa_helper.c5887 #define Rd(pwr, i) (pwr->d[i]) macro