1f6fcefa1SLuca Ceresoli================ 2f6fcefa1SLuca CeresoliThe I2C Protocol 3f6fcefa1SLuca Ceresoli================ 4ccf988b6SMauro Carvalho Chehab 59bbebdf7SLuca CeresoliThis document is an overview of the basic I2C transactions and the kernel 69bbebdf7SLuca CeresoliAPIs to perform them. 7ccf988b6SMauro Carvalho Chehab 8ccf988b6SMauro Carvalho ChehabKey to symbols 9ccf988b6SMauro Carvalho Chehab============== 10ccf988b6SMauro Carvalho Chehab 11ccf988b6SMauro Carvalho Chehab=============== ============================================================= 1202622c88SLuca CeresoliS Start condition 1302622c88SLuca CeresoliP Stop condition 1402622c88SLuca CeresoliRd/Wr (1 bit) Read/Write bit. Rd equals 1, Wr equals 0. 15db0d7424SLuca CeresoliA, NA (1 bit) Acknowledge (ACK) and Not Acknowledge (NACK) bit 1624d129d4SLuca CeresoliAddr (7 bits) I2C 7 bit address. Note that this can be expanded to 17ccf988b6SMauro Carvalho Chehab get a 10 bit I2C address. 18*0721ceeeSLuca CeresoliData (8 bits) A plain data byte. 19ccf988b6SMauro Carvalho Chehab 2002622c88SLuca Ceresoli[..] Data sent by I2C device, as opposed to data sent by the 21ccf988b6SMauro Carvalho Chehab host adapter. 22ccf988b6SMauro Carvalho Chehab=============== ============================================================= 23ccf988b6SMauro Carvalho Chehab 24ccf988b6SMauro Carvalho Chehab 25ccf988b6SMauro Carvalho ChehabSimple send transaction 26ccf988b6SMauro Carvalho Chehab======================= 27ccf988b6SMauro Carvalho Chehab 28ca5dbb02SLuca CeresoliImplemented by i2c_master_send():: 29ccf988b6SMauro Carvalho Chehab 30ccf988b6SMauro Carvalho Chehab S Addr Wr [A] Data [A] Data [A] ... [A] Data [A] P 31ccf988b6SMauro Carvalho Chehab 32ccf988b6SMauro Carvalho Chehab 33ccf988b6SMauro Carvalho ChehabSimple receive transaction 34ccf988b6SMauro Carvalho Chehab========================== 35ccf988b6SMauro Carvalho Chehab 36ca5dbb02SLuca CeresoliImplemented by i2c_master_recv():: 37ccf988b6SMauro Carvalho Chehab 38ccf988b6SMauro Carvalho Chehab S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P 39ccf988b6SMauro Carvalho Chehab 40ccf988b6SMauro Carvalho Chehab 41ccf988b6SMauro Carvalho ChehabCombined transactions 42ccf988b6SMauro Carvalho Chehab===================== 43ccf988b6SMauro Carvalho Chehab 44ca5dbb02SLuca CeresoliImplemented by i2c_transfer(). 45ccf988b6SMauro Carvalho Chehab 46f954731dSLuca CeresoliThey are just like the above transactions, but instead of a stop 47f954731dSLuca Ceresolicondition P a start condition S is sent and the transaction continues. 48f954731dSLuca CeresoliAn example of a byte read, followed by a byte write:: 49ccf988b6SMauro Carvalho Chehab 50ccf988b6SMauro Carvalho Chehab S Addr Rd [A] [Data] NA S Addr Wr [A] Data [A] P 51ccf988b6SMauro Carvalho Chehab 52ccf988b6SMauro Carvalho Chehab 53ccf988b6SMauro Carvalho ChehabModified transactions 54ccf988b6SMauro Carvalho Chehab===================== 55ccf988b6SMauro Carvalho Chehab 56ccf988b6SMauro Carvalho ChehabThe following modifications to the I2C protocol can also be generated by 572f07c05fSLuca Ceresolisetting these flags for I2C messages. With the exception of I2C_M_NOSTART, they 58ccf988b6SMauro Carvalho Chehabare usually only needed to work around device issues: 59ccf988b6SMauro Carvalho Chehab 60ccf988b6SMauro Carvalho ChehabI2C_M_IGNORE_NAK: 61ccf988b6SMauro Carvalho Chehab Normally message is interrupted immediately if there is [NA] from the 62ccf988b6SMauro Carvalho Chehab client. Setting this flag treats any [NA] as [A], and all of 63ccf988b6SMauro Carvalho Chehab message is sent. 64ccf988b6SMauro Carvalho Chehab These messages may still fail to SCL lo->hi timeout. 65ccf988b6SMauro Carvalho Chehab 66ccf988b6SMauro Carvalho ChehabI2C_M_NO_RD_ACK: 67ccf988b6SMauro Carvalho Chehab In a read message, master A/NA bit is skipped. 68ccf988b6SMauro Carvalho Chehab 69ccf988b6SMauro Carvalho ChehabI2C_M_NOSTART: 70ccf988b6SMauro Carvalho Chehab In a combined transaction, no 'S Addr Wr/Rd [A]' is generated at some 71ccf988b6SMauro Carvalho Chehab point. For example, setting I2C_M_NOSTART on the second partial message 72ccf988b6SMauro Carvalho Chehab generates something like:: 73ccf988b6SMauro Carvalho Chehab 74ccf988b6SMauro Carvalho Chehab S Addr Rd [A] [Data] NA Data [A] P 75ccf988b6SMauro Carvalho Chehab 76ccf988b6SMauro Carvalho Chehab If you set the I2C_M_NOSTART variable for the first partial message, 77f954731dSLuca Ceresoli we do not generate Addr, but we do generate the start condition S. 78f954731dSLuca Ceresoli This will probably confuse all other clients on your bus, so don't 79f954731dSLuca Ceresoli try this. 80ccf988b6SMauro Carvalho Chehab 81ccf988b6SMauro Carvalho Chehab This is often used to gather transmits from multiple data buffers in 82ccf988b6SMauro Carvalho Chehab system memory into something that appears as a single transfer to the 83ccf988b6SMauro Carvalho Chehab I2C device but may also be used between direction changes by some 84ccf988b6SMauro Carvalho Chehab rare devices. 85ccf988b6SMauro Carvalho Chehab 86ccf988b6SMauro Carvalho ChehabI2C_M_REV_DIR_ADDR: 87ccf988b6SMauro Carvalho Chehab This toggles the Rd/Wr flag. That is, if you want to do a write, but 88ccf988b6SMauro Carvalho Chehab need to emit an Rd instead of a Wr, or vice versa, you set this 89ccf988b6SMauro Carvalho Chehab flag. For example:: 90ccf988b6SMauro Carvalho Chehab 91ccf988b6SMauro Carvalho Chehab S Addr Rd [A] Data [A] Data [A] ... [A] Data [A] P 92ccf988b6SMauro Carvalho Chehab 93ccf988b6SMauro Carvalho ChehabI2C_M_STOP: 94ccf988b6SMauro Carvalho Chehab Force a stop condition (P) after the message. Some I2C related protocols 95ccf988b6SMauro Carvalho Chehab like SCCB require that. Normally, you really don't want to get interrupted 96ccf988b6SMauro Carvalho Chehab between the messages of one transfer. 97