1caab277bSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2e54bcde3SZi Shen Lim /* 3e54bcde3SZi Shen Lim * BPF JIT compiler for ARM64 4e54bcde3SZi Shen Lim * 5ddb55992SZi Shen Lim * Copyright (C) 2014-2016 Zi Shen Lim <zlim.lnx@gmail.com> 6e54bcde3SZi Shen Lim */ 7e54bcde3SZi Shen Lim #ifndef _BPF_JIT_H 8e54bcde3SZi Shen Lim #define _BPF_JIT_H 9e54bcde3SZi Shen Lim 10e54bcde3SZi Shen Lim #include <asm/insn.h> 11e54bcde3SZi Shen Lim 12e54bcde3SZi Shen Lim /* 5-bit Register Operand */ 13e54bcde3SZi Shen Lim #define A64_R(x) AARCH64_INSN_REG_##x 14e54bcde3SZi Shen Lim #define A64_FP AARCH64_INSN_REG_FP 15e54bcde3SZi Shen Lim #define A64_LR AARCH64_INSN_REG_LR 16e54bcde3SZi Shen Lim #define A64_ZR AARCH64_INSN_REG_ZR 17e54bcde3SZi Shen Lim #define A64_SP AARCH64_INSN_REG_SP 18e54bcde3SZi Shen Lim 19e54bcde3SZi Shen Lim #define A64_VARIANT(sf) \ 20e54bcde3SZi Shen Lim ((sf) ? AARCH64_INSN_VARIANT_64BIT : AARCH64_INSN_VARIANT_32BIT) 21e54bcde3SZi Shen Lim 22e54bcde3SZi Shen Lim /* Compare & branch (immediate) */ 23e54bcde3SZi Shen Lim #define A64_COMP_BRANCH(sf, Rt, offset, type) \ 24e54bcde3SZi Shen Lim aarch64_insn_gen_comp_branch_imm(0, offset, Rt, A64_VARIANT(sf), \ 25e54bcde3SZi Shen Lim AARCH64_INSN_BRANCH_COMP_##type) 26e54bcde3SZi Shen Lim #define A64_CBZ(sf, Rt, imm19) A64_COMP_BRANCH(sf, Rt, (imm19) << 2, ZERO) 27251599e1SZi Shen Lim #define A64_CBNZ(sf, Rt, imm19) A64_COMP_BRANCH(sf, Rt, (imm19) << 2, NONZERO) 28e54bcde3SZi Shen Lim 29e54bcde3SZi Shen Lim /* Conditional branch (immediate) */ 30e54bcde3SZi Shen Lim #define A64_COND_BRANCH(cond, offset) \ 31e54bcde3SZi Shen Lim aarch64_insn_gen_cond_branch_imm(0, offset, cond) 32e54bcde3SZi Shen Lim #define A64_COND_EQ AARCH64_INSN_COND_EQ /* == */ 33e54bcde3SZi Shen Lim #define A64_COND_NE AARCH64_INSN_COND_NE /* != */ 34e54bcde3SZi Shen Lim #define A64_COND_CS AARCH64_INSN_COND_CS /* unsigned >= */ 35e54bcde3SZi Shen Lim #define A64_COND_HI AARCH64_INSN_COND_HI /* unsigned > */ 36c362b2f3SDaniel Borkmann #define A64_COND_LS AARCH64_INSN_COND_LS /* unsigned <= */ 37c362b2f3SDaniel Borkmann #define A64_COND_CC AARCH64_INSN_COND_CC /* unsigned < */ 38e54bcde3SZi Shen Lim #define A64_COND_GE AARCH64_INSN_COND_GE /* signed >= */ 39e54bcde3SZi Shen Lim #define A64_COND_GT AARCH64_INSN_COND_GT /* signed > */ 40c362b2f3SDaniel Borkmann #define A64_COND_LE AARCH64_INSN_COND_LE /* signed <= */ 41c362b2f3SDaniel Borkmann #define A64_COND_LT AARCH64_INSN_COND_LT /* signed < */ 42e54bcde3SZi Shen Lim #define A64_B_(cond, imm19) A64_COND_BRANCH(cond, (imm19) << 2) 43e54bcde3SZi Shen Lim 44e54bcde3SZi Shen Lim /* Unconditional branch (immediate) */ 45e54bcde3SZi Shen Lim #define A64_BRANCH(offset, type) aarch64_insn_gen_branch_imm(0, offset, \ 46e54bcde3SZi Shen Lim AARCH64_INSN_BRANCH_##type) 47e54bcde3SZi Shen Lim #define A64_B(imm26) A64_BRANCH((imm26) << 2, NOLINK) 48e54bcde3SZi Shen Lim #define A64_BL(imm26) A64_BRANCH((imm26) << 2, LINK) 49e54bcde3SZi Shen Lim 50e54bcde3SZi Shen Lim /* Unconditional branch (register) */ 51ddb55992SZi Shen Lim #define A64_BR(Rn) aarch64_insn_gen_branch_reg(Rn, AARCH64_INSN_BRANCH_NOLINK) 52e54bcde3SZi Shen Lim #define A64_BLR(Rn) aarch64_insn_gen_branch_reg(Rn, AARCH64_INSN_BRANCH_LINK) 53e54bcde3SZi Shen Lim #define A64_RET(Rn) aarch64_insn_gen_branch_reg(Rn, AARCH64_INSN_BRANCH_RETURN) 54e54bcde3SZi Shen Lim 55e54bcde3SZi Shen Lim /* Load/store register (register offset) */ 56e54bcde3SZi Shen Lim #define A64_LS_REG(Rt, Rn, Rm, size, type) \ 57e54bcde3SZi Shen Lim aarch64_insn_gen_load_store_reg(Rt, Rn, Rm, \ 58e54bcde3SZi Shen Lim AARCH64_INSN_SIZE_##size, \ 59e54bcde3SZi Shen Lim AARCH64_INSN_LDST_##type##_REG_OFFSET) 60e54bcde3SZi Shen Lim #define A64_STRB(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 8, STORE) 61e54bcde3SZi Shen Lim #define A64_LDRB(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 8, LOAD) 62cc88f540SXu Kuohai #define A64_LDRSB(Xt, Xn, Xm) A64_LS_REG(Xt, Xn, Xm, 8, SIGNED_LOAD) 63e54bcde3SZi Shen Lim #define A64_STRH(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 16, STORE) 64e54bcde3SZi Shen Lim #define A64_LDRH(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 16, LOAD) 65cc88f540SXu Kuohai #define A64_LDRSH(Xt, Xn, Xm) A64_LS_REG(Xt, Xn, Xm, 16, SIGNED_LOAD) 66e54bcde3SZi Shen Lim #define A64_STR32(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 32, STORE) 67e54bcde3SZi Shen Lim #define A64_LDR32(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 32, LOAD) 68cc88f540SXu Kuohai #define A64_LDRSW(Xt, Xn, Xm) A64_LS_REG(Xt, Xn, Xm, 32, SIGNED_LOAD) 69e54bcde3SZi Shen Lim #define A64_STR64(Xt, Xn, Xm) A64_LS_REG(Xt, Xn, Xm, 64, STORE) 70e54bcde3SZi Shen Lim #define A64_LDR64(Xt, Xn, Xm) A64_LS_REG(Xt, Xn, Xm, 64, LOAD) 71e54bcde3SZi Shen Lim 727db6c0f1SXu Kuohai /* Load/store register (immediate offset) */ 737db6c0f1SXu Kuohai #define A64_LS_IMM(Rt, Rn, imm, size, type) \ 747db6c0f1SXu Kuohai aarch64_insn_gen_load_store_imm(Rt, Rn, imm, \ 757db6c0f1SXu Kuohai AARCH64_INSN_SIZE_##size, \ 767db6c0f1SXu Kuohai AARCH64_INSN_LDST_##type##_IMM_OFFSET) 777db6c0f1SXu Kuohai #define A64_STRBI(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 8, STORE) 787db6c0f1SXu Kuohai #define A64_LDRBI(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 8, LOAD) 79cc88f540SXu Kuohai #define A64_LDRSBI(Xt, Xn, imm) A64_LS_IMM(Xt, Xn, imm, 8, SIGNED_LOAD) 807db6c0f1SXu Kuohai #define A64_STRHI(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 16, STORE) 817db6c0f1SXu Kuohai #define A64_LDRHI(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 16, LOAD) 82cc88f540SXu Kuohai #define A64_LDRSHI(Xt, Xn, imm) A64_LS_IMM(Xt, Xn, imm, 16, SIGNED_LOAD) 837db6c0f1SXu Kuohai #define A64_STR32I(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 32, STORE) 847db6c0f1SXu Kuohai #define A64_LDR32I(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 32, LOAD) 85cc88f540SXu Kuohai #define A64_LDRSWI(Xt, Xn, imm) A64_LS_IMM(Xt, Xn, imm, 32, SIGNED_LOAD) 867db6c0f1SXu Kuohai #define A64_STR64I(Xt, Xn, imm) A64_LS_IMM(Xt, Xn, imm, 64, STORE) 877db6c0f1SXu Kuohai #define A64_LDR64I(Xt, Xn, imm) A64_LS_IMM(Xt, Xn, imm, 64, LOAD) 887db6c0f1SXu Kuohai 89b2ad54e1SXu Kuohai /* LDR (literal) */ 90b2ad54e1SXu Kuohai #define A64_LDR32LIT(Wt, offset) \ 91b2ad54e1SXu Kuohai aarch64_insn_gen_load_literal(0, offset, Wt, false) 92b2ad54e1SXu Kuohai #define A64_LDR64LIT(Xt, offset) \ 93b2ad54e1SXu Kuohai aarch64_insn_gen_load_literal(0, offset, Xt, true) 94b2ad54e1SXu Kuohai 95e54bcde3SZi Shen Lim /* Load/store register pair */ 96e54bcde3SZi Shen Lim #define A64_LS_PAIR(Rt, Rt2, Rn, offset, ls, type) \ 97e54bcde3SZi Shen Lim aarch64_insn_gen_load_store_pair(Rt, Rt2, Rn, offset, \ 98e54bcde3SZi Shen Lim AARCH64_INSN_VARIANT_64BIT, \ 99e54bcde3SZi Shen Lim AARCH64_INSN_LDST_##ls##_PAIR_##type) 100e54bcde3SZi Shen Lim /* Rn -= 16; Rn[0] = Rt; Rn[8] = Rt2; */ 101e54bcde3SZi Shen Lim #define A64_PUSH(Rt, Rt2, Rn) A64_LS_PAIR(Rt, Rt2, Rn, -16, STORE, PRE_INDEX) 102e54bcde3SZi Shen Lim /* Rt = Rn[0]; Rt2 = Rn[8]; Rn += 16; */ 103e54bcde3SZi Shen Lim #define A64_POP(Rt, Rt2, Rn) A64_LS_PAIR(Rt, Rt2, Rn, 16, LOAD, POST_INDEX) 104e54bcde3SZi Shen Lim 10585f68fe8SDaniel Borkmann /* Load/store exclusive */ 10685f68fe8SDaniel Borkmann #define A64_SIZE(sf) \ 10785f68fe8SDaniel Borkmann ((sf) ? AARCH64_INSN_SIZE_64 : AARCH64_INSN_SIZE_32) 10885f68fe8SDaniel Borkmann #define A64_LSX(sf, Rt, Rn, Rs, type) \ 10985f68fe8SDaniel Borkmann aarch64_insn_gen_load_store_ex(Rt, Rn, Rs, A64_SIZE(sf), \ 11085f68fe8SDaniel Borkmann AARCH64_INSN_LDST_##type) 11185f68fe8SDaniel Borkmann /* Rt = [Rn]; (atomic) */ 11285f68fe8SDaniel Borkmann #define A64_LDXR(sf, Rt, Rn) \ 11385f68fe8SDaniel Borkmann A64_LSX(sf, Rt, Rn, A64_ZR, LOAD_EX) 11485f68fe8SDaniel Borkmann /* [Rn] = Rt; (atomic) Rs = [state] */ 11585f68fe8SDaniel Borkmann #define A64_STXR(sf, Rt, Rn, Rs) \ 11685f68fe8SDaniel Borkmann A64_LSX(sf, Rt, Rn, Rs, STORE_EX) 1171902472bSHou Tao /* [Rn] = Rt (store release); (atomic) Rs = [state] */ 1181902472bSHou Tao #define A64_STLXR(sf, Rt, Rn, Rs) \ 1191902472bSHou Tao aarch64_insn_gen_load_store_ex(Rt, Rn, Rs, A64_SIZE(sf), \ 1201902472bSHou Tao AARCH64_INSN_LDST_STORE_REL_EX) 12185f68fe8SDaniel Borkmann 122fa1114d9SHou Tao /* 123fa1114d9SHou Tao * LSE atomics 124fa1114d9SHou Tao * 1251902472bSHou Tao * ST{ADD,CLR,SET,EOR} is simply encoded as an alias for 1261902472bSHou Tao * LDD{ADD,CLR,SET,EOR} with XZR as the destination register. 127fa1114d9SHou Tao */ 1281902472bSHou Tao #define A64_ST_OP(sf, Rn, Rs, op) \ 129fa1114d9SHou Tao aarch64_insn_gen_atomic_ld_op(A64_ZR, Rn, Rs, \ 1301902472bSHou Tao A64_SIZE(sf), AARCH64_INSN_MEM_ATOMIC_##op, \ 131fa1114d9SHou Tao AARCH64_INSN_MEM_ORDER_NONE) 1321902472bSHou Tao /* [Rn] <op>= Rs */ 1331902472bSHou Tao #define A64_STADD(sf, Rn, Rs) A64_ST_OP(sf, Rn, Rs, ADD) 1341902472bSHou Tao #define A64_STCLR(sf, Rn, Rs) A64_ST_OP(sf, Rn, Rs, CLR) 1351902472bSHou Tao #define A64_STEOR(sf, Rn, Rs) A64_ST_OP(sf, Rn, Rs, EOR) 1361902472bSHou Tao #define A64_STSET(sf, Rn, Rs) A64_ST_OP(sf, Rn, Rs, SET) 1371902472bSHou Tao 1381902472bSHou Tao #define A64_LD_OP_AL(sf, Rt, Rn, Rs, op) \ 1391902472bSHou Tao aarch64_insn_gen_atomic_ld_op(Rt, Rn, Rs, \ 1401902472bSHou Tao A64_SIZE(sf), AARCH64_INSN_MEM_ATOMIC_##op, \ 1411902472bSHou Tao AARCH64_INSN_MEM_ORDER_ACQREL) 1421902472bSHou Tao /* Rt = [Rn] (load acquire); [Rn] <op>= Rs (store release) */ 1431902472bSHou Tao #define A64_LDADDAL(sf, Rt, Rn, Rs) A64_LD_OP_AL(sf, Rt, Rn, Rs, ADD) 1441902472bSHou Tao #define A64_LDCLRAL(sf, Rt, Rn, Rs) A64_LD_OP_AL(sf, Rt, Rn, Rs, CLR) 1451902472bSHou Tao #define A64_LDEORAL(sf, Rt, Rn, Rs) A64_LD_OP_AL(sf, Rt, Rn, Rs, EOR) 1461902472bSHou Tao #define A64_LDSETAL(sf, Rt, Rn, Rs) A64_LD_OP_AL(sf, Rt, Rn, Rs, SET) 1471902472bSHou Tao /* Rt = [Rn] (load acquire); [Rn] = Rs (store release) */ 1481902472bSHou Tao #define A64_SWPAL(sf, Rt, Rn, Rs) A64_LD_OP_AL(sf, Rt, Rn, Rs, SWP) 1491902472bSHou Tao /* Rs = CAS(Rn, Rs, Rt) (load acquire & store release) */ 1501902472bSHou Tao #define A64_CASAL(sf, Rt, Rn, Rs) \ 1511902472bSHou Tao aarch64_insn_gen_cas(Rt, Rn, Rs, A64_SIZE(sf), \ 1521902472bSHou Tao AARCH64_INSN_MEM_ORDER_ACQREL) 15334b8ab09SDaniel Borkmann 154e54bcde3SZi Shen Lim /* Add/subtract (immediate) */ 155e54bcde3SZi Shen Lim #define A64_ADDSUB_IMM(sf, Rd, Rn, imm12, type) \ 156e54bcde3SZi Shen Lim aarch64_insn_gen_add_sub_imm(Rd, Rn, imm12, \ 157e54bcde3SZi Shen Lim A64_VARIANT(sf), AARCH64_INSN_ADSB_##type) 158e54bcde3SZi Shen Lim /* Rd = Rn OP imm12 */ 159e54bcde3SZi Shen Lim #define A64_ADD_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, ADD) 160e54bcde3SZi Shen Lim #define A64_SUB_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, SUB) 161fd868f14SLuke Nelson #define A64_ADDS_I(sf, Rd, Rn, imm12) \ 162fd868f14SLuke Nelson A64_ADDSUB_IMM(sf, Rd, Rn, imm12, ADD_SETFLAGS) 163fd868f14SLuke Nelson #define A64_SUBS_I(sf, Rd, Rn, imm12) \ 164fd868f14SLuke Nelson A64_ADDSUB_IMM(sf, Rd, Rn, imm12, SUB_SETFLAGS) 165fd868f14SLuke Nelson /* Rn + imm12; set condition flags */ 166fd868f14SLuke Nelson #define A64_CMN_I(sf, Rn, imm12) A64_ADDS_I(sf, A64_ZR, Rn, imm12) 167fd868f14SLuke Nelson /* Rn - imm12; set condition flags */ 168fd868f14SLuke Nelson #define A64_CMP_I(sf, Rn, imm12) A64_SUBS_I(sf, A64_ZR, Rn, imm12) 169e54bcde3SZi Shen Lim /* Rd = Rn */ 170e54bcde3SZi Shen Lim #define A64_MOV(sf, Rd, Rn) A64_ADD_I(sf, Rd, Rn, 0) 171e54bcde3SZi Shen Lim 172e54bcde3SZi Shen Lim /* Bitfield move */ 173e54bcde3SZi Shen Lim #define A64_BITFIELD(sf, Rd, Rn, immr, imms, type) \ 174e54bcde3SZi Shen Lim aarch64_insn_gen_bitfield(Rd, Rn, immr, imms, \ 175e54bcde3SZi Shen Lim A64_VARIANT(sf), AARCH64_INSN_BITFIELD_MOVE_##type) 176e54bcde3SZi Shen Lim /* Signed, with sign replication to left and zeros to right */ 177e54bcde3SZi Shen Lim #define A64_SBFM(sf, Rd, Rn, ir, is) A64_BITFIELD(sf, Rd, Rn, ir, is, SIGNED) 178e54bcde3SZi Shen Lim /* Unsigned, with zeros to left and right */ 179e54bcde3SZi Shen Lim #define A64_UBFM(sf, Rd, Rn, ir, is) A64_BITFIELD(sf, Rd, Rn, ir, is, UNSIGNED) 180e54bcde3SZi Shen Lim 181e54bcde3SZi Shen Lim /* Rd = Rn << shift */ 182e54bcde3SZi Shen Lim #define A64_LSL(sf, Rd, Rn, shift) ({ \ 183e54bcde3SZi Shen Lim int sz = (sf) ? 64 : 32; \ 184e54bcde3SZi Shen Lim A64_UBFM(sf, Rd, Rn, (unsigned)-(shift) % sz, sz - 1 - (shift)); \ 185e54bcde3SZi Shen Lim }) 186e54bcde3SZi Shen Lim /* Rd = Rn >> shift */ 187e54bcde3SZi Shen Lim #define A64_LSR(sf, Rd, Rn, shift) A64_UBFM(sf, Rd, Rn, shift, (sf) ? 63 : 31) 188e54bcde3SZi Shen Lim /* Rd = Rn >> shift; signed */ 189e54bcde3SZi Shen Lim #define A64_ASR(sf, Rd, Rn, shift) A64_SBFM(sf, Rd, Rn, shift, (sf) ? 63 : 31) 190e54bcde3SZi Shen Lim 191d63903bbSXi Wang /* Zero extend */ 192d63903bbSXi Wang #define A64_UXTH(sf, Rd, Rn) A64_UBFM(sf, Rd, Rn, 0, 15) 193d63903bbSXi Wang #define A64_UXTW(sf, Rd, Rn) A64_UBFM(sf, Rd, Rn, 0, 31) 194d63903bbSXi Wang 195bb0a1d6bSXu Kuohai /* Sign extend */ 196bb0a1d6bSXu Kuohai #define A64_SXTB(sf, Rd, Rn) A64_SBFM(sf, Rd, Rn, 0, 7) 197bb0a1d6bSXu Kuohai #define A64_SXTH(sf, Rd, Rn) A64_SBFM(sf, Rd, Rn, 0, 15) 198bb0a1d6bSXu Kuohai #define A64_SXTW(sf, Rd, Rn) A64_SBFM(sf, Rd, Rn, 0, 31) 199bb0a1d6bSXu Kuohai 200e54bcde3SZi Shen Lim /* Move wide (immediate) */ 201e54bcde3SZi Shen Lim #define A64_MOVEW(sf, Rd, imm16, shift, type) \ 202e54bcde3SZi Shen Lim aarch64_insn_gen_movewide(Rd, imm16, shift, \ 203e54bcde3SZi Shen Lim A64_VARIANT(sf), AARCH64_INSN_MOVEWIDE_##type) 204e54bcde3SZi Shen Lim /* Rd = Zeros (for MOVZ); 205e54bcde3SZi Shen Lim * Rd |= imm16 << shift (where shift is {0, 16, 32, 48}); 206e54bcde3SZi Shen Lim * Rd = ~Rd; (for MOVN); */ 207e54bcde3SZi Shen Lim #define A64_MOVN(sf, Rd, imm16, shift) A64_MOVEW(sf, Rd, imm16, shift, INVERSE) 208e54bcde3SZi Shen Lim #define A64_MOVZ(sf, Rd, imm16, shift) A64_MOVEW(sf, Rd, imm16, shift, ZERO) 209e54bcde3SZi Shen Lim #define A64_MOVK(sf, Rd, imm16, shift) A64_MOVEW(sf, Rd, imm16, shift, KEEP) 210e54bcde3SZi Shen Lim 211e54bcde3SZi Shen Lim /* Add/subtract (shifted register) */ 212e54bcde3SZi Shen Lim #define A64_ADDSUB_SREG(sf, Rd, Rn, Rm, type) \ 213e54bcde3SZi Shen Lim aarch64_insn_gen_add_sub_shifted_reg(Rd, Rn, Rm, 0, \ 214e54bcde3SZi Shen Lim A64_VARIANT(sf), AARCH64_INSN_ADSB_##type) 215e54bcde3SZi Shen Lim /* Rd = Rn OP Rm */ 216e54bcde3SZi Shen Lim #define A64_ADD(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, ADD) 217e54bcde3SZi Shen Lim #define A64_SUB(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB) 218e54bcde3SZi Shen Lim #define A64_SUBS(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB_SETFLAGS) 219e54bcde3SZi Shen Lim /* Rd = -Rm */ 220e54bcde3SZi Shen Lim #define A64_NEG(sf, Rd, Rm) A64_SUB(sf, Rd, A64_ZR, Rm) 221e54bcde3SZi Shen Lim /* Rn - Rm; set condition flags */ 222e54bcde3SZi Shen Lim #define A64_CMP(sf, Rn, Rm) A64_SUBS(sf, A64_ZR, Rn, Rm) 223e54bcde3SZi Shen Lim 224e54bcde3SZi Shen Lim /* Data-processing (1 source) */ 225e54bcde3SZi Shen Lim #define A64_DATA1(sf, Rd, Rn, type) aarch64_insn_gen_data1(Rd, Rn, \ 226e54bcde3SZi Shen Lim A64_VARIANT(sf), AARCH64_INSN_DATA1_##type) 227e54bcde3SZi Shen Lim /* Rd = BSWAPx(Rn) */ 228e54bcde3SZi Shen Lim #define A64_REV16(sf, Rd, Rn) A64_DATA1(sf, Rd, Rn, REVERSE_16) 229e54bcde3SZi Shen Lim #define A64_REV32(sf, Rd, Rn) A64_DATA1(sf, Rd, Rn, REVERSE_32) 230e54bcde3SZi Shen Lim #define A64_REV64(Rd, Rn) A64_DATA1(1, Rd, Rn, REVERSE_64) 231e54bcde3SZi Shen Lim 232e54bcde3SZi Shen Lim /* Data-processing (2 source) */ 233e54bcde3SZi Shen Lim /* Rd = Rn OP Rm */ 234d65a634aSZi Shen Lim #define A64_DATA2(sf, Rd, Rn, Rm, type) aarch64_insn_gen_data2(Rd, Rn, Rm, \ 235d65a634aSZi Shen Lim A64_VARIANT(sf), AARCH64_INSN_DATA2_##type) 236d65a634aSZi Shen Lim #define A64_UDIV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, UDIV) 237*68b18191SXu Kuohai #define A64_SDIV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, SDIV) 238d65a634aSZi Shen Lim #define A64_LSLV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSLV) 239d65a634aSZi Shen Lim #define A64_LSRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSRV) 240d65a634aSZi Shen Lim #define A64_ASRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, ASRV) 241e54bcde3SZi Shen Lim 242e54bcde3SZi Shen Lim /* Data-processing (3 source) */ 243e54bcde3SZi Shen Lim /* Rd = Ra + Rn * Rm */ 244e54bcde3SZi Shen Lim #define A64_MADD(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \ 245e54bcde3SZi Shen Lim A64_VARIANT(sf), AARCH64_INSN_DATA3_MADD) 246504792e0SJerin Jacob /* Rd = Ra - Rn * Rm */ 247504792e0SJerin Jacob #define A64_MSUB(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \ 248504792e0SJerin Jacob A64_VARIANT(sf), AARCH64_INSN_DATA3_MSUB) 249e54bcde3SZi Shen Lim /* Rd = Rn * Rm */ 250e54bcde3SZi Shen Lim #define A64_MUL(sf, Rd, Rn, Rm) A64_MADD(sf, Rd, A64_ZR, Rn, Rm) 251e54bcde3SZi Shen Lim 252e54bcde3SZi Shen Lim /* Logical (shifted register) */ 253e54bcde3SZi Shen Lim #define A64_LOGIC_SREG(sf, Rd, Rn, Rm, type) \ 254e54bcde3SZi Shen Lim aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \ 255e54bcde3SZi Shen Lim A64_VARIANT(sf), AARCH64_INSN_LOGIC_##type) 256e54bcde3SZi Shen Lim /* Rd = Rn OP Rm */ 257e54bcde3SZi Shen Lim #define A64_AND(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND) 258e54bcde3SZi Shen Lim #define A64_ORR(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, ORR) 259e54bcde3SZi Shen Lim #define A64_EOR(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, EOR) 260e54bcde3SZi Shen Lim #define A64_ANDS(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND_SETFLAGS) 261e54bcde3SZi Shen Lim /* Rn & Rm; set condition flags */ 262e54bcde3SZi Shen Lim #define A64_TST(sf, Rn, Rm) A64_ANDS(sf, A64_ZR, Rn, Rm) 2631902472bSHou Tao /* Rd = ~Rm (alias of ORN with A64_ZR as Rn) */ 2641902472bSHou Tao #define A64_MVN(sf, Rd, Rm) \ 2651902472bSHou Tao A64_LOGIC_SREG(sf, Rd, A64_ZR, Rm, ORN) 266e54bcde3SZi Shen Lim 267fd49591cSLuke Nelson /* Logical (immediate) */ 268fd49591cSLuke Nelson #define A64_LOGIC_IMM(sf, Rd, Rn, imm, type) ({ \ 269fd49591cSLuke Nelson u64 imm64 = (sf) ? (u64)imm : (u64)(u32)imm; \ 270fd49591cSLuke Nelson aarch64_insn_gen_logical_immediate(AARCH64_INSN_LOGIC_##type, \ 271fd49591cSLuke Nelson A64_VARIANT(sf), Rn, Rd, imm64); \ 272fd49591cSLuke Nelson }) 273fd49591cSLuke Nelson /* Rd = Rn OP imm */ 274fd49591cSLuke Nelson #define A64_AND_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, AND) 275fd49591cSLuke Nelson #define A64_ORR_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, ORR) 276fd49591cSLuke Nelson #define A64_EOR_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, EOR) 277fd49591cSLuke Nelson #define A64_ANDS_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, AND_SETFLAGS) 278fd49591cSLuke Nelson /* Rn & imm; set condition flags */ 279fd49591cSLuke Nelson #define A64_TST_I(sf, Rn, imm) A64_ANDS_I(sf, A64_ZR, Rn, imm) 280fd49591cSLuke Nelson 281fa76cfe6SMark Brown /* HINTs */ 282fa76cfe6SMark Brown #define A64_HINT(x) aarch64_insn_gen_hint(x) 283fa76cfe6SMark Brown 284042152c2SXu Kuohai #define A64_PACIASP A64_HINT(AARCH64_INSN_HINT_PACIASP) 285042152c2SXu Kuohai #define A64_AUTIASP A64_HINT(AARCH64_INSN_HINT_AUTIASP) 286042152c2SXu Kuohai 287fa76cfe6SMark Brown /* BTI */ 288fa76cfe6SMark Brown #define A64_BTI_C A64_HINT(AARCH64_INSN_HINT_BTIC) 289fa76cfe6SMark Brown #define A64_BTI_J A64_HINT(AARCH64_INSN_HINT_BTIJ) 290fa76cfe6SMark Brown #define A64_BTI_JC A64_HINT(AARCH64_INSN_HINT_BTIJC) 291b2ad54e1SXu Kuohai #define A64_NOP A64_HINT(AARCH64_INSN_HINT_NOP) 292fa76cfe6SMark Brown 2931902472bSHou Tao /* DMB */ 2941902472bSHou Tao #define A64_DMB_ISH aarch64_insn_gen_dmb(AARCH64_INSN_MB_ISH) 2951902472bSHou Tao 296738a96c4SXu Kuohai /* ADR */ 297738a96c4SXu Kuohai #define A64_ADR(Rd, offset) \ 298738a96c4SXu Kuohai aarch64_insn_gen_adr(0, offset, Rd, AARCH64_INSN_ADR_TYPE_ADR) 299738a96c4SXu Kuohai 300e54bcde3SZi Shen Lim #endif /* _BPF_JIT_H */ 301