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Searched refs:RREG32 (Results 1 – 25 of 184) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/radeon/
H A Dradeon_bios.c269 bus_cntl = RREG32(R600_BUS_CNTL); in ni_read_disabled_bios()
270 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); in ni_read_disabled_bios()
271 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); in ni_read_disabled_bios()
272 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); in ni_read_disabled_bios()
273 rom_cntl = RREG32(R600_ROM_CNTL); in ni_read_disabled_bios()
315 viph_control = RREG32(RADEON_VIPH_CONTROL); in r700_read_disabled_bios()
316 bus_cntl = RREG32(R600_BUS_CNTL); in r700_read_disabled_bios()
317 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); in r700_read_disabled_bios()
318 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); in r700_read_disabled_bios()
319 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); in r700_read_disabled_bios()
[all …]
H A Dradeon_legacy_encoders.c67 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_update()
95 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN); in radeon_legacy_lvds_update()
98 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_update()
103 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_update()
198 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); in radeon_legacy_lvds_mode_set()
201 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
208 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
219 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_mode_set()
289 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> in radeon_legacy_get_backlight_level()
361 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> in radeon_legacy_backlight_get_brightness()
[all …]
H A Dradeon_i2c.c124 temp = RREG32(rec->mask_clk_reg); in pre_xfer()
130 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; in pre_xfer()
133 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; in pre_xfer()
137 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; in pre_xfer()
140 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; in pre_xfer()
144 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; in pre_xfer()
146 temp = RREG32(rec->mask_clk_reg); in pre_xfer()
148 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; in pre_xfer()
150 temp = RREG32(rec->mask_data_reg); in pre_xfer()
163 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; in post_xfer()
[all …]
H A Dvce_v2_0.c44 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
48 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
52 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
58 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
63 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
68 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
78 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_dyn_cg()
88 orig = tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
94 orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
135 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v2_0_init_cg()
[all …]
H A Dvce_v1_0.c64 return RREG32(VCE_RB_RPTR); in vce_v1_0_get_rptr()
66 return RREG32(VCE_RB_RPTR2); in vce_v1_0_get_rptr()
81 return RREG32(VCE_RB_WPTR); in vce_v1_0_get_wptr()
83 return RREG32(VCE_RB_WPTR2); in vce_v1_0_get_wptr()
108 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v1_0_enable_mgcg()
112 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v1_0_enable_mgcg()
117 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v1_0_enable_mgcg()
121 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v1_0_enable_mgcg()
125 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v1_0_enable_mgcg()
130 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v1_0_enable_mgcg()
[all …]
H A Drs600.c65 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) in avivo_is_in_vblank()
75 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
76 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
99 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) in avivo_wait_for_vblank()
124 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rs600_page_flip()
145 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rs600_page_flip()
161 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rs600_page_flip_pending()
239 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
248 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
334 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); in rs600_pm_prepare()
[all …]
H A Drv730_dpm.c200 RREG32(CG_SPLL_FUNC_CNTL); in rv730_read_clock_registers()
202 RREG32(CG_SPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
204 RREG32(CG_SPLL_FUNC_CNTL_3); in rv730_read_clock_registers()
206 RREG32(CG_SPLL_SPREAD_SPECTRUM); in rv730_read_clock_registers()
208 RREG32(CG_SPLL_SPREAD_SPECTRUM_2); in rv730_read_clock_registers()
211 RREG32(TCI_MCLK_PWRMGT_CNTL); in rv730_read_clock_registers()
213 RREG32(TCI_DLL_CNTL); in rv730_read_clock_registers()
215 RREG32(CG_MPLL_FUNC_CNTL); in rv730_read_clock_registers()
217 RREG32(CG_MPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
219 RREG32(CG_MPLL_FUNC_CNTL_3); in rv730_read_clock_registers()
[all …]
H A Dr600.c127 r = RREG32(R600_RCU_DATA); in r600_rcu_rreg()
149 r = RREG32(R600_UVD_CTX_DATA); in r600_uvd_ctx_rreg()
183 *val = RREG32(reg); in r600_get_allowed_info_register()
352 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> in rv6xx_get_temp()
797 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) in r600_gui_idle()
811 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
815 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
819 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
823 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
828 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
[all …]
H A Dr100.c80 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) in r100_is_in_vblank()
85 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) in r100_is_in_vblank()
97 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
98 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
100 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
101 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
125 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) in r100_wait_for_vblank()
128 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) in r100_wait_for_vblank()
184 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) in r100_page_flip()
210 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & in r100_page_flip_pending()
[all …]
H A Drs400.c156 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; in rs400_gart_enable()
160 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; in rs400_gart_enable()
247 tmp = RREG32(RADEON_MC_STATUS); in rs400_mc_wait_for_idle()
262 RREG32(RADEON_MC_STATUS)); in rs400_gpu_init()
276 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; in rs400_mc_init()
290 r = RREG32(RS480_NB_MC_DATA); in rs400_mc_rreg()
313 tmp = RREG32(RADEON_HOST_PATH_CNTL); in rs400_debugfs_gart_info_show()
315 tmp = RREG32(RADEON_BUS_CNTL); in rs400_debugfs_gart_info_show()
328 tmp = RREG32(RS690_HDP_FB_LOCATION); in rs400_debugfs_gart_info_show()
331 tmp = RREG32(RADEON_AGP_BASE); in rs400_debugfs_gart_info_show()
[all …]
H A Dcik.c169 *val = RREG32(reg); in cik_get_allowed_info_register()
186 r = RREG32(CIK_DIDT_IND_DATA); in cik_didt_rreg()
244 (void)RREG32(PCIE_INDEX); in cik_pciep_rreg()
245 r = RREG32(PCIE_DATA); in cik_pciep_rreg()
256 (void)RREG32(PCIE_INDEX); in cik_pciep_wreg()
258 (void)RREG32(PCIE_DATA); in cik_pciep_wreg()
1902 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; in ci_mc_load_microcode()
1920 tmp = RREG32(MC_SEQ_MISC0); in ci_mc_load_microcode()
1943 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) in ci_mc_load_microcode()
1948 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1) in ci_mc_load_microcode()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgmc_v8_0.c176 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v8_0_mc_stop()
194 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v8_0_mc_resume()
243 if (RREG32(mmMC_SEQ_IO_DEBUG_DATA) == 0x05b4dc40) in gmc_v8_0_init_microcode()
305 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v8_0_tonga_mc_load_microcode()
328 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
334 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
374 data = RREG32(mmMC_SEQ_MISC0); in gmc_v8_0_polaris_mc_load_microcode()
398 data = RREG32(mmMC_SEQ_MISC0); in gmc_v8_0_polaris_mc_load_microcode()
413 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; in gmc_v8_0_vram_gtt_location()
448 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v8_0_mc_program()
[all …]
H A Dgmc_v7_0.c94 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v7_0_mc_stop()
112 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v7_0_mc_resume()
196 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v7_0_mc_load_microcode()
219 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
225 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
238 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; in gmc_v7_0_vram_gtt_location()
274 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v7_0_mc_program()
279 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v7_0_mc_program()
298 tmp = RREG32(mmHDP_MISC_CNTL); in gmc_v7_0_mc_program()
302 tmp = RREG32(mmHDP_HOST_PATH_CNTL); in gmc_v7_0_mc_program()
[all …]
H A Damdgpu_i2c.c51 temp = RREG32(rec->mask_clk_reg); in amdgpu_i2c_pre_xfer()
57 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; in amdgpu_i2c_pre_xfer()
60 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; in amdgpu_i2c_pre_xfer()
64 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; in amdgpu_i2c_pre_xfer()
67 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; in amdgpu_i2c_pre_xfer()
71 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; in amdgpu_i2c_pre_xfer()
73 temp = RREG32(rec->mask_clk_reg); in amdgpu_i2c_pre_xfer()
75 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; in amdgpu_i2c_pre_xfer()
77 temp = RREG32(rec->mask_data_reg); in amdgpu_i2c_pre_xfer()
90 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; in amdgpu_i2c_post_xfer()
[all …]
H A Dgmc_v6_0.c70 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v6_0_mc_stop()
89 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v6_0_mc_resume()
128 if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58) in gmc_v6_0_init_microcode()
168 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK; in gmc_v6_0_mc_load_microcode()
192 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK) in gmc_v6_0_mc_load_microcode()
197 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK) in gmc_v6_0_mc_load_microcode()
210 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; in gmc_v6_0_vram_gtt_location()
239 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v6_0_mc_program()
244 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v6_0_mc_program()
270 tmp = RREG32(mmMC_ARB_RAMCFG); in gmc_v6_0_mc_init()
[all …]
H A Dvce_v2_0.c60 return RREG32(mmVCE_RB_RPTR); in vce_v2_0_ring_get_rptr()
62 return RREG32(mmVCE_RB_RPTR2); in vce_v2_0_ring_get_rptr()
77 return RREG32(mmVCE_RB_WPTR); in vce_v2_0_ring_get_wptr()
79 return RREG32(mmVCE_RB_WPTR2); in vce_v2_0_ring_get_wptr()
105 uint32_t status = RREG32(mmVCE_LMI_STATUS); in vce_v2_0_lmi_clean()
122 uint32_t status = RREG32(mmVCE_STATUS); in vce_v2_0_firmware_loaded()
151 tmp = RREG32(mmVCE_CLOCK_GATING_A); in vce_v2_0_init_cg()
157 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v2_0_init_cg()
162 tmp = RREG32(mmVCE_CLOCK_GATING_B); in vce_v2_0_init_cg()
208 return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK); in vce_v2_0_is_idle()
[all …]
H A Diceland_ih.c62 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_enable_interrupts()
63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_enable_interrupts()
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_disable_interrupts()
82 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_disable_interrupts()
117 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in iceland_ih_irq_init()
148 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_irq_init()
201 wptr = RREG32(mmIH_RB_WPTR); in iceland_ih_get_wptr()
214 tmp = RREG32(mmIH_RB_CNTL); in iceland_ih_get_wptr()
347 u32 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_is_idle()
363 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_wait_for_idle()
[all …]
H A Dcz_ih.c62 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_enable_interrupts()
63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_enable_interrupts()
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_disable_interrupts()
82 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_disable_interrupts()
117 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in cz_ih_irq_init()
148 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_irq_init()
201 wptr = RREG32(mmIH_RB_WPTR); in cz_ih_get_wptr()
215 tmp = RREG32(mmIH_RB_CNTL); in cz_ih_get_wptr()
353 u32 tmp = RREG32(mmSRBM_STATUS); in cz_ih_is_idle()
369 tmp = RREG32(mmSRBM_STATUS); in cz_ih_wait_for_idle()
[all …]
H A Dcik_ih.c62 u32 ih_cntl = RREG32(mmIH_CNTL); in cik_ih_enable_interrupts()
63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cik_ih_enable_interrupts()
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cik_ih_disable_interrupts()
82 u32 ih_cntl = RREG32(mmIH_CNTL); in cik_ih_disable_interrupts()
117 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in cik_ih_irq_init()
204 tmp = RREG32(mmIH_RB_CNTL); in cik_ih_get_wptr()
357 u32 tmp = RREG32(mmSRBM_STATUS); in cik_ih_is_idle()
373 tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK; in cik_ih_wait_for_idle()
386 u32 tmp = RREG32(mmSRBM_STATUS); in cik_ih_soft_reset()
392 tmp = RREG32(mmSRBM_SOFT_RESET); in cik_ih_soft_reset()
[all …]
H A Dsi_ih.c37 u32 ih_cntl = RREG32(IH_CNTL); in si_ih_enable_interrupts()
38 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_ih_enable_interrupts()
49 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_ih_disable_interrupts()
50 u32 ih_cntl = RREG32(IH_CNTL); in si_ih_disable_interrupts()
71 interrupt_cntl = RREG32(INTERRUPT_CNTL); in si_ih_irq_init()
119 tmp = RREG32(IH_RB_CNTL); in si_ih_get_wptr()
222 u32 tmp = RREG32(SRBM_STATUS); in si_ih_is_idle()
248 u32 tmp = RREG32(SRBM_STATUS); in si_ih_soft_reset()
254 tmp = RREG32(SRBM_SOFT_RESET); in si_ih_soft_reset()
258 tmp = RREG32(SRBM_SOFT_RESET); in si_ih_soft_reset()
[all …]
H A Dvce_v3_0.c90 v = RREG32(mmVCE_RB_RPTR); in vce_v3_0_ring_get_rptr()
92 v = RREG32(mmVCE_RB_RPTR2); in vce_v3_0_ring_get_rptr()
94 v = RREG32(mmVCE_RB_RPTR3); in vce_v3_0_ring_get_rptr()
122 v = RREG32(mmVCE_RB_WPTR); in vce_v3_0_ring_get_wptr()
124 v = RREG32(mmVCE_RB_WPTR2); in vce_v3_0_ring_get_wptr()
126 v = RREG32(mmVCE_RB_WPTR3); in vce_v3_0_ring_get_wptr()
182 data = RREG32(mmVCE_CLOCK_GATING_B); in vce_v3_0_set_vce_sw_clock_gating()
187 data = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v3_0_set_vce_sw_clock_gating()
192 data = RREG32(mmVCE_UENC_CLOCK_GATING_2); in vce_v3_0_set_vce_sw_clock_gating()
197 data = RREG32(mmVCE_UENC_REG_CLOCK_GATING); in vce_v3_0_set_vce_sw_clock_gating()
[all …]
H A Dgfx_v7_0.c1590 data = RREG32(mmCC_RB_BACKEND_DISABLE); in gfx_v7_0_get_rb_active_bitmap()
1591 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); in gfx_v7_0_get_rb_active_bitmap()
1794 RREG32(mmCC_RB_BACKEND_DISABLE); in gfx_v7_0_setup_rb()
1796 RREG32(mmGC_USER_RB_BACKEND_DISABLE); in gfx_v7_0_setup_rb()
1798 RREG32(mmPA_SC_RASTER_CONFIG); in gfx_v7_0_setup_rb()
1800 RREG32(mmPA_SC_RASTER_CONFIG_1); in gfx_v7_0_setup_rb()
1956 tmp = RREG32(mmSPI_CONFIG_CNTL); in gfx_v7_0_constants_init()
1964 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff; in gfx_v7_0_constants_init()
1968 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c; in gfx_v7_0_constants_init()
1972 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000; in gfx_v7_0_constants_init()
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H A Duvd_v3_1.c48 return RREG32(mmUVD_RBC_RB_RPTR); in uvd_v3_1_ring_get_rptr()
62 return RREG32(mmUVD_RBC_RB_WPTR); in uvd_v3_1_ring_get_wptr()
155 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v3_1_ring_test_ring()
213 tmp = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_set_dcm()
291 if (RREG32(mmUVD_FW_STATUS) & UVD_FW_STATUS__DONE_MASK) in uvd_v3_1_fw_validate()
298 if (!(RREG32(mmUVD_FW_STATUS) & UVD_FW_STATUS__PASS_MASK)) in uvd_v3_1_fw_validate()
303 if (!(RREG32(mmUVD_FW_STATUS) & UVD_FW_STATUS__BUSY_MASK)) in uvd_v3_1_fw_validate()
358 tmp = RREG32(mmUVD_MPC_CNTL); in uvd_v3_1_start()
385 status = RREG32(mmUVD_STATUS); in uvd_v3_1_start()
426 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); in uvd_v3_1_start()
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H A Damdgpu_amdkfd_gfx_v7.c107 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid))) in kgd_set_pasid_vmid_mapping()
214 (*dump)[i++][1] = RREG32(addr); \ in kgd_hqd_dump()
255 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); in kgd_hqd_sdma_load()
329 act = RREG32(mmCP_HQD_ACTIVE); in kgd_hqd_is_occupied()
334 if (low == RREG32(mmCP_HQD_PQ_BASE) && in kgd_hqd_is_occupied()
335 high == RREG32(mmCP_HQD_PQ_BASE_HI)) in kgd_hqd_is_occupied()
351 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL); in kgd_hqd_sdma_is_occupied()
397 temp = RREG32(mmCP_HQD_IQ_TIMER); in kgd_hqd_destroy()
426 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); in kgd_hqd_destroy()
445 temp = RREG32(mmCP_HQD_ACTIVE); in kgd_hqd_destroy()
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H A Dtonga_ih.c62 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in tonga_ih_enable_interrupts()
79 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in tonga_ih_disable_interrupts()
113 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in tonga_ih_irq_init()
145 ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR); in tonga_ih_irq_init()
203 wptr = RREG32(mmIH_RB_WPTR); in tonga_ih_get_wptr()
218 tmp = RREG32(mmIH_RB_CNTL); in tonga_ih_get_wptr()
365 u32 tmp = RREG32(mmSRBM_STATUS); in tonga_ih_is_idle()
381 tmp = RREG32(mmSRBM_STATUS); in tonga_ih_wait_for_idle()
393 u32 tmp = RREG32(mmSRBM_STATUS); in tonga_ih_check_soft_reset()
440 tmp = RREG32(mmSRBM_SOFT_RESET); in tonga_ih_soft_reset()
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