269 	bus_cntl = RREG32(R600_BUS_CNTL);  in ni_read_disabled_bios()
270 	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);  in ni_read_disabled_bios()
271 	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);  in ni_read_disabled_bios()
272 	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);  in ni_read_disabled_bios()
273 	rom_cntl = RREG32(R600_ROM_CNTL);  in ni_read_disabled_bios()
315 	viph_control = RREG32(RADEON_VIPH_CONTROL);  in r700_read_disabled_bios()
316 	bus_cntl = RREG32(R600_BUS_CNTL);  in r700_read_disabled_bios()
317 	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);  in r700_read_disabled_bios()
318 	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);  in r700_read_disabled_bios()
319 	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);  in r700_read_disabled_bios()
320 	rom_cntl = RREG32(R600_ROM_CNTL);  in r700_read_disabled_bios()
337 		cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);  in r700_read_disabled_bios()
346 			cg_spll_status = RREG32(R600_CG_SPLL_STATUS);  in r700_read_disabled_bios()
361 			cg_spll_status = RREG32(R600_CG_SPLL_STATUS);  in r700_read_disabled_bios()
388 	viph_control = RREG32(RADEON_VIPH_CONTROL);  in r600_read_disabled_bios()
389 	bus_cntl = RREG32(R600_BUS_CNTL);  in r600_read_disabled_bios()
390 	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);  in r600_read_disabled_bios()
391 	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);  in r600_read_disabled_bios()
392 	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);  in r600_read_disabled_bios()
393 	rom_cntl = RREG32(R600_ROM_CNTL);  in r600_read_disabled_bios()
394 	general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);  in r600_read_disabled_bios()
395 	low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);  in r600_read_disabled_bios()
396 	medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);  in r600_read_disabled_bios()
397 	high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);  in r600_read_disabled_bios()
398 	ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);  in r600_read_disabled_bios()
399 	lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);  in r600_read_disabled_bios()
462 	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);  in avivo_read_disabled_bios()
463 	viph_control = RREG32(RADEON_VIPH_CONTROL);  in avivo_read_disabled_bios()
464 	bus_cntl = RREG32(RV370_BUS_CNTL);  in avivo_read_disabled_bios()
465 	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);  in avivo_read_disabled_bios()
466 	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);  in avivo_read_disabled_bios()
467 	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);  in avivo_read_disabled_bios()
468 	gpiopad_a = RREG32(RADEON_GPIOPAD_A);  in avivo_read_disabled_bios()
469 	gpiopad_en = RREG32(RADEON_GPIOPAD_EN);  in avivo_read_disabled_bios()
470 	gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);  in avivo_read_disabled_bios()
521 	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);  in legacy_read_disabled_bios()
522 	viph_control = RREG32(RADEON_VIPH_CONTROL);  in legacy_read_disabled_bios()
524 		bus_cntl = RREG32(RV370_BUS_CNTL);  in legacy_read_disabled_bios()
526 		bus_cntl = RREG32(RADEON_BUS_CNTL);  in legacy_read_disabled_bios()
527 	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);  in legacy_read_disabled_bios()
529 	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);  in legacy_read_disabled_bios()
533 		fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);  in legacy_read_disabled_bios()
537 		crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);  in legacy_read_disabled_bios()