94 	blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);  in gmc_v7_0_mc_stop()
112 	tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);  in gmc_v7_0_mc_resume()
196 	running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);  in gmc_v7_0_mc_load_microcode()
219 			if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),  in gmc_v7_0_mc_load_microcode()
225 			if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),  in gmc_v7_0_mc_load_microcode()
238 	u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;  in gmc_v7_0_vram_gtt_location()
274 		tmp = RREG32(mmVGA_HDP_CONTROL);  in gmc_v7_0_mc_program()
279 		tmp = RREG32(mmVGA_RENDER_CONTROL);  in gmc_v7_0_mc_program()
298 	tmp = RREG32(mmHDP_MISC_CNTL);  in gmc_v7_0_mc_program()
302 	tmp = RREG32(mmHDP_HOST_PATH_CNTL);  in gmc_v7_0_mc_program()
325 		tmp = RREG32(mmMC_ARB_RAMCFG);  in gmc_v7_0_mc_init()
331 		tmp = RREG32(mmMC_SHARED_CHMAP);  in gmc_v7_0_mc_init()
365 	adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;  in gmc_v7_0_mc_init()
366 	adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;  in gmc_v7_0_mc_init()
380 		adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;  in gmc_v7_0_mc_init()
437 		tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);  in gmc_v7_0_flush_gpu_tlb_pasid()
441 			RREG32(mmVM_INVALIDATE_RESPONSE);  in gmc_v7_0_flush_gpu_tlb_pasid()
521 	tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_set_fault_enable_default()
552 	tmp = RREG32(mmVM_PRT_CNTL);  in gmc_v7_0_set_prt()
619 	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);  in gmc_v7_0_gart_enable()
627 	tmp = RREG32(mmVM_L2_CNTL);  in gmc_v7_0_gart_enable()
641 	tmp = RREG32(mmVM_L2_CNTL3);  in gmc_v7_0_gart_enable()
653 	tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v7_0_gart_enable()
683 	tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_gart_enable()
695 		tmp = RREG32(mmCHUB_CONTROL);  in gmc_v7_0_gart_enable()
739 	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);  in gmc_v7_0_gart_disable()
745 	tmp = RREG32(mmVM_L2_CNTL);  in gmc_v7_0_gart_disable()
826 		orig = data = RREG32(mc_cg_registers[i]);  in gmc_v7_0_enable_mc_ls()
843 		orig = data = RREG32(mc_cg_registers[i]);  in gmc_v7_0_enable_mc_mgcg()
881 	orig = data = RREG32(mmHDP_HOST_PATH_CNTL);  in gmc_v7_0_enable_hdp_mgcg()
897 	orig = data = RREG32(mmHDP_MEM_POWER_LS);  in gmc_v7_0_enable_hdp_ls()
961 	u32 d1vga_control = RREG32(mmD1VGA_CONTROL);  in gmc_v7_0_get_vbios_fb_size()
967 		u32 viewport = RREG32(mmVIEWPORT_SIZE);  in gmc_v7_0_get_vbios_fb_size()
987 		u32 tmp = RREG32(mmMC_SEQ_MISC0);  in gmc_v7_0_sw_init()
1052 		u64 tmp = RREG32(mmMC_VM_FB_OFFSET);  in gmc_v7_0_sw_init()
1146 	u32 tmp = RREG32(mmSRBM_STATUS);  in gmc_v7_0_is_idle()
1163 		tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |  in gmc_v7_0_wait_for_idle()
1180 	u32 tmp = RREG32(mmSRBM_STATUS);  in gmc_v7_0_soft_reset()
1198 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v7_0_soft_reset()
1202 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v7_0_soft_reset()
1208 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v7_0_soft_reset()
1236 		tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1240 		tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1246 		tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1250 		tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1267 	addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);  in gmc_v7_0_process_interrupt()
1268 	status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);  in gmc_v7_0_process_interrupt()
1269 	mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);  in gmc_v7_0_process_interrupt()