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Searched refs:PPI (Results 1 – 25 of 26) sorted by relevance

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/openbmc/qemu/disas/
H A Dsh4.c66 PPI, enumerator
855 /* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up},
856 /* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up},
927 {"dct",{0},{PPI,PDC,HEX_1}, arch_sh_dsp_up},
928 {"dcf",{0},{PPI,PDC,HEX_2}, arch_sh_dsp_up},
957 {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up},
971 {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up},
973 {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up},
975 {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up},
977 {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up},
[all …]
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-driver-ppi6 This folder includes the attributes related with PPI (Physical
9 'find /sys/ -name 'pcrs''. For the detail information of PPI,
10 please refer to the PPI specification from
22 This attribute shows the version of the PPI supported by the
63 This attribute is only supported by PPI version 1.2+.
74 is also only supported by PPI version 1.2+.
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic-v3.yaml14 Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
43 If the system requires describing PPI affinity, then the value must
46 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
48 Extended PPI range. Other values are reserved for future use.
51 SPI interrupts are in the range [0-987]. PPI interrupts are in the
53 Extended PPI interrupts are in the range [0-127].
61 interrupt is affine to. The interrupt must be a PPI, and the node
63 interrupt types other than PPI or PPIs that are not partitionned,
144 PPI affinity can be expressed as a single "ppi-partitions" node,
H A Darm,gic.yaml14 interrupts (PPI), shared processor interrupts (SPI) and software
74 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
78 SPI interrupts are in the range [0-987]. PPI interrupts are in the
87 bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
89 the interrupt is wired to that CPU. Only valid for PPI interrupts.
90 Also note that the configurability of PPI interrupts is IMPLEMENTATION
/openbmc/u-boot/arch/arm/dts/
H A Dfsl-lx2160a.dtsi46 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
47 <1 14 0x8>, /* Physical NS PPI, active-low */
48 <1 11 0x8>, /* Virtual PPI, active-low */
49 <1 10 0x8>; /* Hypervisor PPI, active-low */
H A Dfsl-ls1088a.dtsi31 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
32 <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
33 <1 11 0x8>, /* Virtual PPI, active-low */
34 <1 10 0x8>; /* Hypervisor PPI, active-low */
H A Dfsl-ls2080a.dtsi31 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
32 <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
33 <1 11 0x8>, /* Virtual PPI, active-low */
34 <1 10 0x8>; /* Hypervisor PPI, active-low */
/openbmc/linux/Documentation/devicetree/bindings/perf/
H A Dspe-pmu.yaml23 The PPI to signal SPE events. For heterogeneous systems where SPE is only
25 for details on describing a PPI partition.
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,trace-buffer-extension.yaml30 Exactly 1 PPI must be listed. For heterogeneous systems where
32 the arm,gic-v3 binding for details on describing a PPI partition.
H A Dpmu.yaml74 description: 1 per-cpu interrupt (PPI) or 1 interrupt per core.
85 When using a PPI, specifies a list of phandles to CPU
87 a PMU of this type signalling the PPI listed in the
89 by the PPI interrupt specifier itself (in which case
/openbmc/qemu/docs/specs/
H A Dtpm.rst77 uint32_t tpmppi_address; /* PPI memory location */
79 uint8_t tpmppi_version; /* PPI version */
104 ACPI PPI Interface
107 QEMU supports the Physical Presence Interface (PPI) for TPM 1.2 and
109 `PPI specification`_)
111 PPI enables a system administrator (root) to request a modification to
112 the TPM upon reboot. The PPI specification defines the operation
121 The PPI specification defines a set of mandatory and optional
127 device for PPI where the firmware can indicate which operations it
187 field. The PPI memory region size is 0x400 (``TPM_PPI_ADDR_SIZE``) to
/openbmc/linux/arch/arm64/boot/dts/sprd/
H A Dsc9863a.dtsi130 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */
131 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
132 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */
133 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
H A Dums512.dtsi133 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */
134 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
135 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */
136 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
/openbmc/linux/Documentation/virt/kvm/devices/
H A Dvcpu.rst38 number for this vcpu. This interrupt could be a PPI or SPI, but the interrupt
39 type must be same for each vcpu. As a PPI, the interrupt number is the same for
159 in-kernel virtual GIC. These must be a PPI (16 <= intid < 32). Setting the
167 Setting the same PPI for different timers will prevent the VCPUs from running.
H A Darm-vgic.rst131 A value describing the number of interrupts (SGI, PPI and SPI) for
H A Darm-vgic-v3.rst213 A value describing the number of interrupts (SGI, PPI and SPI) for
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1012a.dtsi77 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
78 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
79 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
80 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
H A Dfsl-ls208xa.dtsi244 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
245 <1 14 4>, /* Physical Non-Secure PPI, active-low */
246 <1 11 4>, /* Virtual PPI, active-low */
247 <1 10 4>; /* Hypervisor PPI, active-low */
252 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
H A Dfsl-ls1088a.dtsi186 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
187 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
188 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
189 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
H A Dfsl-ls1043a.dtsi271 interrupts = <1 13 0xf08>, /* Physical Secure PPI */
272 <1 14 0xf08>, /* Physical Non-Secure PPI */
273 <1 11 0xf08>, /* Virtual PPI */
274 <1 10 0xf08>; /* Hypervisor PPI */
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/
H A D0003-Silicon-ARM-NeoverseN1Soc-Enable-SCP-QSPI-flash-regi.patch43 /** A helper function to locate the NtFwConfig PPI and get the base address of
H A D0001-Platform-ARM-N1sdp-Add-support-to-parse-NT_FW_CONFIG.patch332 +/** A helper function to locate the NtFwConfig PPI and get the base address of
/openbmc/linux/Documentation/devicetree/bindings/display/bridge/
H A Drenesas,dsi.yaml38 - description: DSI D-PHY PPI interrupt
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap5.dtsi95 /* PPI secure/nonsecure IRQ */
/openbmc/linux/drivers/gpio/
H A DKconfig858 Peripheral Interface (PPI). The Intel 8255 PPI chip was first released
927 via the emulation of dual 82C55A PPI chips. This driver provides GPIO

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