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Searched refs:PPC_BITMASK (Results 1 – 25 of 29) sorted by relevance

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/openbmc/qemu/hw/intc/
H A Dpnv_xive2_regs.h20 #define CQ_XIVE_CAP_VERSION PPC_BITMASK(0, 3)
22 #define CQ_XIVE_CAP_USER_INT_PRIO PPC_BITMASK(8, 9)
27 #define CQ_XIVE_CAP_VP_INT_PRIO PPC_BITMASK(10, 11)
32 #define CQ_XIVE_CAP_BLOCK_ID_WIDTH PPC_BITMASK(12, 13)
45 #define CQ_XIVE_CFG_USER_INT_PRIO PPC_BITMASK(8, 9)
46 #define CQ_XIVE_CFG_VP_INT_PRIO PPC_BITMASK(10, 11)
51 #define CQ_XIVE_CFG_BLOCK_ID_WIDTH PPC_BITMASK(12, 13)
56 #define CQ_XIVE_CFG_HYP_HARD_RANGE PPC_BITMASK(14, 15)
546 #define VSD_MODE PPC_BITMASK(0, 1)
554 #define VSD_MIGRATION_REG PPC_BITMASK(52, 55)
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H A Dpnv_xive_regs.h21 #define CQ_INT_ADDR_OPT PPC_BITMASK(14, 15)
34 #define CQ_PC_BARM_MASK PPC_BITMASK(26, 38)
38 #define CQ_VC_BARM_MASK PPC_BITMASK(21, 37)
41 #define CQ_TAR_TSEL PPC_BITMASK(12, 15)
46 #define CQ_TAR_TSEL_INDEX PPC_BITMASK(26, 31)
49 #define CQ_TDR_VDT_BLK PPC_BITMASK(11, 15)
50 #define CQ_TDR_VDT_INDEX PPC_BITMASK(28, 31)
51 #define CQ_TDR_EDT_TYPE PPC_BITMASK(0, 1)
55 #define CQ_TDR_EDT_BLK PPC_BITMASK(12, 15)
56 #define CQ_TDR_EDT_INDEX PPC_BITMASK(26, 31)
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/openbmc/qemu/include/hw/pci-host/
H A Dpnv_phb3_regs.h20 #define PBCQ_NEST_IRSN_COMP PPC_BITMASK(0, 18)
23 #define PBCQ_NEST_LSI_SRC PPC_BITMASK(0, 7)
53 #define PHB_LSI_SRC_ID PPC_BITMASK(5, 12)
64 #define PHB_DMAMSI_NID PPC_BITMASK(24, 31)
69 #define PHB_CA_BUS PPC_BITMASK(4, 11)
70 #define PHB_CA_DEV PPC_BITMASK(12, 16)
71 #define PHB_CA_FUNC PPC_BITMASK(17, 19)
72 #define PHB_CA_REG PPC_BITMASK(20, 31)
73 #define PHB_CA_PE PPC_BITMASK(40, 47)
77 #define PHB_IVT_BASE_ADDRESS_MASK PPC_BITMASK(14, 48)
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H A Dpnv_phb4_regs.h138 #define PHB_LSI_SRC_ID PPC_BITMASK(4, 12)
151 #define PHB_CA_STATUS PPC_BITMASK(1, 3)
156 #define PHB_CA_BUS PPC_BITMASK(4, 11)
157 #define PHB_CA_DEV PPC_BITMASK(12, 16)
158 #define PHB_CA_FUNC PPC_BITMASK(17, 19)
160 #define PHB_CA_REG PPC_BITMASK(20, 31)
161 #define PHB_CA_PE PPC_BITMASK(39, 47)
168 #define PHB_RTT_BASE_ADDRESS_MASK PPC_BITMASK(8, 46)
171 #define PHB_PELTV_BASE_ADDRESS PPC_BITMASK(8, 50)
175 #define PHB_PEST_BASE_ADDRESS PPC_BITMASK(8, 51)
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/openbmc/linux/arch/powerpc/platforms/powernv/
H A Dvas.h115 #define VAS_LPID PPC_BITMASK(0, 11)
118 #define VAS_PID_ID PPC_BITMASK(0, 19)
135 #define VAS_XLATE_MODE PPC_BITMASK(0, 1)
138 #define VAS_AMR PPC_BITMASK(0, 63)
141 #define VAS_SEIDR PPC_BITMASK(0, 63)
163 #define VAS_LFIFO_BAR PPC_BITMASK(8, 53)
171 #define VAS_LDMA_TYPE PPC_BITMASK(0, 1)
184 #define VAS_LRX_WCRED PPC_BITMASK(0, 15)
190 #define VAS_TX_WCRED PPC_BITMASK(4, 15)
196 #define VAS_LFIFO_SIZE PPC_BITMASK(0, 3)
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/openbmc/qemu/include/hw/i2c/
H A Dpnv_i2c_regs.h14 #define I2C_FIFO PPC_BITMASK(0, 7)
25 #define I2C_CMD_DEV_ADDR PPC_BITMASK(8, 14)
27 #define I2C_CMD_LEN_BYTES PPC_BITMASK(16, 31)
32 #define I2C_MODE_BIT_RATE_DIV PPC_BITMASK(0, 15)
33 #define I2C_MODE_PORT_NUM PPC_BITMASK(16, 21)
41 #define I2C_WATERMARK_HIGH PPC_BITMASK(16, 19)
42 #define I2C_WATERMARK_LOW PPC_BITMASK(24, 27)
61 #define I2C_INTR_ALL PPC_BITMASK(16, 31)
91 #define I2C_STAT_UPPER_THRS PPC_BITMASK(9, 15)
114 #define I2C_EXTD_STAT_FIFO_SIZE PPC_BITMASK(0, 7)
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/openbmc/qemu/include/hw/ssi/
H A Dpnv_spi_regs.h31 #define SPI_CTR_CFG_N1 PPC_BITMASK(0, 7)
32 #define SPI_CTR_CFG_N2 PPC_BITMASK(8, 15)
33 #define SPI_CTR_CFG_CMP1 PPC_BITMASK(24, 31)
34 #define SPI_CTR_CFG_CMP2 PPC_BITMASK(32, 39)
49 #define SPI_CLK_CFG_RST_CTRL PPC_BITMASK(24, 27)
51 #define SPI_CLK_CFG_ECC_CTRL PPC_BITMASK(29, 30)
55 #define SPI_MM_RDR_MATCH_VAL PPC_BITMASK(32, 47)
56 #define SPI_MM_RDR_MATCH_MASK PPC_BITMASK(48, 63)
75 #define SPI_STS_SEQ_FSM PPC_BITMASK(8, 15)
79 #define SPI_STS_RDR PPC_BITMASK(1, 3)
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/openbmc/linux/arch/powerpc/include/asm/
H A Dpnv-ocxl.h25 #define PNV_OCXL_ATSD_LNCH_RIC PPC_BITMASK(1, 2)
27 #define PNV_OCXL_ATSD_LNCH_LP PPC_BITMASK(3, 10)
32 #define PNV_OCXL_ATSD_LNCH_IS PPC_BITMASK(11, 12)
43 #define PNV_OCXL_ATSD_LNCH_AP PPC_BITMASK(15, 17)
50 #define PNV_OCXL_ATSD_LNCH_PID PPC_BITMASK(19, 38)
56 #define PNV_OCXL_ATSD_AVA_AVA PPC_BITMASK(0, 51)
H A Dbitops.h48 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) macro
/openbmc/qemu/hw/pci-host/
H A Dpnv_phb4_pec.c49 pec->nest_regs[reg] = val & PPC_BITMASK(0, 25); in pnv_pec_nest_xscom_write()
52 pec->nest_regs[reg] = val & PPC_BITMASK(0, 11); in pnv_pec_nest_xscom_write()
55 pec->nest_regs[reg] = val & PPC_BITMASK(0, 16); in pnv_pec_nest_xscom_write()
58 pec->nest_regs[reg] = val & PPC_BITMASK(0, 37); in pnv_pec_nest_xscom_write()
61 pec->nest_regs[reg] = val & PPC_BITMASK(0, 6); in pnv_pec_nest_xscom_write()
64 pec->nest_regs[reg] = val & PPC_BITMASK(0, 15); in pnv_pec_nest_xscom_write()
67 pec->nest_regs[reg] = val & PPC_BITMASK(0, 48); in pnv_pec_nest_xscom_write()
71 pec->nest_regs[reg] = val & PPC_BITMASK(0, 24); in pnv_pec_nest_xscom_write()
74 pec->nest_regs[reg] = val & PPC_BITMASK(0, 41); in pnv_pec_nest_xscom_write()
114 pec->pci_regs[reg] = val & PPC_BITMASK(0, 42); in pnv_pec_pci_xscom_write()
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H A Dpnv_phb4.c1022 phb->nest_regs[reg] = val & PPC_BITMASK(0, 27); in pnv_pec_stk_nest_xscom_write()
1033 phb->nest_regs[reg] = val & PPC_BITMASK(0, 7); in pnv_pec_stk_nest_xscom_write()
1059 phb->nest_regs[reg] = val & PPC_BITMASK(0, 3); in pnv_pec_stk_nest_xscom_write()
1067 phb->nest_regs[reg] = val & PPC_BITMASK(3, 5); in pnv_pec_stk_nest_xscom_write()
1070 phb->nest_regs[reg] = val & PPC_BITMASK(0, 7); in pnv_pec_stk_nest_xscom_write()
1105 phb->pci_regs[reg] = val & PPC_BITMASK(0, 5); in pnv_pec_stk_pci_xscom_write()
1114 phb->pci_regs[reg] = val & PPC_BITMASK(0, 5); in pnv_pec_stk_pci_xscom_write()
1124 phb->pci_regs[reg] = val & PPC_BITMASK(0, 5); in pnv_pec_stk_pci_xscom_write()
1137 ((PPC_BITMASK(0, 2) | PPC_BITMASK(10, 18) in pnv_pec_stk_pci_xscom_write()
1138 | PPC_BITMASK(26, 34) | PPC_BITMASK(41, 50) in pnv_pec_stk_pci_xscom_write()
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/openbmc/qemu/target/ppc/
H A Dcpu.c114 ciea = ciabr & PPC_BITMASK(0, 61); in ppc_update_ciabr()
115 priv = ciabr & PPC_BITMASK(62, 63); in ppc_update_ciabr()
136 target_ulong deaw = env->spr[SPR_DAWR0] & PPC_BITMASK(0, 60); in ppc_update_daw0()
H A Dcpu.h46 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) macro
532 #define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */
553 #define MMCRA_IFM_MASK PPC_BITMASK(32, 33) /* BHRB Instruction Filtering */
581 #define BESCR_INVALID PPC_BITMASK(32, 33)
1167 #define DBELL_BRDCAST_MASK PPC_BITMASK(37, 38)
1176 #define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63)
2700 HMER_XSCOM_STATUS_MASK = PPC_BITMASK(21, 23),
2705 TFMR_CONTROL_MASK = PPC_BITMASK(0, 24),
2711 TFMR_STATUS_MASK = PPC_BITMASK(25, 63),
2712 TFMR_TBST_ENCODED = PPC_BITMASK(28, 31), /* TBST = TB State */
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H A Dmmu-hash64.h63 #define PATE0_PS PPC_BITMASK(56, 58)
H A Dmmu_helper.c416 #define TLBIE_RB_EPN_MASK PPC_BITMASK(0, 51)
417 #define TLBIE_RB_IS_MASK PPC_BITMASK(52, 53)
418 #define TLBIE_RB_AP_MASK PPC_BITMASK(56, 58)
/openbmc/qemu/include/hw/ppc/
H A Dxive2_regs.h42 #define EAS2_END_BLOCK PPC_BITMASK(4, 7) /* Destination EQ block# */
43 #define EAS2_END_INDEX PPC_BITMASK(8, 31) /* Destination EQ index */
45 #define EAS2_END_DATA PPC_BITMASK(33, 63) /* written to the EQ */
H A Dxive_regs.h161 #define EAS_END_BLOCK PPC_BITMASK(4, 7) /* Destination END block# */
162 #define EAS_END_INDEX PPC_BITMASK(8, 31) /* Destination END index */
164 #define EAS_END_DATA PPC_BITMASK(33, 63) /* Data written to the END */
/openbmc/qemu/hw/ppc/
H A Dpnv_adu.c85 return (adu->lpc_cmd_reg & PPC_BITMASK(32, 63)) >> PPC_BIT_NR(63); in lpc_cmd_addr()
90 return (adu->lpc_cmd_reg & PPC_BITMASK(5, 11)) >> PPC_BIT_NR(11); in lpc_cmd_size()
H A Dpnv_chiptod.c76 #define TOD_TX_TTYPE_PIB_SLAVE_ADDR PPC_BITMASK(26, 31)
118 val |= PPC_BITMASK(6, 10); /* STEP checker validity */ in pnv_chiptod_xscom_read()
304 chiptod->pss_mss_ctrl_reg = val & PPC_BITMASK(0, 31); in pnv_chiptod_xscom_write()
H A Dpnv_sbe.c73 #define SBE_HOST_RESPONSE_MASK (PPC_BITMASK(0, 4) | \
H A Dpnv_lpc.c257 #define ECCB_CTL_SZ_MASK PPC_BITMASK(4, 7)
258 #define ECCB_CTL_ADDR_MASK PPC_BITMASK(32, 63)
H A Dpnv_psi.c597 #define PSIHB9_ESB_CI_ADDR_MASK PPC_BITMASK(8, 47)
600 #define PSIHB9_ESB_NOTIF_ADDR_MASK PPC_BITMASK(8, 60)
/openbmc/linux/arch/powerpc/mm/book3s64/
H A Dradix_tlb.c163 rb = va & ~(PPC_BITMASK(52, 63)); in __tlbiel_va()
179 rb = va & ~(PPC_BITMASK(52, 63)); in __tlbie_va()
195 rb = va & ~(PPC_BITMASK(52, 63)); in __tlbie_lpid_va()
1409 rs = (pid << PPC_BITLSHIFT(31)) | (lpid & ~(PPC_BITMASK(0, 31))); in __tlbie_pid_lpid()
1424 rb = va & ~(PPC_BITMASK(52, 63)); in __tlbie_va_lpid()
1426 rs = (pid << PPC_BITLSHIFT(31)) | (lpid & ~(PPC_BITMASK(0, 31))); in __tlbie_va_lpid()
/openbmc/linux/drivers/misc/cxl/
H A Dcxl.h304 #define CXL_SLBIE_SS PPC_BITMASK(37, 38) /* Segment Size */
308 #define CXL_SLBIE_MAX PPC_BITMASK(24, 31)
309 #define CXL_SLBIE_PENDING PPC_BITMASK(56, 63)
/openbmc/qemu/tests/qtest/
H A Dpnv-host-i2c-test.c18 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) macro

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