| /openbmc/linux/arch/sh/kernel/cpu/sh4/ |
| H A D | perf_event.c | 17 #define PMCR(n) (PM_CR_BASE + ((n) * 0x04)) macro
212 tmp = __raw_readw(PMCR(idx)); in sh7750_pmu_disable()
214 __raw_writew(tmp, PMCR(idx)); in sh7750_pmu_disable()
219 __raw_writew(__raw_readw(PMCR(idx)) | PMCR_PMCLR, PMCR(idx)); in sh7750_pmu_enable()
220 __raw_writew(hwc->config | PMCR_PMEN | PMCR_PMST, PMCR(idx)); in sh7750_pmu_enable()
228 __raw_writew(__raw_readw(PMCR(i)) & ~PMCR_PMEN, PMCR(i)); in sh7750_pmu_disable_all()
236 __raw_writew(__raw_readw(PMCR(i)) | PMCR_PMEN, PMCR(i)); in sh7750_pmu_enable_all()
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| /openbmc/u-boot/board/renesas/ecovec/ |
| H A D | ecovec.c | 75 outw(inw(PMCR) & ~0x0C, PMCR); in board_init()
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| /openbmc/linux/arch/arm/include/asm/ |
| H A D | arm_pmuv3.h | 14 #define PMCR __ACCESS_CP15(c9, 0, c12, 0) macro
132 write_sysreg(val, PMCR); in write_pmcr()
137 return read_sysreg(PMCR); in read_pmcr()
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| /openbmc/u-boot/board/renesas/sh7763rdp/ |
| H A D | sh7763rdp.c | 23 #define PMCR 0xffef0018 macro
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| /openbmc/linux/arch/arm/mach-sa1100/ |
| H A D | sleep.S | 110 ldr r12, =PMCR
139 @ Step 6 set force sleep bit in PMCR
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| H A D | generic.c | 91 PMCR = PMCR_SF; in sa1100_power_off()
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| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/pxaregs/pxaregs-1.14/ |
| H A D | serial.patch | 14 { "PMCR", 0x40F00000, 0, 0xffffffff, 'x', "Power Manager Control Register (3-23)" },
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| /openbmc/u-boot/board/mpr2/ |
| H A D | mpr2.c | 108 __raw_writew(0x5552, PMCR); /* 01 01 01 01 01 01 00 10 */ in board_init()
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| /openbmc/linux/arch/arm/mach-pxa/ |
| H A D | pxa3xx-regs.h | 26 #define PMCR __REG(0x40F50000) /* Power Manager Control Register */ macro
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| H A D | pxa2xx-regs.h | 20 #define PMCR __REG(0x40F00000) /* Power Manager Control Register */ macro
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| H A D | spitz.c | 993 PMCR = 0x00; in spitz_init()
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| /openbmc/u-boot/arch/sh/include/asm/ |
| H A D | cpu_sh7723.h | 133 #define PMCR 0xA4050116 macro
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| H A D | cpu_sh7724.h | 154 #define PMCR 0xA4050116 macro
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| H A D | cpu_sh7720.h | 171 #define PMCR (PFC_BASE + 0x16) macro
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| H A D | cpu_sh7780.h | 410 #define PMCR 0xFFEA0016 macro
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| H A D | cpu_sh7722.h | 1204 #define PMCR 0xA4050116 macro
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| /openbmc/u-boot/board/renesas/ap325rxa/ |
| H A D | ap325rxa.c | 108 outw(PMCR_D, PMCR); in board_init()
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| /openbmc/u-boot/include/faraday/ |
| H A D | ftpmu010.h | 19 unsigned int PMCR; /* 0x10 */ member
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| /openbmc/linux/drivers/perf/arm_cspmu/ |
| H A D | arm_cspmu.c | 57 #define PMCR 0xE04 macro
515 writel(pmcr, cspmu->base0 + PMCR); in arm_cspmu_reset_counters()
520 writel(PMCR_E, cspmu->base0 + PMCR); in arm_cspmu_start_counters()
525 writel(0, cspmu->base0 + PMCR); in arm_cspmu_stop_counters()
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| /openbmc/u-boot/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 1915 #define PMCR 0x40F50000 /* Power Manager Control Register */ macro
1971 #define PMCR 0x40F00000 /* Power Manager Control Register */ macro
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| /openbmc/qemu/hw/arm/ |
| H A D | pxa2xx.c | 86 #define PMCR 0x00 /* Power Manager Control register */ macro
114 case PMCR ... PCMD31: in pxa2xx_pm_read()
135 case PMCR: in pxa2xx_pm_write()
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| /openbmc/u-boot/include/ |
| H A D | SA-1100.h | 1238 #define PMCR /* PM Control Reg. */ \ macro
1256 #define PMCR (io_p2v (_PMCR)) macro
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| /openbmc/linux/arch/arm/mach-sa1100/include/mach/ |
| H A D | SA-1100.h | 884 #define PMCR __REG(0x90020000) /* PM Control Reg. */ macro
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