Searched refs:PDC (Results 1 – 25 of 32) sorted by relevance
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7 title: PDC interrupt controller14 Power Domain Controller (PDC) that is on always-on domain. In addition to20 controller PDC is next in hierarchy, followed by others. Drivers requiring21 wakeup capabilities of their device interrupts routed through the PDC, must22 specify PDC as their interrupt controller and request the PDC port associated48 - description: PDC base register region62 - description: starting PDC port63 - description: GIC hwirq number for the PDC port66 Specifies the PDC pin offset and the number of PDC ports.67 The tuples indicates the valid mapping of valid PDC ports
1 * ImgTec Powerdown Controller (PDC) Interrupt Controller Binding4 representation of a PDC IRQ controller. This has a number of input interrupt13 - reg: Specifies the base PDC physical address(s) and size(s) of the27 shared SysWake interrupt, and remaining specifies shall be PDC peripheral52 * TZ1090 PDC block82 * An SoC peripheral that is wired through the PDC.
1 The PDC driver manages data transfer to and from various offload engines2 on some Broadcom SoCs. An SoC may have multiple PDC hardware blocks. There is3 one device tree entry per block. On some chips, the PDC functionality is9 - reg: Should contain PDC registers location and length.10 - interrupts: Should contain the IRQ line for the PDC.20 reg = <0 0x612c0000 0 0x445>; /* PDC FS0 regs */
94 - description: GMU PDC registers95 - description: GMU PDC sequence registers127 - description: GMU PDC registers163 - description: GMU PDC registers164 - description: GMU PDC sequence registers183 - description: GMU PDC registers184 - description: GMU PDC sequence registers
7 title: Qualcomm PDC Global13 The bindings describes the reset-controller found on PDC-Global (Power Domain
71 description: use of PDC or DMA for receiving data75 description: use of PDC or DMA for transmitting data132 /* use PDC */
116 bool "PDC chassis state codes support"134 bool "PDC chassis warnings support"148 tristate "PDC Stable Storage support"153 variables (PDC non volatile variables such as Primary Boot Path,
1 *ImgTec PowerDown Controller (PDC) Watchdog Timer (WDT)
31 - PDC transfer:
219 reg = <0x612c0000 0x445>; /* PDC FS0 regs */235 reg = <0x612e0000 0x445>; /* PDC FS1 regs */251 reg = <0x61300000 0x445>; /* PDC FS2 regs */267 reg = <0x61320000 0x445>; /* PDC FS3 regs */
25 tristate "SoC PCM DAI support for AT91 SSC controller using PDC"31 in PDC mode configured using audio-graph-card in device-tree.
177 tristate "Qualcomm PDC Reset Driver"180 This enables the PDC (Power Domain Controller) reset driver182 to control reset signals provided by PDC for Modem, Compute,
68 - description: PDC AUDIO SYNC RESET
71 - description: PDC SYNC
64 - description: PDC AUDIO SYNC RESET
87 - description: PDC reset
86 - description: PDC reset (only valid for qcom,sdm845-mss-pil)
295 short PDC, PDCA; member
3007 if(ivideo->SiS_Pr.PDC == -1) { in sisfb_save_pdc_emi()3009 ivideo->SiS_Pr.PDC = ivideo->detectedpdc; in sisfb_save_pdc_emi()3014 if((ivideo->SiS_Pr.PDC != -1) && in sisfb_save_pdc_emi()3015 (ivideo->SiS_Pr.PDC != ivideo->detectedpdc)) { in sisfb_save_pdc_emi()3017 ivideo->SiS_Pr.PDC); in sisfb_save_pdc_emi()3058 if(ivideo->SiS_Pr.PDC == -1) { in sisfb_save_pdc_emi()3060 ivideo->SiS_Pr.PDC = ivideo->detectedpdc; in sisfb_save_pdc_emi()3095 if((ivideo->SiS_Pr.PDC != -1) && in sisfb_save_pdc_emi()3098 ivideo->SiS_Pr.PDC); in sisfb_save_pdc_emi()5979 ivideo->SiS_Pr.PDC = -1; in sisfb_probe()[all …]
149 { PCI_VDEVICE(PDC, 0x2068), board_2068_idx },
160 { PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
34 :title: ETS 300 231 "Specification of the domestic video Programme Delivery Control system (PDC…
87 ;* for RDR10 which has bits that preclude PDC stack operations
77 PDC, enumerator927 {"dct",{0},{PPI,PDC,HEX_1}, arch_sh_dsp_up},928 {"dcf",{0},{PPI,PDC,HEX_2}, arch_sh_dsp_up},