1b04f1272SRob RiceThe PDC driver manages data transfer to and from various offload engines 2b04f1272SRob Riceon some Broadcom SoCs. An SoC may have multiple PDC hardware blocks. There is 352e2daddSSteve Linone device tree entry per block. On some chips, the PDC functionality is 452e2daddSSteve Linhandled by the FA2 (Northstar Plus). 5b04f1272SRob Rice 6b04f1272SRob RiceRequired properties: 752e2daddSSteve Lin- compatible : Should be "brcm,iproc-pdc-mbox" or "brcm,iproc-fa2-mbox" for 852e2daddSSteve Lin FA2/Northstar Plus. 9b04f1272SRob Rice- reg: Should contain PDC registers location and length. 10b04f1272SRob Rice- interrupts: Should contain the IRQ line for the PDC. 11b04f1272SRob Rice- #mbox-cells: 1 12b04f1272SRob Rice- brcm,rx-status-len: Length of metadata preceding received frames, in bytes. 13b04f1272SRob Rice 14b04f1272SRob RiceOptional properties: 15b04f1272SRob Rice- brcm,use-bcm-hdr: present if a BCM header precedes each frame. 16b04f1272SRob Rice 17b04f1272SRob RiceExample: 184c9847b7SMathieu Malaterre pdc0: iproc-pdc0@612c0000 { 19b04f1272SRob Rice compatible = "brcm,iproc-pdc-mbox"; 20b04f1272SRob Rice reg = <0 0x612c0000 0 0x445>; /* PDC FS0 regs */ 21b04f1272SRob Rice interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 22b04f1272SRob Rice #mbox-cells = <1>; /* one cell per mailbox channel */ 23b04f1272SRob Rice brcm,rx-status-len = <32>; 24b04f1272SRob Rice brcm,use-bcm-hdr; 25b04f1272SRob Rice }; 26