Searched refs:PCDR (Results 1 – 18 of 18) sorted by relevance
72 return get_systemPLLCLK() / (((PCDR) & 0xf)+1); in get_PERCLK1()77 return get_systemPLLCLK() / (((PCDR>>4) & 0xf)+1); in get_PERCLK2()82 return get_systemPLLCLK() / (((PCDR>>16) & 0x7f)+1); in get_PERCLK3()
39 #define PCDR 0xa7 /* Port C Data Register */ macro63 outb(PCDR, CSCIR); in dnp_dio_insn_bits()72 outb(PCDR, CSCIR); in dnp_dio_insn_bits()
26 #define PCDR 0x0040 /* PCM FIFO Data Register */ macro238 pxa2xx_ac97_pcm_stereo_in.addr = regs->start + PCDR; in pxa2xx_ac97_dev_probe()239 pxa2xx_ac97_pcm_stereo_out.addr = regs->start + PCDR; in pxa2xx_ac97_dev_probe()
17 #define PCDR 0xA4050124 macro
20 #define PCDR 0xA4050124 macro
162 #define PCDR 0xA4050124 macro
184 #define PCDR 0xA4050124 macro
187 #define PCDR (PORT_BASE + 0x44) macro
413 #define PCDR 0xFFEA0024 macro
1234 #define PCDR 0xA4050124 macro
32 #define PCDR 0xa4000124 macro153 *s++ = __raw_readb(PCDR); in jornada_scan_keyb()
73 #define PCDR (0x0040) /* PCM FIFO Data Register */ macro
377 volatile u_char PCDR; /* Port C Data Register */ member
40 PFC registers PCCR and PCDR must be set to peripheral mode.
105 #define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */ macro
415 #define PCDR 0x40500040 /* PCM FIFO Data Register */ macro