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Searched refs:MHZ (Results 1 – 20 of 20) sorted by relevance

/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A Dddrphy_utils.c110 dram_pll_init(MHZ(800)); in ddrphy_init_set_dfi_clk()
114 dram_pll_init(MHZ(750)); in ddrphy_init_set_dfi_clk()
118 dram_pll_init(MHZ(600)); in ddrphy_init_set_dfi_clk()
122 dram_pll_init(MHZ(400)); in ddrphy_init_set_dfi_clk()
126 dram_pll_init(MHZ(167)); in ddrphy_init_set_dfi_clk()
130 dram_enable_bypass(MHZ(400)); in ddrphy_init_set_dfi_clk()
133 dram_enable_bypass(MHZ(100)); in ddrphy_init_set_dfi_clk()
H A Dlpddr4_init.c57 dram_pll_init(MHZ(750)); in ddr_init()
/openbmc/u-boot/drivers/video/exynos/
H A Dexynos_mipi_dsi_common.c17 #define MHZ (1000 * 1000) macro
18 #define FIN_HZ (24 * MHZ)
20 #define DFIN_PLL_MIN_HZ (6 * MHZ)
21 #define DFIN_PLL_MAX_HZ (12 * MHZ)
23 #define DFVCO_MIN_HZ (500 * MHZ)
24 #define DFVCO_MAX_HZ (1000 * MHZ)
109 delay_val = MHZ / dsim->dsim_config->esc_clk; in exynos_mipi_dsi_wr_data()
288 if (dfin_pll < 7 * MHZ) in exynos_mipi_dsi_change_pll()
290 else if (dfin_pll < 8 * MHZ) in exynos_mipi_dsi_change_pll()
292 else if (dfin_pll < 9 * MHZ) in exynos_mipi_dsi_change_pll()
[all …]
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7623.c19 #define MT7623_PLL_FMAX (2000UL * MHZ)
83 FIXED_CLK(CLK_TOP_DPI, CLK_XTAL, 108 * MHZ),
84 FIXED_CLK(CLK_TOP_DMPLL, CLK_XTAL, 400 * MHZ),
85 FIXED_CLK(CLK_TOP_VENCPLL, CLK_XTAL, 295.75 * MHZ),
86 FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, CLK_XTAL, 340 * MHZ),
87 FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, CLK_XTAL, 340 * MHZ),
88 FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, CLK_XTAL, 340 * MHZ),
89 FIXED_CLK(CLK_TOP_HADDS2_FB, CLK_XTAL, 27 * MHZ),
90 FIXED_CLK(CLK_TOP_WBG_DIG_416M, CLK_XTAL, 416 * MHZ),
91 FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, CLK_XTAL, 143 * MHZ),
[all …]
H A Dclk-mtk.h11 #define MHZ (1000 * 1000) macro
H A Dclk-mt7629.c19 #define MT7629_PLL_FMAX (2500UL * MHZ)
543 .xtal_rate = 40 * MHZ,
544 .xtal2_rate = 20 * MHZ,
H A Dclk-mtk.c153 unsigned long fmin = 1000 * MHZ; in mtk_pll_calc_values()
/openbmc/u-boot/board/freescale/bsc9132qds/
H A DREADME94 make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK
95 make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK
98 make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK
99 make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK
101 make BSC9132QDS_SDCARD_DDRCLK100 : For 100MHZ DDR CLK
102 make BSC9132QDS_SDCARD_DDRCLK133 : For 133MHZ DDR CLK
/openbmc/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c529 DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
531 DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
533 DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
585 case MHZ(800): in dram_pll_init()
597 case MHZ(600): in dram_pll_init()
609 case MHZ(400): in dram_pll_init()
621 case MHZ(167): in dram_pll_init()
/openbmc/u-boot/board/freescale/b4860qds/
H A Db4_pbi.cfg25 #slowing down the MDC clock to make it <= 2.5 MHZ
/openbmc/u-boot/board/freescale/t208xqds/
H A Dt208x_pbi.cfg32 #Errata for slowing down the MDC clock to make it <= 2.5 MHZ
/openbmc/u-boot/board/freescale/t208xrdb/
H A Dt2080_pbi.cfg32 #Errata for slowing down the MDC clock to make it <= 2.5 MHZ
/openbmc/u-boot/arch/m68k/cpu/mcf5445x/
H A Dspeed.c27 #define MHZ 1000000 macro
209 if (bus <= CLOCK_PLL_FSYS_MIN - MHZ) in setup_5445x_clocks()
/openbmc/u-boot/arch/m68k/cpu/mcf5227x/
H A Dspeed.c27 #define MHZ 1000000 macro
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-benchmark/lmbench/lmbench/
H A Dupdate-results-script.patch95 -MHZ=`../bin/$OS/mhz`
96 +MHZ=`mhz`
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-kernel/oprofile/oprofile/
H A D0006-replace-sym_iterator-0-with-sym_iterator.patch43 str << init_attr(MHZ, speed) << endl;
/openbmc/u-boot/board/freescale/mpc8641hpcn/
H A DREADME65 SW6(3-5) = 000 CONFIG_SYS_REFCLKSEL = 000 :: 100MHZ
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dclock.h13 #define MHZ(X) ((X) * 1000000UL) macro
/openbmc/u-boot/board/freescale/m52277evb/
H A DREADME143 CPU CLK 160 Mhz BUS CLK 80 Mhz FLB CLK 80 MHZ
/openbmc/u-boot/
H A DREADME566 converts clock data to MHZ before passing it to the