1254887a5SShengzhou Liu# 2254887a5SShengzhou Liu# Copyright 2013 Freescale Semiconductor, Inc. 3254887a5SShengzhou Liu# 4254887a5SShengzhou Liu# SPDX-License-Identifier: GPL-2.0+ 5254887a5SShengzhou Liu# 6254887a5SShengzhou Liu# Refer doc/README.pblimage for more details about how-to configure 7254887a5SShengzhou Liu# and create PBL boot image 8254887a5SShengzhou Liu# 9254887a5SShengzhou Liu 10254887a5SShengzhou Liu#PBI commands 11254887a5SShengzhou Liu#Initialize CPC1 12254887a5SShengzhou Liu09010000 00200400 13254887a5SShengzhou Liu09138000 00000000 14254887a5SShengzhou Liu091380c0 00000100 15254887a5SShengzhou Liu#512KB SRAM 16254887a5SShengzhou Liu09010100 00000000 17254887a5SShengzhou Liu09010104 fff80009 18254887a5SShengzhou Liu09010f00 08000000 19254887a5SShengzhou Liu#enable CPC1 20254887a5SShengzhou Liu09010000 80000000 21254887a5SShengzhou Liu#Configure LAW for CPC1 22254887a5SShengzhou Liu09000d00 00000000 23254887a5SShengzhou Liu09000d04 fff80000 24254887a5SShengzhou Liu09000d08 81000012 25254887a5SShengzhou Liu#Initialize eSPI controller, default configuration is slow for eSPI to 26254887a5SShengzhou Liu#load data, this configuration comes from u-boot eSPI driver. 27254887a5SShengzhou Liu09110000 80000403 28254887a5SShengzhou Liu09110020 2d170008 29254887a5SShengzhou Liu09110024 00100008 30254887a5SShengzhou Liu09110028 00100008 31254887a5SShengzhou Liu0911002c 00100008 32254887a5SShengzhou Liu#Errata for slowing down the MDC clock to make it <= 2.5 MHZ 33254887a5SShengzhou Liu094fc030 00008148 34254887a5SShengzhou Liu094fd030 00008148 35254887a5SShengzhou Liu#Configure alternate space 36254887a5SShengzhou Liu09000010 00000000 37254887a5SShengzhou Liu09000014 ff000000 38254887a5SShengzhou Liu09000018 81000000 39254887a5SShengzhou Liu#Flush PBL data 40*c5938c10SZhao Qiang091380c0 00100000 41