L1 (reference) in projects: openbmc - OpenGrok search results

Searched refs:L1 (Results 1 – 25 of 195) sorted by relevance

/openbmc/qemu/tests/unit/
H A D	test-hbitmap.c	306 hbitmap_test_set(data, L1 * 4, L1 + 1); in test_hbitmap_set_two_elem() 307 hbitmap_test_set(data, L1 * 8 - 1, L1 + 1); in test_hbitmap_set_two_elem() 310 hbitmap_test_set(data, L2 + L1 * 4, L1 + 1); in test_hbitmap_set_two_elem() 318 hbitmap_test_set(data, L1 - 1, L1 + 2); in test_hbitmap_set() 319 hbitmap_test_set(data, L1 * 3 - 1, L1 + 2); in test_hbitmap_set() 320 hbitmap_test_set(data, L1 * 5, L1 * 2 + 1); in test_hbitmap_set() 341 hbitmap_test_set(data, L1 - 1, L1 + 2); in test_hbitmap_set_overlap() 348 hbitmap_test_set(data, L3 - L1, L1 * 3); in test_hbitmap_set_overlap() 364 hbitmap_test_set(data, L1 - 1, L1 + 2); in test_hbitmap_reset() 371 hbitmap_test_reset(data, L3 - L1, L1 * 3); in test_hbitmap_reset() [all …]
/openbmc/qemu/tests/qemu-iotests/
H A D	080.out	40 == Invalid L1 table == 47 == Invalid L1 table (with internal snapshot in the image) == 49 qemu-img: Could not open 'TEST_DIR/t.IMGFMT': L1 table is too small 62 == Invalid snapshot L1 table offset == 66 qemu-img: Failed to load snapshot: Snapshot L1 table offset invalid 67 qemu-img: Snapshot L1 table offset invalid 71 qemu-img: Snapshot L1 table offset invalid 85 == Invalid snapshot L1 table size == 89 qemu-img: Failed to load snapshot: Snapshot L1 table too large 90 qemu-img: Snapshot L1 table too large [all …]
H A D	029.out	`3 Test loading internal snapshots where the L1 table of the snapshot 4 is smaller than the current L1 table. 24 qcow2_snapshot_load_tmp() should take the L1 size from the snapshot`
H A D	029	`53 echo Test loading internal snapshots where the L1 table of the snapshot 54 echo is smaller than the current L1 table.`
/openbmc/linux/Documentation/virt/kvm/x86/
H A D	running-nested-guests.rst	19 \| L1 (Guest Hypervisor) \| 33 - L1 – level-1 guest; a VM running on L0; also called the "guest 36 - L2 – level-2 guest; a VM running on L1, this is the "nested guest" 148 able to start an L1 guest with:: 191 On AMD systems, once an L1 guest has started an L2 guest, the L1 guest 238 - Kernel, libvirt and QEMU version from L1 248 - ``cat /sys/cpuinfo`` from L1 252 - ``lscpu`` from L1 256 - Full ``dmesg`` output from L1 266 - Output of: ``x86info -a`` from L1 [all …]
/openbmc/linux/arch/arc/kernel/
H A D	entry-compact.S	152 ; if L2 IRQ interrupted a L1 ISR, disable preemption 154 ; This is to avoid a potential L1-L2-L1 scenario 155 ; -L1 IRQ taken 156 ; -L2 interrupts L1 (before L1 ISR could run) 160 ; But both L1 and L2 re-enabled, so another L1 can be taken 161 ; while prev L1 is still unserviced 165 ; L2 interrupting L1 implies both L2 and L1 active 167 ; need to check STATUS32_L2 to determine if L1 was active 320 ; use the same priority as rtie: EXCPN, L2 IRQ, L1 IRQ, None 343 ; if L2 IRQ interrupted an L1 ISR, we'd disabled preemption earlier [all …]
/openbmc/linux/arch/arm/mm/
H A D	proc-xsc3.S	68 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line 113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB 196 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line 197 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line 224 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line 229 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB 269 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line 271 mcrne p15, 0, r1, c7, c10, 1 @ clean L1 D line 272 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line 289 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line [all …]
/openbmc/linux/security/apparmor/include/
H A D	label.h	163 #define next_comb(I, L1, L2) \ argument 174 #define label_for_each_comb(I, L1, L2, P1, P2) \ argument 177 (I) = next_comb(I, L1, L2)) 179 #define fn_for_each_comb(L1, L2, P1, P2, FN) \ argument 183 label_for_each_comb(i, (L1), (L2), (P1), (P2)) { \ 243 #define fn_for_each2_XXX(L1, L2, P, FN, ...) \ argument 247 label_for_each ## __VA_ARGS__(i, (L1), (L2), (P)) { \ 253 #define fn_for_each_in_merge(L1, L2, P, FN) \ argument 254 fn_for_each2_XXX((L1), (L2), P, FN, _in_merge) 255 #define fn_for_each_not_in_set(L1, L2, P, FN) \ argument [all …]
H A D	perms.h	`183 #define xcheck_ns_labels(L1, L2, FN, args...) \ argument 186 fn_for_each((L1), __p1, FN(__p1, (L2), args)); \ 190 #define xcheck_labels_profiles(L1, L2, FN, args...) \ argument 191 xcheck_ns_labels((L1), (L2), xcheck_ns_profile_label, (FN), args) 193 #define xcheck_labels(L1, L2, P, FN1, FN2) \ argument 194 xcheck(fn_for_each((L1), (P), (FN1)), fn_for_each((L2), (P), (FN2)))`
/openbmc/phosphor-inventory-manager/
H A D	utils.hpp	`150 template <typename L1, typename L2, typename R1, typename R2> 151 bool operator()(const std::pair<L1, L2>& l, in operator ()() 168 template <typename L1, typename L2, typename R> 169 bool operator()(const std::pair<L1, L2>& l, const R& r) const in operator ()()`
/openbmc/linux/arch/powerpc/perf/
H A D	power8-pmu.c	`133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1); 134 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1); 136 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF); 137 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1); 138 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS); 139 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1); 140 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);`
H A D	power9-pmu.c	`177 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN); 178 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1); 179 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF); 180 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1); 181 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS); 182 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1); 183 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);`
H A D	power10-pmu.c	`133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1); 134 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1); 135 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_LD_PREFETCH_CACHE_LINE_MISS); 136 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1); 137 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS); 138 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1); 139 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_REQ);`
/openbmc/linux/arch/hexagon/lib/
H A D	memset.S	`159 if (r2==#0) jump:nt .L1 186 if (p1) jump .L1 197 if (p0.new) jump:nt .L1 208 if (p0.new) jump:nt .L1 284 .L1: label`
/openbmc/qemu/docs/interop/
H A D	qed_spec.txt	9 … regular cluster may be a '''data cluster''', an '''L2''', or an '''L1 table'''. L1 and L2 tables… 20 uint32_t table_size; /* for L1 and L2 tables, in clusters / 43 ''l1_table_offset'' is the offset of the first byte of the L1 table in the image file and must be… 69 \| L1 table \| 82 …ge size must be less than or equal to the maximum possible size of clusters rooted by the L1 table: 85 L1, L2, and data cluster offsets must be aligned to header.cluster_size. The following offsets hav… 114 \| L1 index \| L2 index \| byte offset \| 134 …ce. It is an inconsistency to have a cluster referenced more than once by L1 or L2 tables. A clu…
H A D	parallels.txt	209 The number of entries in the L1 table of the bitmap. 211 variable: L1 offset table (l1_table), size: 8 * l1_size bytes 215 saved in the L1 offset table specified by the feature extension. Each L1 table 218 Given an offset in bytes into the bitmap data, corresponding L1 entry is 222 If an L1 table entry is 0, all bits in the corresponding cluster of the bitmap 225 If an L1 table entry is 1, all bits in the corresponding cluster of the bitmap 228 If an L1 table entry is not 0 or 1, it contains the corresponding cluster
/openbmc/linux/Documentation/locking/
H A D	lockdep-design.rst	`145 <L1> -> <L2> 146 <L2> -> <L1> 521 L1 -> L2 608 L1 -> L2 ... -> Ln -> L1 612 L1 -> L2 616 Ln -> L1 620 Firstly let's make one CPU/task get the L1 in L1 -> L2, and then another get 624 And then because we have L1 -> L2, so the holder of L1 is going to acquire L2 625 in L1 -> L2, however since L2 is already held by another CPU/task, plus L1 -> 645 for L1 and holding Ln, so we will have Ln -> L1 in the dependency graph. Similarly, [all …]`
/openbmc/linux/drivers/pci/pcie/
H A D	Kconfig	`73 state L0/L0s/L1. 99 Enable PCI Express ASPM L0s and L1 where possible, even if the 106 Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where 107 possible. This would result in higher power savings while staying in L1 114 Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them.`
/openbmc/linux/arch/m68k/fpsp040/
H A D	setox.S	104 \| 3.1 R := X + NL1, where L1 := single-precision(-log2/64). 106 \| Notes: a) The way L1 and L2 are chosen ensures L1+L2 approximate 108 \| b) NL1 is exact because N is no longer than 22 bits and 109 \| L1 is no longer than 24 bits. 111 \| Thus, R is practically X+N(L1+L2) to full 64 bits. 505 fmuls #0xBC317218,%fp0 \| ...N * L1, L1 = lead(-log2/64) 506 fmulx L2,%fp2 \| ...N * L2, L1+L2 = -log2/64 507 faddx %fp1,%fp0 \| ...X + NL1 671 fmuls #0xBC317218,%fp0 \| ...N L1, L1 = lead(-log2/64) 672 fmulx L2,%fp2 \| ...N * L2, L1+L2 = -log2/64 [all …]
/openbmc/linux/Documentation/devicetree/bindings/media/
H A D	st-rc.txt	`10 - rx-mode: can be "infrared" or "uhf". This property specifies the L1 13 - tx-mode: should be "infrared". This property specifies the L1`
/openbmc/linux/arch/m68k/lib/
H A D	divsi3.S	`95 jpl L1 102 L1: movel sp@(8), d0 /* d0 = dividend */ label`
/openbmc/linux/Documentation/translations/zh_CN/arch/arm64/
H A D	memory.txt	`90 \| \| +---------------------> [38:30] L1 索引 105 \| +-------------------------------> [47:42] L1 索引`
/openbmc/linux/arch/alpha/boot/
H A D	bootp.c	`65 #define L1 ((unsigned long *) 0x200802000) macro 77 pcb_va->ptbr = L1[1] >> 32; in pal_init()`
H A D	main.c	`59 #define L1 ((unsigned long *) 0x200802000) macro 71 pcb_va->ptbr = L1[1] >> 32; in pal_init()`
/openbmc/linux/arch/riscv/lib/
H A D	tishift.S	`10 beqz a2, .L1 21 .L1: label`

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