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Searched refs:ICPU_SW_MODE_SW_SPI_CS (Results 1 – 8 of 8) sorted by relevance

/openbmc/u-boot/board/mscc/common/
H A Dspi.c20 ICPU_SW_MODE_SW_SPI_CS(BIT(cs)), in external_cs_manage()
/openbmc/u-boot/arch/mips/mach-mscc/
H A Dreset.c61 writel(ICPU_SW_MODE_SW_SPI_CS_OE(1) | ICPU_SW_MODE_SW_SPI_CS(1) | in _machine_restart()
/openbmc/u-boot/drivers/spi/
H A Dmscc_bb_spi.c58 ICPU_SW_MODE_SW_SPI_CS(BIT(cs)); in mscc_bb_spi_cs_activate()
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_icpu_cfg.h54 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5)) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_icpu_cfg.h54 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5)) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h50 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5)) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h57 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5)) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h55 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5)) macro