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Searched refs:ICPU_SW_MODE (Results 1 – 12 of 12) sorted by relevance

/openbmc/u-boot/board/mscc/common/
H A Dspi.c21 BASE_CFG + ICPU_SW_MODE); in external_cs_manage()
26 writel(0, BASE_CFG + ICPU_SW_MODE); in external_cs_manage()
/openbmc/u-boot/board/mscc/servalt/
H A Dservalt.c17 writel(0, BASE_CFG + ICPU_SW_MODE); in board_early_init_r()
/openbmc/u-boot/board/mscc/luton/
H A Dluton.c27 writel(0, BASE_CFG + ICPU_SW_MODE); in board_early_init_r()
/openbmc/u-boot/board/mscc/serval/
H A Dserval.c18 writel(0, BASE_CFG + ICPU_SW_MODE); in board_early_init_r()
/openbmc/u-boot/arch/mips/mach-mscc/
H A Dreset.c62 ICPU_SW_MODE_SW_PIN_CTRL_MODE, BASE_CFG + ICPU_SW_MODE); in _machine_restart()
/openbmc/u-boot/board/mscc/ocelot/
H A Docelot.c55 writel(0, BASE_CFG + ICPU_SW_MODE); in board_early_init_r()
/openbmc/u-boot/board/mscc/jr2/
H A Djr2.c19 writel(0, BASE_CFG + ICPU_SW_MODE); in board_early_init_r()
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_icpu_cfg.h47 #define ICPU_SW_MODE 0x64 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_icpu_cfg.h47 #define ICPU_SW_MODE 0x50 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h43 #define ICPU_SW_MODE 0x50 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h48 #define ICPU_SW_MODE 0x50 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h50 #define ICPU_SW_MODE 0x50 macro