| /openbmc/u-boot/drivers/i2c/ |
| H A D | Kconfig | 2 # I2C subsystem configuration
5 menu "I2C support"
8 bool "Enable Driver Model for I2C drivers"
11 Enable driver model for I2C. The I2C uclass interface: probe, read,
20 bool "Enable I2C compatibility layer"
23 Enable old-style I2C functions for compatibility with existing code.
29 tristate "Chrome OS EC tunnel I2C bus"
32 This provides an I2C bus that will tunnel i2c commands through to
33 the other side of the Chrome OS EC to the I2C bus connected there.
35 I2C or LPC). Some Chromebooks use this when the hardware design
[all …]
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| /openbmc/phosphor-bmc-code-mgmt/common/include/i2c/ |
| H A D | i2c.hpp | 23 class I2C class
26 explicit I2C(uint16_t bus, uint16_t node) : in I2C() function in phosphor::i2c::I2C
32 I2C(I2C& i2c) = delete;
33 I2C& operator=(I2C other) = delete;
34 I2C(I2C&& other) = delete;
35 I2C& operator=(I2C&& other) = delete;
37 ~I2C() in ~I2C()
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| /openbmc/u-boot/drivers/i2c/muxes/ |
| H A D | Kconfig | 2 bool "Support I2C multiplexers"
5 This enables I2C buses to be multiplexed, so that you can select
8 using a suitable I2C MUX driver.
11 bool "Support I2C multiplexers on SPL"
14 This enables I2C buses to be multiplexed, so that you can select
17 using a suitable I2C MUX driver.
20 bool "GPIO-based I2C arbitration"
24 I2C multimaster arbitration scheme using GPIOs and a challenge &
29 tristate "TI PCA954x I2C Mux/switches"
33 I2C mux/switch devices. It is x width I2C multiplexer which enables to
[all …]
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| /openbmc/qemu/hw/i2c/ |
| H A D | Kconfig | 1 config I2C config
11 select I2C
27 select I2C
31 select I2C
35 select I2C
39 select I2C
43 select I2C
51 select I2C
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| /openbmc/u-boot/doc/device-tree-bindings/i2c/ |
| H A D | nvidia,tegra186-bpmp-i2c.txt | 1 NVIDIA Tegra186 BPMP I2C controller
4 devices, such as the I2C controller for the power management I2C bus. Software
6 transactions on that I2C bus. This binding describes an I2C bus that is
9 The BPMP I2C node must be located directly inside the main BPMP node. See
12 This node represents an I2C controller. See ../i2c/i2c.txt for details of the
13 core I2C binding.
20 - #address-cells: Address cells for I2C device address.
28 Indicates the I2C bus number this DT node represent, as defined by the
|
| H A D | i2c.txt | 1 U-Boot I2C
4 U-Boot's I2C model has the concept of an offset within a chip (I2C target
9 Apart from the controller-specific I2C bindings, U-Boot supports a special
19 Pin description for I2C bus software deblocking.
|
| H A D | i2c-stm32.txt | 1 * I2C controller embedded in STMicroelectronis STM32 platforms
7 - clocks: Must contain the input clock of the I2C instance
9 operation for I2C transfer
14 - clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
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| /openbmc/qemu/hw/sensor/ |
| H A D | Kconfig | 3 depends on I2C
8 depends on I2C
13 depends on I2C
18 depends on I2C
23 depends on I2C
32 depends on I2C
36 depends on I2C
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| /openbmc/u-boot/doc/ |
| H A D | I2C_Edge_Conditions | 1 I2C Edge Conditions:
4 I2C devices may be left in a write state if a read was occuring
9 2) I2C controller issues a start command.
10 3) The I2C writes the device address.
14 1) The I2C controller issues a start command.
15 2) The I2C controller writes the device address.
16 3) The I2C controller writes the offset.
31 !!!THIS IS AN UNDOCUMENTED I2C BUS BUG, NOT A AMCC 4xx BUG!!!
33 This reset edge condition could possibly be present in every I2C
34 controller and device available. For boards where a I2C bus reset
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| /openbmc/phosphor-power/phosphor-regulators/docs/config_file/ |
| H A D | i2c_interface.md | 5 I2C interface to a device.
7 Direct I2C communication to the device will be performed using the
17 | bus | yes | number | I2C bus number of the device. The first bus is 0. …
18 | address | yes | string | 7-bit I2C address of the device expressed in hexadecimal. Must be p…
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| /openbmc/qemu/hw/gpio/ |
| H A D | Kconfig | 21 depends on I2C
25 depends on I2C
29 depends on I2C
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| /openbmc/qemu/hw/rtc/ |
| H A D | Kconfig | 3 depends on I2C
8 depends on I2C
32 depends on I2C
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| /openbmc/phosphor-power/phosphor-power-sequencer/docs/config_file/ |
| H A D | i2c_interface.md | 5 I2C interface to a device.
11 | bus | yes | number | I2C bus number of the device. The first bus is 0. …
12 | address | yes | string | 7-bit I2C address of the device expressed in hexadecimal. Must be p…
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| /openbmc/qemu/docs/system/arm/ |
| H A D | stellaris.rst | 11 - Timers, UARTs, ADC and |I2C| interface.
14 |I2C| bus.
23 - Timers, UARTs, ADC, |I2C| and SSI interfaces.
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| /openbmc/phosphor-power/phosphor-power-supply/ |
| H A D | README.md | 23 ### I2C Bus
25 The I2C bus(es) that the power supply is on will be represented by the `I2CBus`
29 ### I2C Address
31 The I2C address(es) that the power supply is at will be represented by the
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| /openbmc/phosphor-bmc-code-mgmt/common/i2c/ |
| H A D | i2c.cpp | 15 int I2C::open() in open()
34 sdbusplus::async::task<bool> I2C::sendReceive( in sendReceive()
79 bool I2C::sendReceive(const std::vector<uint8_t>& writeData, in sendReceive()
124 void I2C::close() in close()
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| /openbmc/u-boot/board/ti/common/ |
| H A D | Kconfig | 5 Evaluation Boards which have I2C based EEPROM detection
8 int "Board EEPROM's I2C bus address"
13 hex "Board EEPROM's I2C chip address"
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| /openbmc/qemu/hw/misc/ |
| H A D | Kconfig | 36 depends on I2C
40 depends on I2C
44 depends on I2C
178 select I2C
240 depends on I2C
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| /openbmc/phosphor-host-ipmid/docs/ |
| H A D | oem-extension-numbering.md | 72 | 2 | i2cCmd | I2C Device Access |
77 ## I2C Device Access (Command 2)
79 The next subsections describe command and response messages supporting the I2C
82 ### I2C Request Message - Overall
86 | 0 | | bus | Logical I2C bus. |
114 ### I2C Request Message - Step Properties
119 | | 7:1 | dev | 7-bit I2C device address. |
123 | | 6 | i2cFlagNoStart | 1 to suppress I2C start. |
155 ### I2C Response Message
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| /openbmc/qemu/hw/display/ |
| H A D | Kconfig | 3 depends on I2C
30 depends on I2C
35 depends on I2C
74 select I2C
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| /openbmc/u-boot/board/ge/common/ |
| H A D | Kconfig | 2 hex "I2C address of the EEPROM device used for VPD"
7 int "I2C bus of the EEPROM device used for VPD."
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| /openbmc/u-boot/drivers/misc/ |
| H A D | Kconfig | 45 Enable support for I2C connected Atmel's ATSHA204A
78 and talking to the I2C bus behind the EC (if there is one).
90 bool "Enable Chrome OS EC I2C driver"
93 Enable I2C access to the Chrome OS EC. This is used on older
95 changed to SPI. The EC will accept commands across the I2C using
102 Enable I2C access to the Chrome OS EC. This is used on x86
122 provides a faster and more robust interface than I2C but the bugs
131 connected over I2C.
184 is connected via I2C. So I2C needs to be enabled.
187 hex "I2C address of PCA9551 LED controller"
[all …]
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| /openbmc/u-boot/drivers/reset/aspeed/ |
| H A D | Kconfig | 9 is that some reset signals, like I2C or MISC reset multiple devices.
19 is that some reset signals, like I2C or MISC reset multiple devices.
29 is that some reset signals, like I2C or MISC reset multiple devices.
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| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/pxaregs/pxaregs-1.14/ |
| H A D | serial.patch | 8 { "ISAR", 0x403016A0, 0, 0xffffffff, 'x', "I2C Slave Address Register" },
9 { "ISAR_SA", 0x403016A0, 0, 0x0000007f, 'x', "I2C Slave Address" },
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| /openbmc/qemu/hw/tpm/ |
| H A D | trace-events | 41 tpm_tis_i2c_recv(uint8_t data) "TPM I2C read: 0x%X"
42 tpm_tis_i2c_send(uint8_t data) "TPM I2C write: 0x%X"
43 tpm_tis_i2c_event(const char *event) "TPM I2C event: %s"
44 tpm_tis_i2c_send_reg(const char *name, int reg) "TPM I2C write register: %s(0x%X)"
|