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Searched refs:GPIO_NUM_PINS (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/hw/arm/
H A Db-l475e-iot01a.c47 1 * GPIO_NUM_PINS + 2, /* ROW0 PB2 */
48 0 * GPIO_NUM_PINS + 15, /* ROW1 PA15 */
49 0 * GPIO_NUM_PINS + 2, /* ROW2 PA2 */
50 0 * GPIO_NUM_PINS + 7, /* ROW3 PA7 */
51 0 * GPIO_NUM_PINS + 6, /* ROW4 PA6 */
52 0 * GPIO_NUM_PINS + 5, /* ROW5 PA5 */
53 1 * GPIO_NUM_PINS + 0, /* ROW6 PB0 */
54 0 * GPIO_NUM_PINS + 3, /* ROW7 PA3 */
55 0 * GPIO_NUM_PINS + 4, /* SIN (SDA) PA4 */
56 1 * GPIO_NUM_PINS + 1, /* DCK (SCK) PB1 */
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H A Dstm32l4x5_soc.c245 for (unsigned j = 0; j < GPIO_NUM_PINS; j++) { in stm32l4x5_soc_realize()
246 pin_index = GPIO_NUM_PINS * i + j; in stm32l4x5_soc_realize()
301 for (unsigned i = 0; i < GPIO_NUM_PINS; i++) { in stm32l4x5_soc_realize()
/openbmc/qemu/include/hw/gpio/
H A Dstm32l4x5_gpio.h29 #define GPIO_NUM_PINS 16 macro
68 qemu_irq pin[GPIO_NUM_PINS];
/openbmc/qemu/hw/misc/
H A Dstm32l4x5_syscfg.c88 const uint8_t gpio = irq / GPIO_NUM_PINS; in stm32l4x5_syscfg_set_irq()
89 const int line = irq % GPIO_NUM_PINS; in stm32l4x5_syscfg_set_irq()
226 GPIO_NUM_PINS * NUM_GPIOS); in stm32l4x5_syscfg_init()
227 qdev_init_gpio_out(DEVICE(obj), s->gpio_out, GPIO_NUM_PINS); in stm32l4x5_syscfg_init()
/openbmc/qemu/hw/gpio/
H A Dstm32l4x5_gpio.c127 for (int i = 0; i < GPIO_NUM_PINS; i++) { in update_gpio_idr()
185 for (int i = 0; i < GPIO_NUM_PINS; i++) { in update_gpio_idr()
206 for (int i = 0; i < GPIO_NUM_PINS; i++) { in get_gpio_pinmask_to_disconnect()
299 uint32_t bits_to_reset = (value & RESERVED_BITS_MASK) >> GPIO_NUM_PINS; in stm32l4x5_gpio_write()
407 qdev_init_gpio_out(DEVICE(obj), s->pin, GPIO_NUM_PINS); in stm32l4x5_gpio_init()
408 qdev_init_gpio_in(DEVICE(obj), stm32l4x5_gpio_set, GPIO_NUM_PINS); in stm32l4x5_gpio_init()
/openbmc/qemu/include/hw/misc/
H A Dstm32l4x5_syscfg.h50 qemu_irq gpio_out[GPIO_NUM_PINS];