| /openbmc/u-boot/arch/arm/lib/ |
| H A D | cache-cp15.c | 215 if ((cache_bit == CR_C) && !mmu_enabled()) in cache_enable()
218 if ((cache_bit == CR_C) && !mpu_enabled()) { in cache_enable()
234 if (cache_bit == CR_C) { in cache_disable()
236 if ((reg & CR_C) != CR_C) in cache_disable()
243 if (cache_bit == (CR_C | CR_M)) in cache_disable()
299 cache_enable(CR_C); in dcache_enable()
304 cache_disable(CR_C); in dcache_disable()
309 return (get_cr() & CR_C) != 0; in dcache_status()
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| /openbmc/linux/arch/arm/mach-spear/ |
| H A D | hotplug.c | 35 : "r" (0), "Ir" (CR_C) in cpu_enter_lowpower()
50 : "Ir" (CR_C) in cpu_leave_lowpower()
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| /openbmc/linux/arch/arm/mach-versatile/ |
| H A D | hotplug.c | 37 : "r" (0), "Ir" (CR_C), "Ir" (actrl_mask) in versatile_immitation_enter_lowpower()
53 : "Ir" (CR_C), "Ir" (actrl_mask) in versatile_immitation_leave_lowpower()
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| /openbmc/linux/arch/arm/mach-tegra/ |
| H A D | sleep.S | 41 tst r2, #CR_C @ see tegra_sleep_cpu()
42 bic r2, r2, #CR_C
117 movw r2, #CR_I | CR_Z | CR_C | CR_M
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| /openbmc/u-boot/arch/arm/mach-uniphier/arm32/ |
| H A D | lowlevel_init.S | 24 orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
43 bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache
75 orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable
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| H A D | psci_smp.S | 16 bic r1, r1, #(CR_C | CR_M) @ Disable MMU and Dcache
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| /openbmc/linux/arch/arm/mm/ |
| H A D | cache-feroceon-l2.c | 243 if (cr & CR_C) { in flush_and_disable_dcache()
248 set_cr(cr & ~CR_C); in flush_and_disable_dcache()
260 set_cr(cr | CR_C); in enable_dcache()
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| H A D | mmu.c | 82 .cr_mask = CR_W|CR_C,
87 .cr_mask = CR_C,
1689 set_cr(cr & ~(CR_I | CR_C)); in early_paging_init()
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| /openbmc/linux/arch/arm/mach-shmobile/ |
| H A D | platsmp-apmu.c | 98 : "Ir" (CR_C) in cpu_enter_lowpower_a15()
168 : "Ir" (CR_C), "Ir" (0x40) in cpu_leave_lowpower()
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| /openbmc/u-boot/arch/arm/cpu/armv8/ |
| H A D | cache_v8.c | 471 set_sctlr(get_sctlr() | CR_C); in dcache_enable()
481 if (!(sctlr & CR_C)) in dcache_disable()
484 set_sctlr(sctlr & ~(CR_C|CR_M)); in dcache_disable()
492 return (get_sctlr() & CR_C) != 0; in dcache_status()
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| H A D | cache.S | 231 movn x1, #(CR_M | CR_C | CR_I)
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| /openbmc/linux/arch/arm/include/asm/ |
| H A D | cp15.h | 12 #define CR_C (1 << 2) /* Dcache enable */ macro
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| H A D | cacheflush.h | 454 "bic r0, r0, #"__stringify(CR_C)" \n\t" \
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| /openbmc/u-boot/arch/arm/include/asm/ |
| H A D | system.h | 15 #define CR_C (1 << 2) /* Dcache enable */ macro
292 #define CR_C (1 << 2) /* Dcache enable */ macro
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| /openbmc/linux/arch/arm/mach-exynos/ |
| H A D | mcpm-exynos.c | 39 "bic r0, r0, #"__stringify(CR_C)"\n\t" \
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| H A D | platsmp.c | 45 : "Ir" (CR_C), "Ir" (0x40) in cpu_leave_lowpower()
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| /openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 216 set_cr(get_cr() | CR_C); in enable_caches()
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| /openbmc/linux/arch/arm/mach-mvebu/ |
| H A D | pmsu.c | 300 : : "Ir" (CR_C) : "r0"); in armada_370_xp_pmsu_idle_enter()
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| /openbmc/linux/arch/arm/kernel/ |
| H A D | head-nommu.S | 176 bic r0, r0, #CR_C
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| /openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/ |
| H A D | cpu.c | 594 set_sctlr(get_sctlr() | CR_C); in arch_cpu_init()
|