| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 69 #define CLK_TOP_APLL2 37 macro
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| H A D | mediatek,mt6795-clk.h | 37 #define CLK_TOP_APLL2 26 macro
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| H A D | mt8173-clk.h | 36 #define CLK_TOP_APLL2 26 macro
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| H A D | mediatek,mt8365-clk.h | 58 #define CLK_TOP_APLL2 48 macro
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| H A D | mt2712-clk.h | 79 #define CLK_TOP_APLL2 48 macro
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| H A D | mt8192-clk.h | 117 #define CLK_TOP_APLL2 105 macro
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| H A D | mediatek,mt8188-clk.h | 84 #define CLK_TOP_APLL2 73 macro
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| H A D | mt8195-clk.h | 105 #define CLK_TOP_APLL2 93 macro
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| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt6795-topckgen.c | 387 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
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| H A D | clk-mt8173-topckgen.c | 462 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
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| H A D | clk-mt8516.c | 64 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
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| H A D | clk-mt8167.c | 71 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
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| H A D | clk-mt8188-topckgen.c | 1132 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL2, "top_apll2",
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| H A D | clk-mt2712.c | 87 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
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| H A D | clk-mt8365.c | 80 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
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| H A D | clk-mt8192.c | 63 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
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| H A D | clk-mt8195-topckgen.c | 1091 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL2, "top_apll2",
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| /openbmc/linux/Documentation/devicetree/bindings/sound/ |
| H A D | mt8195-afe-pcm.yaml | 162 <&topckgen 166>, //CLK_TOP_APLL2
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| /openbmc/linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt8173.dtsi | 880 <&topckgen CLK_TOP_APLL2>;
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| H A D | mt8192.dtsi | 980 <&topckgen CLK_TOP_APLL2>,
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