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Searched refs:CLKID_VPU_0_DIV (Results 1 – 9 of 9) sorted by relevance

/openbmc/u-boot/drivers/clk/
H A Dclk_meson.c48 #define CLKID_VPU_0_DIV 127 macro
277 case CLKID_VPU_0_DIV: in meson_div_get_rate()
332 case CLKID_VPU_0_DIV: in meson_div_set_rate()
756 rate = meson_div_get_rate(clk, CLKID_VPU_0_DIV); in meson_clk_get_rate_by_id()
770 case CLKID_VPU_0_DIV: in meson_clk_get_rate_by_id()
840 return meson_div_set_rate(clk, CLKID_VPU_0_DIV, rate, in meson_clk_set_rate_by_id()
851 case CLKID_VPU_0_DIV: in meson_clk_set_rate_by_id()
/openbmc/linux/include/dt-bindings/clock/
H A Daxg-clkc.h101 #define CLKID_VPU_0_DIV 91 macro
H A Dgxbb-clkc.h135 #define CLKID_VPU_0_DIV 127 macro
H A Dmeson8b-clkc.h191 #define CLKID_VPU_0_DIV 184 macro
H A Dg12a-clkc.h122 #define CLKID_VPU_0_DIV 111 macro
/openbmc/linux/drivers/clk/meson/
H A Dmeson8b.c2957 [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
3165 [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
3382 [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
H A Dgxbb.c2860 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
3068 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
H A Dg12a.c4361 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4586 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4846 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
H A Daxg.c1986 [CLKID_VPU_0_DIV] = &axg_vpu_0_div.hw,