122f65a38SJerome Brunet // SPDX-License-Identifier: GPL-2.0 2738f66d3SMichael Turquette /* 3738f66d3SMichael Turquette * Copyright (c) 2016 AmLogic, Inc. 4738f66d3SMichael Turquette * Michael Turquette <mturquette@baylibre.com> 5738f66d3SMichael Turquette */ 6738f66d3SMichael Turquette 7738f66d3SMichael Turquette #include <linux/clk-provider.h> 8161f6e5bSJerome Brunet #include <linux/init.h> 90d48fc55SNeil Armstrong #include <linux/mod_devicetable.h> 10738f66d3SMichael Turquette #include <linux/platform_device.h> 1120425f63SKevin Hilman #include <linux/module.h> 12738f66d3SMichael Turquette 13738f66d3SMichael Turquette #include "gxbb.h" 147f9768a5SJerome Brunet #include "clk-regmap.h" 15889c2b7eSJerome Brunet #include "clk-pll.h" 16889c2b7eSJerome Brunet #include "clk-mpll.h" 176682bd4dSJerome Brunet #include "meson-eeclk.h" 18889c2b7eSJerome Brunet #include "vid-pll-div.h" 19738f66d3SMichael Turquette 20*ccbfbd36SNeil Armstrong #include <dt-bindings/clock/gxbb-clkc.h> 21*ccbfbd36SNeil Armstrong 2227aad905SYixun Lan static DEFINE_SPINLOCK(meson_clk_lock); 23738f66d3SMichael Turquette 24dd601dbcSJerome Brunet static const struct pll_params_table gxbb_gp0_pll_params_table[] = { 25dd601dbcSJerome Brunet PLL_PARAMS(32, 1), 26dd601dbcSJerome Brunet PLL_PARAMS(33, 1), 27dd601dbcSJerome Brunet PLL_PARAMS(34, 1), 28dd601dbcSJerome Brunet PLL_PARAMS(35, 1), 29dd601dbcSJerome Brunet PLL_PARAMS(36, 1), 30dd601dbcSJerome Brunet PLL_PARAMS(37, 1), 31dd601dbcSJerome Brunet PLL_PARAMS(38, 1), 32dd601dbcSJerome Brunet PLL_PARAMS(39, 1), 33dd601dbcSJerome Brunet PLL_PARAMS(40, 1), 34dd601dbcSJerome Brunet PLL_PARAMS(41, 1), 35dd601dbcSJerome Brunet PLL_PARAMS(42, 1), 36dd601dbcSJerome Brunet PLL_PARAMS(43, 1), 37dd601dbcSJerome Brunet PLL_PARAMS(44, 1), 38dd601dbcSJerome Brunet PLL_PARAMS(45, 1), 39dd601dbcSJerome Brunet PLL_PARAMS(46, 1), 40dd601dbcSJerome Brunet PLL_PARAMS(47, 1), 41dd601dbcSJerome Brunet PLL_PARAMS(48, 1), 42dd601dbcSJerome Brunet PLL_PARAMS(49, 1), 43dd601dbcSJerome Brunet PLL_PARAMS(50, 1), 44dd601dbcSJerome Brunet PLL_PARAMS(51, 1), 45dd601dbcSJerome Brunet PLL_PARAMS(52, 1), 46dd601dbcSJerome Brunet PLL_PARAMS(53, 1), 47dd601dbcSJerome Brunet PLL_PARAMS(54, 1), 48dd601dbcSJerome Brunet PLL_PARAMS(55, 1), 49dd601dbcSJerome Brunet PLL_PARAMS(56, 1), 50dd601dbcSJerome Brunet PLL_PARAMS(57, 1), 51dd601dbcSJerome Brunet PLL_PARAMS(58, 1), 52dd601dbcSJerome Brunet PLL_PARAMS(59, 1), 53dd601dbcSJerome Brunet PLL_PARAMS(60, 1), 54dd601dbcSJerome Brunet PLL_PARAMS(61, 1), 55dd601dbcSJerome Brunet PLL_PARAMS(62, 1), 56738f66d3SMichael Turquette { /* sentinel */ }, 57738f66d3SMichael Turquette }; 58738f66d3SMichael Turquette 59dd601dbcSJerome Brunet static const struct pll_params_table gxl_gp0_pll_params_table[] = { 60dd601dbcSJerome Brunet PLL_PARAMS(42, 1), 61dd601dbcSJerome Brunet PLL_PARAMS(43, 1), 62dd601dbcSJerome Brunet PLL_PARAMS(44, 1), 63dd601dbcSJerome Brunet PLL_PARAMS(45, 1), 64dd601dbcSJerome Brunet PLL_PARAMS(46, 1), 65dd601dbcSJerome Brunet PLL_PARAMS(47, 1), 66dd601dbcSJerome Brunet PLL_PARAMS(48, 1), 67dd601dbcSJerome Brunet PLL_PARAMS(49, 1), 68dd601dbcSJerome Brunet PLL_PARAMS(50, 1), 69dd601dbcSJerome Brunet PLL_PARAMS(51, 1), 70dd601dbcSJerome Brunet PLL_PARAMS(52, 1), 71dd601dbcSJerome Brunet PLL_PARAMS(53, 1), 72dd601dbcSJerome Brunet PLL_PARAMS(54, 1), 73dd601dbcSJerome Brunet PLL_PARAMS(55, 1), 74dd601dbcSJerome Brunet PLL_PARAMS(56, 1), 75dd601dbcSJerome Brunet PLL_PARAMS(57, 1), 76dd601dbcSJerome Brunet PLL_PARAMS(58, 1), 77dd601dbcSJerome Brunet PLL_PARAMS(59, 1), 78dd601dbcSJerome Brunet PLL_PARAMS(60, 1), 79dd601dbcSJerome Brunet PLL_PARAMS(61, 1), 80dd601dbcSJerome Brunet PLL_PARAMS(62, 1), 81dd601dbcSJerome Brunet PLL_PARAMS(63, 1), 82dd601dbcSJerome Brunet PLL_PARAMS(64, 1), 83dd601dbcSJerome Brunet PLL_PARAMS(65, 1), 84dd601dbcSJerome Brunet PLL_PARAMS(66, 1), 850d48fc55SNeil Armstrong { /* sentinel */ }, 860d48fc55SNeil Armstrong }; 870d48fc55SNeil Armstrong 8887173557SJerome Brunet static struct clk_regmap gxbb_fixed_pll_dco = { 89722825dcSJerome Brunet .data = &(struct meson_clk_pll_data){ 90e40c7e3cSJerome Brunet .en = { 91e40c7e3cSJerome Brunet .reg_off = HHI_MPLL_CNTL, 92e40c7e3cSJerome Brunet .shift = 30, 93e40c7e3cSJerome Brunet .width = 1, 94e40c7e3cSJerome Brunet }, 95738f66d3SMichael Turquette .m = { 96738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL, 97738f66d3SMichael Turquette .shift = 0, 98738f66d3SMichael Turquette .width = 9, 99738f66d3SMichael Turquette }, 100738f66d3SMichael Turquette .n = { 101738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL, 102738f66d3SMichael Turquette .shift = 9, 103738f66d3SMichael Turquette .width = 5, 104738f66d3SMichael Turquette }, 10507f45e2eSJerome Brunet .frac = { 10607f45e2eSJerome Brunet .reg_off = HHI_MPLL_CNTL2, 10707f45e2eSJerome Brunet .shift = 0, 10807f45e2eSJerome Brunet .width = 12, 10907f45e2eSJerome Brunet }, 110722825dcSJerome Brunet .l = { 111722825dcSJerome Brunet .reg_off = HHI_MPLL_CNTL, 112722825dcSJerome Brunet .shift = 31, 113722825dcSJerome Brunet .width = 1, 114722825dcSJerome Brunet }, 115722825dcSJerome Brunet .rst = { 116722825dcSJerome Brunet .reg_off = HHI_MPLL_CNTL, 117722825dcSJerome Brunet .shift = 29, 118722825dcSJerome Brunet .width = 1, 119722825dcSJerome Brunet }, 120722825dcSJerome Brunet }, 121738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 12287173557SJerome Brunet .name = "fixed_pll_dco", 123738f66d3SMichael Turquette .ops = &meson_clk_pll_ro_ops, 1240dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 1250dea3f35SAlexandre Mergnat .fw_name = "xtal", 1260dea3f35SAlexandre Mergnat }, 127738f66d3SMichael Turquette .num_parents = 1, 128738f66d3SMichael Turquette }, 129738f66d3SMichael Turquette }; 130738f66d3SMichael Turquette 13187173557SJerome Brunet static struct clk_regmap gxbb_fixed_pll = { 13287173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 13387173557SJerome Brunet .offset = HHI_MPLL_CNTL, 13487173557SJerome Brunet .shift = 16, 13587173557SJerome Brunet .width = 2, 13687173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 13787173557SJerome Brunet }, 13887173557SJerome Brunet .hw.init = &(struct clk_init_data){ 13987173557SJerome Brunet .name = "fixed_pll", 14087173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 1410dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 1420dea3f35SAlexandre Mergnat &gxbb_fixed_pll_dco.hw 1430dea3f35SAlexandre Mergnat }, 14487173557SJerome Brunet .num_parents = 1, 14587173557SJerome Brunet /* 14687173557SJerome Brunet * This clock won't ever change at runtime so 14787173557SJerome Brunet * CLK_SET_RATE_PARENT is not required 14887173557SJerome Brunet */ 14987173557SJerome Brunet }, 15087173557SJerome Brunet }; 15187173557SJerome Brunet 1523c4fe763SJerome Brunet static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = { 1533c4fe763SJerome Brunet .mult = 2, 1543c4fe763SJerome Brunet .div = 1, 1553c4fe763SJerome Brunet .hw.init = &(struct clk_init_data){ 1563c4fe763SJerome Brunet .name = "hdmi_pll_pre_mult", 1573c4fe763SJerome Brunet .ops = &clk_fixed_factor_ops, 1580dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 1590dea3f35SAlexandre Mergnat .fw_name = "xtal", 1600dea3f35SAlexandre Mergnat }, 1613c4fe763SJerome Brunet .num_parents = 1, 1623c4fe763SJerome Brunet }, 1633c4fe763SJerome Brunet }; 1643c4fe763SJerome Brunet 16587173557SJerome Brunet static struct clk_regmap gxbb_hdmi_pll_dco = { 166722825dcSJerome Brunet .data = &(struct meson_clk_pll_data){ 167e40c7e3cSJerome Brunet .en = { 168e40c7e3cSJerome Brunet .reg_off = HHI_HDMI_PLL_CNTL, 169e40c7e3cSJerome Brunet .shift = 30, 170e40c7e3cSJerome Brunet .width = 1, 171e40c7e3cSJerome Brunet }, 172738f66d3SMichael Turquette .m = { 173738f66d3SMichael Turquette .reg_off = HHI_HDMI_PLL_CNTL, 174738f66d3SMichael Turquette .shift = 0, 175738f66d3SMichael Turquette .width = 9, 176738f66d3SMichael Turquette }, 177738f66d3SMichael Turquette .n = { 178738f66d3SMichael Turquette .reg_off = HHI_HDMI_PLL_CNTL, 179738f66d3SMichael Turquette .shift = 9, 180738f66d3SMichael Turquette .width = 5, 181738f66d3SMichael Turquette }, 182738f66d3SMichael Turquette .frac = { 183738f66d3SMichael Turquette .reg_off = HHI_HDMI_PLL_CNTL2, 184738f66d3SMichael Turquette .shift = 0, 185738f66d3SMichael Turquette .width = 12, 186738f66d3SMichael Turquette }, 187722825dcSJerome Brunet .l = { 188722825dcSJerome Brunet .reg_off = HHI_HDMI_PLL_CNTL, 189722825dcSJerome Brunet .shift = 31, 190722825dcSJerome Brunet .width = 1, 191722825dcSJerome Brunet }, 192722825dcSJerome Brunet .rst = { 193722825dcSJerome Brunet .reg_off = HHI_HDMI_PLL_CNTL, 194722825dcSJerome Brunet .shift = 28, 195722825dcSJerome Brunet .width = 1, 196722825dcSJerome Brunet }, 197722825dcSJerome Brunet }, 198738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 19987173557SJerome Brunet .name = "hdmi_pll_dco", 200738f66d3SMichael Turquette .ops = &meson_clk_pll_ro_ops, 2010dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 2020dea3f35SAlexandre Mergnat &gxbb_hdmi_pll_pre_mult.hw 2030dea3f35SAlexandre Mergnat }, 204738f66d3SMichael Turquette .num_parents = 1, 2052303a9caSJerome Brunet /* 2062303a9caSJerome Brunet * Display directly handle hdmi pll registers ATM, we need 2072303a9caSJerome Brunet * NOCACHE to keep our view of the clock as accurate as possible 2082303a9caSJerome Brunet */ 209738f66d3SMichael Turquette .flags = CLK_GET_RATE_NOCACHE, 210738f66d3SMichael Turquette }, 211738f66d3SMichael Turquette }; 212738f66d3SMichael Turquette 2130058502fSNeil Armstrong static struct clk_regmap gxl_hdmi_pll_dco = { 2140058502fSNeil Armstrong .data = &(struct meson_clk_pll_data){ 2150058502fSNeil Armstrong .en = { 2160058502fSNeil Armstrong .reg_off = HHI_HDMI_PLL_CNTL, 2170058502fSNeil Armstrong .shift = 30, 2180058502fSNeil Armstrong .width = 1, 2190058502fSNeil Armstrong }, 2200058502fSNeil Armstrong .m = { 2210058502fSNeil Armstrong .reg_off = HHI_HDMI_PLL_CNTL, 2220058502fSNeil Armstrong .shift = 0, 2230058502fSNeil Armstrong .width = 9, 2240058502fSNeil Armstrong }, 2250058502fSNeil Armstrong .n = { 2260058502fSNeil Armstrong .reg_off = HHI_HDMI_PLL_CNTL, 2270058502fSNeil Armstrong .shift = 9, 2280058502fSNeil Armstrong .width = 5, 2290058502fSNeil Armstrong }, 23021310c39SNeil Armstrong /* 23121310c39SNeil Armstrong * On gxl, there is a register shift due to 23221310c39SNeil Armstrong * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb, 23321310c39SNeil Armstrong * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB 23421310c39SNeil Armstrong * instead which is defined at the same offset. 23521310c39SNeil Armstrong */ 2360058502fSNeil Armstrong .frac = { 2370058502fSNeil Armstrong .reg_off = HHI_HDMI_PLL_CNTL2, 2380058502fSNeil Armstrong .shift = 0, 23921310c39SNeil Armstrong .width = 10, 2400058502fSNeil Armstrong }, 2410058502fSNeil Armstrong .l = { 2420058502fSNeil Armstrong .reg_off = HHI_HDMI_PLL_CNTL, 2430058502fSNeil Armstrong .shift = 31, 2440058502fSNeil Armstrong .width = 1, 2450058502fSNeil Armstrong }, 2460058502fSNeil Armstrong .rst = { 2470058502fSNeil Armstrong .reg_off = HHI_HDMI_PLL_CNTL, 2480058502fSNeil Armstrong .shift = 28, 2490058502fSNeil Armstrong .width = 1, 2500058502fSNeil Armstrong }, 2510058502fSNeil Armstrong }, 2520058502fSNeil Armstrong .hw.init = &(struct clk_init_data){ 2530058502fSNeil Armstrong .name = "hdmi_pll_dco", 2540058502fSNeil Armstrong .ops = &meson_clk_pll_ro_ops, 2550dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 2560dea3f35SAlexandre Mergnat .fw_name = "xtal", 2570dea3f35SAlexandre Mergnat }, 2580058502fSNeil Armstrong .num_parents = 1, 2590058502fSNeil Armstrong /* 2600058502fSNeil Armstrong * Display directly handle hdmi pll registers ATM, we need 2610058502fSNeil Armstrong * NOCACHE to keep our view of the clock as accurate as possible 2620058502fSNeil Armstrong */ 2630058502fSNeil Armstrong .flags = CLK_GET_RATE_NOCACHE, 2640058502fSNeil Armstrong }, 2650058502fSNeil Armstrong }; 2660058502fSNeil Armstrong 26787173557SJerome Brunet static struct clk_regmap gxbb_hdmi_pll_od = { 26887173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 26987173557SJerome Brunet .offset = HHI_HDMI_PLL_CNTL2, 27087173557SJerome Brunet .shift = 16, 27187173557SJerome Brunet .width = 2, 27287173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 27387173557SJerome Brunet }, 27487173557SJerome Brunet .hw.init = &(struct clk_init_data){ 27587173557SJerome Brunet .name = "hdmi_pll_od", 27687173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 2770dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 2780dea3f35SAlexandre Mergnat &gxbb_hdmi_pll_dco.hw 2790dea3f35SAlexandre Mergnat }, 28087173557SJerome Brunet .num_parents = 1, 28187173557SJerome Brunet .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 28287173557SJerome Brunet }, 28387173557SJerome Brunet }; 28487173557SJerome Brunet 28587173557SJerome Brunet static struct clk_regmap gxbb_hdmi_pll_od2 = { 28687173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 28787173557SJerome Brunet .offset = HHI_HDMI_PLL_CNTL2, 28887173557SJerome Brunet .shift = 22, 28987173557SJerome Brunet .width = 2, 29087173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 29187173557SJerome Brunet }, 29287173557SJerome Brunet .hw.init = &(struct clk_init_data){ 29387173557SJerome Brunet .name = "hdmi_pll_od2", 29487173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 2950dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 2960dea3f35SAlexandre Mergnat &gxbb_hdmi_pll_od.hw 2970dea3f35SAlexandre Mergnat }, 29887173557SJerome Brunet .num_parents = 1, 29987173557SJerome Brunet .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 30087173557SJerome Brunet }, 30187173557SJerome Brunet }; 30287173557SJerome Brunet 30387173557SJerome Brunet static struct clk_regmap gxbb_hdmi_pll = { 30487173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 30587173557SJerome Brunet .offset = HHI_HDMI_PLL_CNTL2, 30687173557SJerome Brunet .shift = 18, 30787173557SJerome Brunet .width = 2, 30887173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 30987173557SJerome Brunet }, 31087173557SJerome Brunet .hw.init = &(struct clk_init_data){ 31187173557SJerome Brunet .name = "hdmi_pll", 31287173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 3130dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 3140dea3f35SAlexandre Mergnat &gxbb_hdmi_pll_od2.hw 3150dea3f35SAlexandre Mergnat }, 31687173557SJerome Brunet .num_parents = 1, 31787173557SJerome Brunet .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 31887173557SJerome Brunet }, 31987173557SJerome Brunet }; 32087173557SJerome Brunet 32187173557SJerome Brunet static struct clk_regmap gxl_hdmi_pll_od = { 32287173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 32387173557SJerome Brunet .offset = HHI_HDMI_PLL_CNTL + 8, 32487173557SJerome Brunet .shift = 21, 32587173557SJerome Brunet .width = 2, 32687173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 32787173557SJerome Brunet }, 32887173557SJerome Brunet .hw.init = &(struct clk_init_data){ 32987173557SJerome Brunet .name = "hdmi_pll_od", 33087173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 3310dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 3320dea3f35SAlexandre Mergnat &gxl_hdmi_pll_dco.hw 3330dea3f35SAlexandre Mergnat }, 33487173557SJerome Brunet .num_parents = 1, 33587173557SJerome Brunet .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 33687173557SJerome Brunet }, 33787173557SJerome Brunet }; 33887173557SJerome Brunet 33987173557SJerome Brunet static struct clk_regmap gxl_hdmi_pll_od2 = { 34087173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 34187173557SJerome Brunet .offset = HHI_HDMI_PLL_CNTL + 8, 34287173557SJerome Brunet .shift = 23, 34387173557SJerome Brunet .width = 2, 34487173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 34587173557SJerome Brunet }, 34687173557SJerome Brunet .hw.init = &(struct clk_init_data){ 34787173557SJerome Brunet .name = "hdmi_pll_od2", 34887173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 3490dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 3500dea3f35SAlexandre Mergnat &gxl_hdmi_pll_od.hw 3510dea3f35SAlexandre Mergnat }, 35287173557SJerome Brunet .num_parents = 1, 35387173557SJerome Brunet .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 35487173557SJerome Brunet }, 35587173557SJerome Brunet }; 35687173557SJerome Brunet 357722825dcSJerome Brunet static struct clk_regmap gxl_hdmi_pll = { 35887173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 35987173557SJerome Brunet .offset = HHI_HDMI_PLL_CNTL + 8, 36087173557SJerome Brunet .shift = 19, 36187173557SJerome Brunet .width = 2, 36287173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 36387173557SJerome Brunet }, 36487173557SJerome Brunet .hw.init = &(struct clk_init_data){ 36587173557SJerome Brunet .name = "hdmi_pll", 36687173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 3670dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 3680dea3f35SAlexandre Mergnat &gxl_hdmi_pll_od2.hw 3690dea3f35SAlexandre Mergnat }, 37087173557SJerome Brunet .num_parents = 1, 37187173557SJerome Brunet .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 37287173557SJerome Brunet }, 37387173557SJerome Brunet }; 37487173557SJerome Brunet 37587173557SJerome Brunet static struct clk_regmap gxbb_sys_pll_dco = { 376722825dcSJerome Brunet .data = &(struct meson_clk_pll_data){ 377e40c7e3cSJerome Brunet .en = { 37887173557SJerome Brunet .reg_off = HHI_SYS_PLL_CNTL, 379e40c7e3cSJerome Brunet .shift = 30, 380e40c7e3cSJerome Brunet .width = 1, 381e40c7e3cSJerome Brunet }, 38269d92293SJerome Brunet .m = { 38387173557SJerome Brunet .reg_off = HHI_SYS_PLL_CNTL, 38469d92293SJerome Brunet .shift = 0, 38569d92293SJerome Brunet .width = 9, 38669d92293SJerome Brunet }, 38769d92293SJerome Brunet .n = { 38887173557SJerome Brunet .reg_off = HHI_SYS_PLL_CNTL, 38969d92293SJerome Brunet .shift = 9, 39069d92293SJerome Brunet .width = 5, 39169d92293SJerome Brunet }, 392722825dcSJerome Brunet .l = { 39387173557SJerome Brunet .reg_off = HHI_SYS_PLL_CNTL, 394722825dcSJerome Brunet .shift = 31, 395722825dcSJerome Brunet .width = 1, 396722825dcSJerome Brunet }, 397722825dcSJerome Brunet .rst = { 39887173557SJerome Brunet .reg_off = HHI_SYS_PLL_CNTL, 399722825dcSJerome Brunet .shift = 29, 400722825dcSJerome Brunet .width = 1, 401722825dcSJerome Brunet }, 402722825dcSJerome Brunet }, 40369d92293SJerome Brunet .hw.init = &(struct clk_init_data){ 40487173557SJerome Brunet .name = "sys_pll_dco", 40569d92293SJerome Brunet .ops = &meson_clk_pll_ro_ops, 4060dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 4070dea3f35SAlexandre Mergnat .fw_name = "xtal", 4080dea3f35SAlexandre Mergnat }, 40969d92293SJerome Brunet .num_parents = 1, 41069d92293SJerome Brunet }, 41169d92293SJerome Brunet }; 41269d92293SJerome Brunet 413722825dcSJerome Brunet static struct clk_regmap gxbb_sys_pll = { 41487173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 41587173557SJerome Brunet .offset = HHI_SYS_PLL_CNTL, 416738f66d3SMichael Turquette .shift = 10, 417738f66d3SMichael Turquette .width = 2, 41887173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 419722825dcSJerome Brunet }, 420738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 421738f66d3SMichael Turquette .name = "sys_pll", 42287173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 4230dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 4240dea3f35SAlexandre Mergnat &gxbb_sys_pll_dco.hw 4250dea3f35SAlexandre Mergnat }, 426738f66d3SMichael Turquette .num_parents = 1, 42787173557SJerome Brunet .flags = CLK_SET_RATE_PARENT, 428738f66d3SMichael Turquette }, 429738f66d3SMichael Turquette }; 430738f66d3SMichael Turquette 4315d1c04ddSStephen Boyd static const struct reg_sequence gxbb_gp0_init_regs[] = { 432722825dcSJerome Brunet { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 }, 433722825dcSJerome Brunet { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 }, 434722825dcSJerome Brunet { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d }, 435e194401cSNeil Armstrong }; 436e194401cSNeil Armstrong 43787173557SJerome Brunet static struct clk_regmap gxbb_gp0_pll_dco = { 438722825dcSJerome Brunet .data = &(struct meson_clk_pll_data){ 439e40c7e3cSJerome Brunet .en = { 440e40c7e3cSJerome Brunet .reg_off = HHI_GP0_PLL_CNTL, 441e40c7e3cSJerome Brunet .shift = 30, 442e40c7e3cSJerome Brunet .width = 1, 443e40c7e3cSJerome Brunet }, 444738f66d3SMichael Turquette .m = { 445738f66d3SMichael Turquette .reg_off = HHI_GP0_PLL_CNTL, 446738f66d3SMichael Turquette .shift = 0, 447738f66d3SMichael Turquette .width = 9, 448738f66d3SMichael Turquette }, 449738f66d3SMichael Turquette .n = { 450738f66d3SMichael Turquette .reg_off = HHI_GP0_PLL_CNTL, 451738f66d3SMichael Turquette .shift = 9, 452738f66d3SMichael Turquette .width = 5, 453738f66d3SMichael Turquette }, 454722825dcSJerome Brunet .l = { 455722825dcSJerome Brunet .reg_off = HHI_GP0_PLL_CNTL, 456722825dcSJerome Brunet .shift = 31, 457722825dcSJerome Brunet .width = 1, 458e194401cSNeil Armstrong }, 459722825dcSJerome Brunet .rst = { 460722825dcSJerome Brunet .reg_off = HHI_GP0_PLL_CNTL, 461722825dcSJerome Brunet .shift = 29, 462722825dcSJerome Brunet .width = 1, 463722825dcSJerome Brunet }, 464dd601dbcSJerome Brunet .table = gxbb_gp0_pll_params_table, 465722825dcSJerome Brunet .init_regs = gxbb_gp0_init_regs, 466722825dcSJerome Brunet .init_count = ARRAY_SIZE(gxbb_gp0_init_regs), 467722825dcSJerome Brunet }, 4680d48fc55SNeil Armstrong .hw.init = &(struct clk_init_data){ 46987173557SJerome Brunet .name = "gp0_pll_dco", 4700d48fc55SNeil Armstrong .ops = &meson_clk_pll_ops, 4710dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 4720dea3f35SAlexandre Mergnat .fw_name = "xtal", 4730dea3f35SAlexandre Mergnat }, 4740d48fc55SNeil Armstrong .num_parents = 1, 4750d48fc55SNeil Armstrong }, 4760d48fc55SNeil Armstrong }; 4770d48fc55SNeil Armstrong 4785d1c04ddSStephen Boyd static const struct reg_sequence gxl_gp0_init_regs[] = { 479c77de0e5SJerome Brunet { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 }, 480722825dcSJerome Brunet { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, 481722825dcSJerome Brunet { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, 482722825dcSJerome Brunet { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, 483722825dcSJerome Brunet { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, 4840d48fc55SNeil Armstrong }; 4850d48fc55SNeil Armstrong 48687173557SJerome Brunet static struct clk_regmap gxl_gp0_pll_dco = { 487722825dcSJerome Brunet .data = &(struct meson_clk_pll_data){ 488e40c7e3cSJerome Brunet .en = { 489e40c7e3cSJerome Brunet .reg_off = HHI_GP0_PLL_CNTL, 490e40c7e3cSJerome Brunet .shift = 30, 491e40c7e3cSJerome Brunet .width = 1, 492e40c7e3cSJerome Brunet }, 4930d48fc55SNeil Armstrong .m = { 4940d48fc55SNeil Armstrong .reg_off = HHI_GP0_PLL_CNTL, 4950d48fc55SNeil Armstrong .shift = 0, 4960d48fc55SNeil Armstrong .width = 9, 4970d48fc55SNeil Armstrong }, 4980d48fc55SNeil Armstrong .n = { 4990d48fc55SNeil Armstrong .reg_off = HHI_GP0_PLL_CNTL, 5000d48fc55SNeil Armstrong .shift = 9, 5010d48fc55SNeil Armstrong .width = 5, 5020d48fc55SNeil Armstrong }, 503c77de0e5SJerome Brunet .frac = { 504c77de0e5SJerome Brunet .reg_off = HHI_GP0_PLL_CNTL1, 505c77de0e5SJerome Brunet .shift = 0, 506c77de0e5SJerome Brunet .width = 10, 507c77de0e5SJerome Brunet }, 508722825dcSJerome Brunet .l = { 509722825dcSJerome Brunet .reg_off = HHI_GP0_PLL_CNTL, 510722825dcSJerome Brunet .shift = 31, 511722825dcSJerome Brunet .width = 1, 5120d48fc55SNeil Armstrong }, 513722825dcSJerome Brunet .rst = { 514722825dcSJerome Brunet .reg_off = HHI_GP0_PLL_CNTL, 515722825dcSJerome Brunet .shift = 29, 516722825dcSJerome Brunet .width = 1, 517722825dcSJerome Brunet }, 518dd601dbcSJerome Brunet .table = gxl_gp0_pll_params_table, 519722825dcSJerome Brunet .init_regs = gxl_gp0_init_regs, 520722825dcSJerome Brunet .init_count = ARRAY_SIZE(gxl_gp0_init_regs), 521722825dcSJerome Brunet }, 522738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 52387173557SJerome Brunet .name = "gp0_pll_dco", 524738f66d3SMichael Turquette .ops = &meson_clk_pll_ops, 5250dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 5260dea3f35SAlexandre Mergnat .fw_name = "xtal", 5270dea3f35SAlexandre Mergnat }, 528738f66d3SMichael Turquette .num_parents = 1, 529738f66d3SMichael Turquette }, 530738f66d3SMichael Turquette }; 531738f66d3SMichael Turquette 53287173557SJerome Brunet static struct clk_regmap gxbb_gp0_pll = { 53387173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 53487173557SJerome Brunet .offset = HHI_GP0_PLL_CNTL, 53587173557SJerome Brunet .shift = 16, 53687173557SJerome Brunet .width = 2, 53787173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 53887173557SJerome Brunet }, 53987173557SJerome Brunet .hw.init = &(struct clk_init_data){ 54087173557SJerome Brunet .name = "gp0_pll", 54187173557SJerome Brunet .ops = &clk_regmap_divider_ops, 5420dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 5430dea3f35SAlexandre Mergnat /* 5440dea3f35SAlexandre Mergnat * Note: 5450dea3f35SAlexandre Mergnat * GXL and GXBB have different gp0_pll_dco (with 5460dea3f35SAlexandre Mergnat * different struct clk_hw). We fallback to the global 5470dea3f35SAlexandre Mergnat * naming string mechanism so gp0_pll picks up the 5480dea3f35SAlexandre Mergnat * appropriate one. 5490dea3f35SAlexandre Mergnat */ 5500dea3f35SAlexandre Mergnat .name = "gp0_pll_dco", 5510dea3f35SAlexandre Mergnat .index = -1, 5520dea3f35SAlexandre Mergnat }, 55387173557SJerome Brunet .num_parents = 1, 55487173557SJerome Brunet .flags = CLK_SET_RATE_PARENT, 55587173557SJerome Brunet }, 55687173557SJerome Brunet }; 55787173557SJerome Brunet 55805f81440SJerome Brunet static struct clk_fixed_factor gxbb_fclk_div2_div = { 559738f66d3SMichael Turquette .mult = 1, 560738f66d3SMichael Turquette .div = 2, 561738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 56205f81440SJerome Brunet .name = "fclk_div2_div", 563738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 5640dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 5650dea3f35SAlexandre Mergnat &gxbb_fixed_pll.hw 5660dea3f35SAlexandre Mergnat }, 567738f66d3SMichael Turquette .num_parents = 1, 568738f66d3SMichael Turquette }, 569738f66d3SMichael Turquette }; 570738f66d3SMichael Turquette 57105f81440SJerome Brunet static struct clk_regmap gxbb_fclk_div2 = { 57205f81440SJerome Brunet .data = &(struct clk_regmap_gate_data){ 57305f81440SJerome Brunet .offset = HHI_MPLL_CNTL6, 57405f81440SJerome Brunet .bit_idx = 27, 57505f81440SJerome Brunet }, 57605f81440SJerome Brunet .hw.init = &(struct clk_init_data){ 57705f81440SJerome Brunet .name = "fclk_div2", 57805f81440SJerome Brunet .ops = &clk_regmap_gate_ops, 5790dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 5800dea3f35SAlexandre Mergnat &gxbb_fclk_div2_div.hw 5810dea3f35SAlexandre Mergnat }, 58205f81440SJerome Brunet .num_parents = 1, 583c987ac6fSNeil Armstrong .flags = CLK_IS_CRITICAL, 58405f81440SJerome Brunet }, 58505f81440SJerome Brunet }; 58605f81440SJerome Brunet 58705f81440SJerome Brunet static struct clk_fixed_factor gxbb_fclk_div3_div = { 588738f66d3SMichael Turquette .mult = 1, 589738f66d3SMichael Turquette .div = 3, 590738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 59105f81440SJerome Brunet .name = "fclk_div3_div", 592738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 5930dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 594738f66d3SMichael Turquette .num_parents = 1, 595738f66d3SMichael Turquette }, 596738f66d3SMichael Turquette }; 597738f66d3SMichael Turquette 59805f81440SJerome Brunet static struct clk_regmap gxbb_fclk_div3 = { 59905f81440SJerome Brunet .data = &(struct clk_regmap_gate_data){ 60005f81440SJerome Brunet .offset = HHI_MPLL_CNTL6, 60105f81440SJerome Brunet .bit_idx = 28, 60205f81440SJerome Brunet }, 60305f81440SJerome Brunet .hw.init = &(struct clk_init_data){ 60405f81440SJerome Brunet .name = "fclk_div3", 60505f81440SJerome Brunet .ops = &clk_regmap_gate_ops, 6060dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 6070dea3f35SAlexandre Mergnat &gxbb_fclk_div3_div.hw 6080dea3f35SAlexandre Mergnat }, 60905f81440SJerome Brunet .num_parents = 1, 610e2576c8bSChristian Hewitt /* 611e2576c8bSChristian Hewitt * FIXME: 612e2576c8bSChristian Hewitt * This clock, as fdiv2, is used by the SCPI FW and is required 613e2576c8bSChristian Hewitt * by the platform to operate correctly. 614e2576c8bSChristian Hewitt * Until the following condition are met, we need this clock to 615e2576c8bSChristian Hewitt * be marked as critical: 616e2576c8bSChristian Hewitt * a) The SCPI generic driver claims and enable all the clocks 617e2576c8bSChristian Hewitt * it needs 618e2576c8bSChristian Hewitt * b) CCF has a clock hand-off mechanism to make the sure the 619e2576c8bSChristian Hewitt * clock stays on until the proper driver comes along 620e2576c8bSChristian Hewitt */ 621e2576c8bSChristian Hewitt .flags = CLK_IS_CRITICAL, 62205f81440SJerome Brunet }, 62305f81440SJerome Brunet }; 62405f81440SJerome Brunet 62505f81440SJerome Brunet static struct clk_fixed_factor gxbb_fclk_div4_div = { 626738f66d3SMichael Turquette .mult = 1, 627738f66d3SMichael Turquette .div = 4, 628738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 62905f81440SJerome Brunet .name = "fclk_div4_div", 630738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 6310dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 632738f66d3SMichael Turquette .num_parents = 1, 633738f66d3SMichael Turquette }, 634738f66d3SMichael Turquette }; 635738f66d3SMichael Turquette 63605f81440SJerome Brunet static struct clk_regmap gxbb_fclk_div4 = { 63705f81440SJerome Brunet .data = &(struct clk_regmap_gate_data){ 63805f81440SJerome Brunet .offset = HHI_MPLL_CNTL6, 63905f81440SJerome Brunet .bit_idx = 29, 64005f81440SJerome Brunet }, 64105f81440SJerome Brunet .hw.init = &(struct clk_init_data){ 64205f81440SJerome Brunet .name = "fclk_div4", 64305f81440SJerome Brunet .ops = &clk_regmap_gate_ops, 6440dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 6450dea3f35SAlexandre Mergnat &gxbb_fclk_div4_div.hw 6460dea3f35SAlexandre Mergnat }, 64705f81440SJerome Brunet .num_parents = 1, 64805f81440SJerome Brunet }, 64905f81440SJerome Brunet }; 65005f81440SJerome Brunet 65105f81440SJerome Brunet static struct clk_fixed_factor gxbb_fclk_div5_div = { 652738f66d3SMichael Turquette .mult = 1, 653738f66d3SMichael Turquette .div = 5, 654738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 65505f81440SJerome Brunet .name = "fclk_div5_div", 656738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 6570dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 658738f66d3SMichael Turquette .num_parents = 1, 659738f66d3SMichael Turquette }, 660738f66d3SMichael Turquette }; 661738f66d3SMichael Turquette 66205f81440SJerome Brunet static struct clk_regmap gxbb_fclk_div5 = { 66305f81440SJerome Brunet .data = &(struct clk_regmap_gate_data){ 66405f81440SJerome Brunet .offset = HHI_MPLL_CNTL6, 66505f81440SJerome Brunet .bit_idx = 30, 66605f81440SJerome Brunet }, 66705f81440SJerome Brunet .hw.init = &(struct clk_init_data){ 66805f81440SJerome Brunet .name = "fclk_div5", 66905f81440SJerome Brunet .ops = &clk_regmap_gate_ops, 6700dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 6710dea3f35SAlexandre Mergnat &gxbb_fclk_div5_div.hw 6720dea3f35SAlexandre Mergnat }, 67305f81440SJerome Brunet .num_parents = 1, 67405f81440SJerome Brunet }, 67505f81440SJerome Brunet }; 67605f81440SJerome Brunet 67705f81440SJerome Brunet static struct clk_fixed_factor gxbb_fclk_div7_div = { 678738f66d3SMichael Turquette .mult = 1, 679738f66d3SMichael Turquette .div = 7, 680738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 68105f81440SJerome Brunet .name = "fclk_div7_div", 682738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 6830dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 684738f66d3SMichael Turquette .num_parents = 1, 685738f66d3SMichael Turquette }, 686738f66d3SMichael Turquette }; 687738f66d3SMichael Turquette 68805f81440SJerome Brunet static struct clk_regmap gxbb_fclk_div7 = { 68905f81440SJerome Brunet .data = &(struct clk_regmap_gate_data){ 69005f81440SJerome Brunet .offset = HHI_MPLL_CNTL6, 69105f81440SJerome Brunet .bit_idx = 31, 69205f81440SJerome Brunet }, 69305f81440SJerome Brunet .hw.init = &(struct clk_init_data){ 69405f81440SJerome Brunet .name = "fclk_div7", 69505f81440SJerome Brunet .ops = &clk_regmap_gate_ops, 6960dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 6970dea3f35SAlexandre Mergnat &gxbb_fclk_div7_div.hw 6980dea3f35SAlexandre Mergnat }, 69905f81440SJerome Brunet .num_parents = 1, 70005f81440SJerome Brunet }, 70105f81440SJerome Brunet }; 70205f81440SJerome Brunet 703513b67acSJerome Brunet static struct clk_regmap gxbb_mpll_prediv = { 704513b67acSJerome Brunet .data = &(struct clk_regmap_div_data){ 705513b67acSJerome Brunet .offset = HHI_MPLL_CNTL5, 706513b67acSJerome Brunet .shift = 12, 707513b67acSJerome Brunet .width = 1, 708513b67acSJerome Brunet }, 709513b67acSJerome Brunet .hw.init = &(struct clk_init_data){ 710513b67acSJerome Brunet .name = "mpll_prediv", 711513b67acSJerome Brunet .ops = &clk_regmap_divider_ro_ops, 7120dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 713513b67acSJerome Brunet .num_parents = 1, 714513b67acSJerome Brunet }, 715513b67acSJerome Brunet }; 716513b67acSJerome Brunet 717d610b54fSJerome Brunet static struct clk_regmap gxbb_mpll0_div = { 718c763e61aSJerome Brunet .data = &(struct meson_clk_mpll_data){ 719738f66d3SMichael Turquette .sdm = { 720738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL7, 721738f66d3SMichael Turquette .shift = 0, 722738f66d3SMichael Turquette .width = 14, 723738f66d3SMichael Turquette }, 724007e6e5cSJerome Brunet .sdm_en = { 725ff54938dSMartin Blumenstingl .reg_off = HHI_MPLL_CNTL, 726ff54938dSMartin Blumenstingl .shift = 25, 727ff54938dSMartin Blumenstingl .width = 1, 728ff54938dSMartin Blumenstingl }, 729ff54938dSMartin Blumenstingl .n2 = { 730ff54938dSMartin Blumenstingl .reg_off = HHI_MPLL_CNTL7, 731ff54938dSMartin Blumenstingl .shift = 16, 732ff54938dSMartin Blumenstingl .width = 9, 733ff54938dSMartin Blumenstingl }, 734ff54938dSMartin Blumenstingl .lock = &meson_clk_lock, 735ff54938dSMartin Blumenstingl }, 736ff54938dSMartin Blumenstingl .hw.init = &(struct clk_init_data){ 737ff54938dSMartin Blumenstingl .name = "mpll0_div", 738ff54938dSMartin Blumenstingl .ops = &meson_clk_mpll_ops, 739ff54938dSMartin Blumenstingl .parent_hws = (const struct clk_hw *[]) { 740ff54938dSMartin Blumenstingl &gxbb_mpll_prediv.hw 741ff54938dSMartin Blumenstingl }, 742ff54938dSMartin Blumenstingl .num_parents = 1, 743ff54938dSMartin Blumenstingl }, 744ff54938dSMartin Blumenstingl }; 745ff54938dSMartin Blumenstingl 746ff54938dSMartin Blumenstingl static struct clk_regmap gxl_mpll0_div = { 747ff54938dSMartin Blumenstingl .data = &(struct meson_clk_mpll_data){ 748ff54938dSMartin Blumenstingl .sdm = { 749ff54938dSMartin Blumenstingl .reg_off = HHI_MPLL_CNTL7, 750ff54938dSMartin Blumenstingl .shift = 0, 751ff54938dSMartin Blumenstingl .width = 14, 752ff54938dSMartin Blumenstingl }, 753ff54938dSMartin Blumenstingl .sdm_en = { 754007e6e5cSJerome Brunet .reg_off = HHI_MPLL_CNTL7, 755007e6e5cSJerome Brunet .shift = 15, 756007e6e5cSJerome Brunet .width = 1, 757007e6e5cSJerome Brunet }, 758738f66d3SMichael Turquette .n2 = { 759738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL7, 760738f66d3SMichael Turquette .shift = 16, 761738f66d3SMichael Turquette .width = 9, 762738f66d3SMichael Turquette }, 76327aad905SYixun Lan .lock = &meson_clk_lock, 764c763e61aSJerome Brunet }, 765738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 766d610b54fSJerome Brunet .name = "mpll0_div", 767d610b54fSJerome Brunet .ops = &meson_clk_mpll_ops, 7680dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 7690dea3f35SAlexandre Mergnat &gxbb_mpll_prediv.hw 7700dea3f35SAlexandre Mergnat }, 771d610b54fSJerome Brunet .num_parents = 1, 772d610b54fSJerome Brunet }, 773d610b54fSJerome Brunet }; 774d610b54fSJerome Brunet 775d610b54fSJerome Brunet static struct clk_regmap gxbb_mpll0 = { 776d610b54fSJerome Brunet .data = &(struct clk_regmap_gate_data){ 777d610b54fSJerome Brunet .offset = HHI_MPLL_CNTL7, 778d610b54fSJerome Brunet .bit_idx = 14, 779d610b54fSJerome Brunet }, 780d610b54fSJerome Brunet .hw.init = &(struct clk_init_data){ 781738f66d3SMichael Turquette .name = "mpll0", 782d610b54fSJerome Brunet .ops = &clk_regmap_gate_ops, 783ff54938dSMartin Blumenstingl .parent_data = &(const struct clk_parent_data) { 784ff54938dSMartin Blumenstingl /* 785ff54938dSMartin Blumenstingl * Note: 786ff54938dSMartin Blumenstingl * GXL and GXBB have different SDM_EN registers. We 787ff54938dSMartin Blumenstingl * fallback to the global naming string mechanism so 788ff54938dSMartin Blumenstingl * mpll0_div picks up the appropriate one. 789ff54938dSMartin Blumenstingl */ 790ff54938dSMartin Blumenstingl .name = "mpll0_div", 791ff54938dSMartin Blumenstingl .index = -1, 792ff54938dSMartin Blumenstingl }, 793d610b54fSJerome Brunet .num_parents = 1, 794d610b54fSJerome Brunet .flags = CLK_SET_RATE_PARENT, 795d610b54fSJerome Brunet }, 796d610b54fSJerome Brunet }; 797d610b54fSJerome Brunet 798d610b54fSJerome Brunet static struct clk_regmap gxbb_mpll1_div = { 799d610b54fSJerome Brunet .data = &(struct meson_clk_mpll_data){ 800d610b54fSJerome Brunet .sdm = { 801d610b54fSJerome Brunet .reg_off = HHI_MPLL_CNTL8, 802d610b54fSJerome Brunet .shift = 0, 803d610b54fSJerome Brunet .width = 14, 804d610b54fSJerome Brunet }, 805d610b54fSJerome Brunet .sdm_en = { 806d610b54fSJerome Brunet .reg_off = HHI_MPLL_CNTL8, 807d610b54fSJerome Brunet .shift = 15, 808d610b54fSJerome Brunet .width = 1, 809d610b54fSJerome Brunet }, 810d610b54fSJerome Brunet .n2 = { 811d610b54fSJerome Brunet .reg_off = HHI_MPLL_CNTL8, 812d610b54fSJerome Brunet .shift = 16, 813d610b54fSJerome Brunet .width = 9, 814d610b54fSJerome Brunet }, 815d610b54fSJerome Brunet .lock = &meson_clk_lock, 816d610b54fSJerome Brunet }, 817d610b54fSJerome Brunet .hw.init = &(struct clk_init_data){ 818d610b54fSJerome Brunet .name = "mpll1_div", 81905b43aa2SJerome Brunet .ops = &meson_clk_mpll_ops, 8200dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 8210dea3f35SAlexandre Mergnat &gxbb_mpll_prediv.hw 8220dea3f35SAlexandre Mergnat }, 823738f66d3SMichael Turquette .num_parents = 1, 824738f66d3SMichael Turquette }, 825738f66d3SMichael Turquette }; 826738f66d3SMichael Turquette 827c763e61aSJerome Brunet static struct clk_regmap gxbb_mpll1 = { 828d610b54fSJerome Brunet .data = &(struct clk_regmap_gate_data){ 829d610b54fSJerome Brunet .offset = HHI_MPLL_CNTL8, 830d610b54fSJerome Brunet .bit_idx = 14, 831d610b54fSJerome Brunet }, 832d610b54fSJerome Brunet .hw.init = &(struct clk_init_data){ 833d610b54fSJerome Brunet .name = "mpll1", 834d610b54fSJerome Brunet .ops = &clk_regmap_gate_ops, 8350dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll1_div.hw }, 836d610b54fSJerome Brunet .num_parents = 1, 837d610b54fSJerome Brunet .flags = CLK_SET_RATE_PARENT, 838d610b54fSJerome Brunet }, 839d610b54fSJerome Brunet }; 840d610b54fSJerome Brunet 841d610b54fSJerome Brunet static struct clk_regmap gxbb_mpll2_div = { 842c763e61aSJerome Brunet .data = &(struct meson_clk_mpll_data){ 843738f66d3SMichael Turquette .sdm = { 844d610b54fSJerome Brunet .reg_off = HHI_MPLL_CNTL9, 845738f66d3SMichael Turquette .shift = 0, 846738f66d3SMichael Turquette .width = 14, 847738f66d3SMichael Turquette }, 848007e6e5cSJerome Brunet .sdm_en = { 849d610b54fSJerome Brunet .reg_off = HHI_MPLL_CNTL9, 850007e6e5cSJerome Brunet .shift = 15, 851007e6e5cSJerome Brunet .width = 1, 852007e6e5cSJerome Brunet }, 853738f66d3SMichael Turquette .n2 = { 854d610b54fSJerome Brunet .reg_off = HHI_MPLL_CNTL9, 855738f66d3SMichael Turquette .shift = 16, 856738f66d3SMichael Turquette .width = 9, 857738f66d3SMichael Turquette }, 85827aad905SYixun Lan .lock = &meson_clk_lock, 859c763e61aSJerome Brunet }, 860738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 861d610b54fSJerome Brunet .name = "mpll2_div", 86205b43aa2SJerome Brunet .ops = &meson_clk_mpll_ops, 8630dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 8640dea3f35SAlexandre Mergnat &gxbb_mpll_prediv.hw 8650dea3f35SAlexandre Mergnat }, 866738f66d3SMichael Turquette .num_parents = 1, 867738f66d3SMichael Turquette }, 868738f66d3SMichael Turquette }; 869738f66d3SMichael Turquette 870c763e61aSJerome Brunet static struct clk_regmap gxbb_mpll2 = { 871d610b54fSJerome Brunet .data = &(struct clk_regmap_gate_data){ 872d610b54fSJerome Brunet .offset = HHI_MPLL_CNTL9, 873d610b54fSJerome Brunet .bit_idx = 14, 874c763e61aSJerome Brunet }, 875738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 876738f66d3SMichael Turquette .name = "mpll2", 877d610b54fSJerome Brunet .ops = &clk_regmap_gate_ops, 8780dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll2_div.hw }, 879738f66d3SMichael Turquette .num_parents = 1, 880d610b54fSJerome Brunet .flags = CLK_SET_RATE_PARENT, 881738f66d3SMichael Turquette }, 882738f66d3SMichael Turquette }; 883738f66d3SMichael Turquette 884215c80a7SJerome Brunet static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; 8850dea3f35SAlexandre Mergnat static const struct clk_parent_data clk81_parent_data[] = { 8860dea3f35SAlexandre Mergnat { .fw_name = "xtal", }, 8870dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div7.hw }, 8880dea3f35SAlexandre Mergnat { .hw = &gxbb_mpll1.hw }, 8890dea3f35SAlexandre Mergnat { .hw = &gxbb_mpll2.hw }, 8900dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div4.hw }, 8910dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div3.hw }, 8920dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div5.hw }, 893215c80a7SJerome Brunet }; 894738f66d3SMichael Turquette 8952513a28cSJerome Brunet static struct clk_regmap gxbb_mpeg_clk_sel = { 8962513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 8972513a28cSJerome Brunet .offset = HHI_MPEG_CLK_CNTL, 898738f66d3SMichael Turquette .mask = 0x7, 899738f66d3SMichael Turquette .shift = 12, 900738f66d3SMichael Turquette .table = mux_table_clk81, 9012513a28cSJerome Brunet }, 902738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 903738f66d3SMichael Turquette .name = "mpeg_clk_sel", 9042513a28cSJerome Brunet .ops = &clk_regmap_mux_ro_ops, 905738f66d3SMichael Turquette /* 906215c80a7SJerome Brunet * bits 14:12 selects from 8 possible parents: 907738f66d3SMichael Turquette * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, 908738f66d3SMichael Turquette * fclk_div4, fclk_div3, fclk_div5 909738f66d3SMichael Turquette */ 9100dea3f35SAlexandre Mergnat .parent_data = clk81_parent_data, 9110dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(clk81_parent_data), 912738f66d3SMichael Turquette }, 913738f66d3SMichael Turquette }; 914738f66d3SMichael Turquette 915f06ddd28SJerome Brunet static struct clk_regmap gxbb_mpeg_clk_div = { 916f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 917f06ddd28SJerome Brunet .offset = HHI_MPEG_CLK_CNTL, 918738f66d3SMichael Turquette .shift = 0, 919738f66d3SMichael Turquette .width = 7, 920f06ddd28SJerome Brunet }, 921738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 922738f66d3SMichael Turquette .name = "mpeg_clk_div", 9235b13ef64SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 9240dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 9250dea3f35SAlexandre Mergnat &gxbb_mpeg_clk_sel.hw 9260dea3f35SAlexandre Mergnat }, 927738f66d3SMichael Turquette .num_parents = 1, 928738f66d3SMichael Turquette }, 929738f66d3SMichael Turquette }; 930738f66d3SMichael Turquette 9317f9768a5SJerome Brunet /* the mother of dragons gates */ 9327f9768a5SJerome Brunet static struct clk_regmap gxbb_clk81 = { 9337f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 9347f9768a5SJerome Brunet .offset = HHI_MPEG_CLK_CNTL, 935738f66d3SMichael Turquette .bit_idx = 7, 9367f9768a5SJerome Brunet }, 937738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 938738f66d3SMichael Turquette .name = "clk81", 9397f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 9400dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 9410dea3f35SAlexandre Mergnat &gxbb_mpeg_clk_div.hw 9420dea3f35SAlexandre Mergnat }, 943738f66d3SMichael Turquette .num_parents = 1, 9445b13ef64SJerome Brunet .flags = CLK_IS_CRITICAL, 945738f66d3SMichael Turquette }, 946738f66d3SMichael Turquette }; 947738f66d3SMichael Turquette 9482513a28cSJerome Brunet static struct clk_regmap gxbb_sar_adc_clk_sel = { 9492513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 9502513a28cSJerome Brunet .offset = HHI_SAR_CLK_CNTL, 95133d0fcdfSMartin Blumenstingl .mask = 0x3, 95233d0fcdfSMartin Blumenstingl .shift = 9, 9532513a28cSJerome Brunet }, 95433d0fcdfSMartin Blumenstingl .hw.init = &(struct clk_init_data){ 95533d0fcdfSMartin Blumenstingl .name = "sar_adc_clk_sel", 9562513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 95733d0fcdfSMartin Blumenstingl /* NOTE: The datasheet doesn't list the parents for bit 10 */ 9580dea3f35SAlexandre Mergnat .parent_data = (const struct clk_parent_data []) { 9590dea3f35SAlexandre Mergnat { .fw_name = "xtal", }, 9600dea3f35SAlexandre Mergnat { .hw = &gxbb_clk81.hw }, 9610dea3f35SAlexandre Mergnat }, 96233d0fcdfSMartin Blumenstingl .num_parents = 2, 96333d0fcdfSMartin Blumenstingl }, 96433d0fcdfSMartin Blumenstingl }; 96533d0fcdfSMartin Blumenstingl 966f06ddd28SJerome Brunet static struct clk_regmap gxbb_sar_adc_clk_div = { 967f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 968f06ddd28SJerome Brunet .offset = HHI_SAR_CLK_CNTL, 96933d0fcdfSMartin Blumenstingl .shift = 0, 97033d0fcdfSMartin Blumenstingl .width = 8, 971f06ddd28SJerome Brunet }, 97233d0fcdfSMartin Blumenstingl .hw.init = &(struct clk_init_data){ 97333d0fcdfSMartin Blumenstingl .name = "sar_adc_clk_div", 974f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 9750dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 9760dea3f35SAlexandre Mergnat &gxbb_sar_adc_clk_sel.hw 9770dea3f35SAlexandre Mergnat }, 97833d0fcdfSMartin Blumenstingl .num_parents = 1, 97944b09b11SMartin Blumenstingl .flags = CLK_SET_RATE_PARENT, 98033d0fcdfSMartin Blumenstingl }, 98133d0fcdfSMartin Blumenstingl }; 98233d0fcdfSMartin Blumenstingl 9837f9768a5SJerome Brunet static struct clk_regmap gxbb_sar_adc_clk = { 9847f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 9857f9768a5SJerome Brunet .offset = HHI_SAR_CLK_CNTL, 98633d0fcdfSMartin Blumenstingl .bit_idx = 8, 9877f9768a5SJerome Brunet }, 98833d0fcdfSMartin Blumenstingl .hw.init = &(struct clk_init_data){ 98933d0fcdfSMartin Blumenstingl .name = "sar_adc_clk", 9907f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 9910dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 9920dea3f35SAlexandre Mergnat &gxbb_sar_adc_clk_div.hw 9930dea3f35SAlexandre Mergnat }, 99433d0fcdfSMartin Blumenstingl .num_parents = 1, 99533d0fcdfSMartin Blumenstingl .flags = CLK_SET_RATE_PARENT, 99633d0fcdfSMartin Blumenstingl }, 99733d0fcdfSMartin Blumenstingl }; 99833d0fcdfSMartin Blumenstingl 999fac9a55bSNeil Armstrong /* 1000fac9a55bSNeil Armstrong * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) 10015c2602e5SMartin Blumenstingl * muxed by a glitch-free switch. The CCF can manage this glitch-free 10025c2602e5SMartin Blumenstingl * mux because it does top-to-bottom updates the each clock tree and 10035c2602e5SMartin Blumenstingl * switches to the "inactive" one when CLK_SET_RATE_GATE is set. 1004fac9a55bSNeil Armstrong */ 1005fac9a55bSNeil Armstrong 10060dea3f35SAlexandre Mergnat static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = { 10070dea3f35SAlexandre Mergnat { .fw_name = "xtal", }, 10080dea3f35SAlexandre Mergnat { .hw = &gxbb_gp0_pll.hw }, 10090dea3f35SAlexandre Mergnat { .hw = &gxbb_mpll2.hw }, 10100dea3f35SAlexandre Mergnat { .hw = &gxbb_mpll1.hw }, 10110dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div7.hw }, 10120dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div4.hw }, 10130dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div3.hw }, 10140dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div5.hw }, 1015fac9a55bSNeil Armstrong }; 1016fac9a55bSNeil Armstrong 10172513a28cSJerome Brunet static struct clk_regmap gxbb_mali_0_sel = { 10182513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 10192513a28cSJerome Brunet .offset = HHI_MALI_CLK_CNTL, 1020fac9a55bSNeil Armstrong .mask = 0x7, 1021fac9a55bSNeil Armstrong .shift = 9, 10222513a28cSJerome Brunet }, 1023fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 1024fac9a55bSNeil Armstrong .name = "mali_0_sel", 10252513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 10260dea3f35SAlexandre Mergnat .parent_data = gxbb_mali_0_1_parent_data, 1027fac9a55bSNeil Armstrong .num_parents = 8, 10285c2602e5SMartin Blumenstingl /* 10295c2602e5SMartin Blumenstingl * Don't request the parent to change the rate because 10305c2602e5SMartin Blumenstingl * all GPU frequencies can be derived from the fclk_* 10315c2602e5SMartin Blumenstingl * clocks and one special GP0_PLL setting. This is 10325c2602e5SMartin Blumenstingl * important because we need the MPLL clocks for audio. 10335c2602e5SMartin Blumenstingl */ 10345c2602e5SMartin Blumenstingl .flags = 0, 1035fac9a55bSNeil Armstrong }, 1036fac9a55bSNeil Armstrong }; 1037fac9a55bSNeil Armstrong 1038f06ddd28SJerome Brunet static struct clk_regmap gxbb_mali_0_div = { 1039f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1040f06ddd28SJerome Brunet .offset = HHI_MALI_CLK_CNTL, 1041fac9a55bSNeil Armstrong .shift = 0, 1042fac9a55bSNeil Armstrong .width = 7, 1043f06ddd28SJerome Brunet }, 1044fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 1045fac9a55bSNeil Armstrong .name = "mali_0_div", 1046f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 10470dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 10480dea3f35SAlexandre Mergnat &gxbb_mali_0_sel.hw 10490dea3f35SAlexandre Mergnat }, 1050fac9a55bSNeil Armstrong .num_parents = 1, 10515c2602e5SMartin Blumenstingl .flags = CLK_SET_RATE_PARENT, 1052fac9a55bSNeil Armstrong }, 1053fac9a55bSNeil Armstrong }; 1054fac9a55bSNeil Armstrong 10557f9768a5SJerome Brunet static struct clk_regmap gxbb_mali_0 = { 10567f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 10577f9768a5SJerome Brunet .offset = HHI_MALI_CLK_CNTL, 1058fac9a55bSNeil Armstrong .bit_idx = 8, 10597f9768a5SJerome Brunet }, 1060fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 1061fac9a55bSNeil Armstrong .name = "mali_0", 10627f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 10630dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 10640dea3f35SAlexandre Mergnat &gxbb_mali_0_div.hw 10650dea3f35SAlexandre Mergnat }, 1066fac9a55bSNeil Armstrong .num_parents = 1, 10675c2602e5SMartin Blumenstingl .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, 1068fac9a55bSNeil Armstrong }, 1069fac9a55bSNeil Armstrong }; 1070fac9a55bSNeil Armstrong 10712513a28cSJerome Brunet static struct clk_regmap gxbb_mali_1_sel = { 10722513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 10732513a28cSJerome Brunet .offset = HHI_MALI_CLK_CNTL, 1074fac9a55bSNeil Armstrong .mask = 0x7, 1075fac9a55bSNeil Armstrong .shift = 25, 10762513a28cSJerome Brunet }, 1077fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 1078fac9a55bSNeil Armstrong .name = "mali_1_sel", 10792513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 10800dea3f35SAlexandre Mergnat .parent_data = gxbb_mali_0_1_parent_data, 1081fac9a55bSNeil Armstrong .num_parents = 8, 10825c2602e5SMartin Blumenstingl /* 10835c2602e5SMartin Blumenstingl * Don't request the parent to change the rate because 10845c2602e5SMartin Blumenstingl * all GPU frequencies can be derived from the fclk_* 10855c2602e5SMartin Blumenstingl * clocks and one special GP0_PLL setting. This is 10865c2602e5SMartin Blumenstingl * important because we need the MPLL clocks for audio. 10875c2602e5SMartin Blumenstingl */ 10885c2602e5SMartin Blumenstingl .flags = 0, 1089fac9a55bSNeil Armstrong }, 1090fac9a55bSNeil Armstrong }; 1091fac9a55bSNeil Armstrong 1092f06ddd28SJerome Brunet static struct clk_regmap gxbb_mali_1_div = { 1093f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1094f06ddd28SJerome Brunet .offset = HHI_MALI_CLK_CNTL, 1095fac9a55bSNeil Armstrong .shift = 16, 1096fac9a55bSNeil Armstrong .width = 7, 1097f06ddd28SJerome Brunet }, 1098fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 1099fac9a55bSNeil Armstrong .name = "mali_1_div", 1100f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 11010dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 11020dea3f35SAlexandre Mergnat &gxbb_mali_1_sel.hw 11030dea3f35SAlexandre Mergnat }, 1104fac9a55bSNeil Armstrong .num_parents = 1, 11055c2602e5SMartin Blumenstingl .flags = CLK_SET_RATE_PARENT, 1106fac9a55bSNeil Armstrong }, 1107fac9a55bSNeil Armstrong }; 1108fac9a55bSNeil Armstrong 11097f9768a5SJerome Brunet static struct clk_regmap gxbb_mali_1 = { 11107f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 11117f9768a5SJerome Brunet .offset = HHI_MALI_CLK_CNTL, 1112fac9a55bSNeil Armstrong .bit_idx = 24, 11137f9768a5SJerome Brunet }, 1114fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 1115fac9a55bSNeil Armstrong .name = "mali_1", 11167f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 11170dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 11180dea3f35SAlexandre Mergnat &gxbb_mali_1_div.hw 11190dea3f35SAlexandre Mergnat }, 1120fac9a55bSNeil Armstrong .num_parents = 1, 11215c2602e5SMartin Blumenstingl .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, 1122fac9a55bSNeil Armstrong }, 1123fac9a55bSNeil Armstrong }; 1124fac9a55bSNeil Armstrong 11250dea3f35SAlexandre Mergnat static const struct clk_hw *gxbb_mali_parent_hws[] = { 11260dea3f35SAlexandre Mergnat &gxbb_mali_0.hw, 11270dea3f35SAlexandre Mergnat &gxbb_mali_1.hw, 1128fac9a55bSNeil Armstrong }; 1129fac9a55bSNeil Armstrong 11302513a28cSJerome Brunet static struct clk_regmap gxbb_mali = { 11312513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 11322513a28cSJerome Brunet .offset = HHI_MALI_CLK_CNTL, 1133fac9a55bSNeil Armstrong .mask = 1, 1134fac9a55bSNeil Armstrong .shift = 31, 11352513a28cSJerome Brunet }, 1136fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 1137fac9a55bSNeil Armstrong .name = "mali", 11382513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 11390dea3f35SAlexandre Mergnat .parent_hws = gxbb_mali_parent_hws, 1140fac9a55bSNeil Armstrong .num_parents = 2, 11415c2602e5SMartin Blumenstingl .flags = CLK_SET_RATE_PARENT, 1142fac9a55bSNeil Armstrong }, 1143fac9a55bSNeil Armstrong }; 1144fac9a55bSNeil Armstrong 11452513a28cSJerome Brunet static struct clk_regmap gxbb_cts_amclk_sel = { 11462513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 11472513a28cSJerome Brunet .offset = HHI_AUD_CLK_CNTL, 11484087bd4bSJerome Brunet .mask = 0x3, 11494087bd4bSJerome Brunet .shift = 9, 11504087bd4bSJerome Brunet .table = (u32[]){ 1, 2, 3 }, 11519799d5aeSJerome Brunet .flags = CLK_MUX_ROUND_CLOSEST, 11522513a28cSJerome Brunet }, 11534087bd4bSJerome Brunet .hw.init = &(struct clk_init_data){ 11544087bd4bSJerome Brunet .name = "cts_amclk_sel", 11552513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 11560dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 11570dea3f35SAlexandre Mergnat &gxbb_mpll0.hw, 11580dea3f35SAlexandre Mergnat &gxbb_mpll1.hw, 11590dea3f35SAlexandre Mergnat &gxbb_mpll2.hw, 11600dea3f35SAlexandre Mergnat }, 11614087bd4bSJerome Brunet .num_parents = 3, 11624087bd4bSJerome Brunet }, 11634087bd4bSJerome Brunet }; 11644087bd4bSJerome Brunet 116588a4e128SJerome Brunet static struct clk_regmap gxbb_cts_amclk_div = { 11669799d5aeSJerome Brunet .data = &(struct clk_regmap_div_data) { 11679799d5aeSJerome Brunet .offset = HHI_AUD_CLK_CNTL, 11684087bd4bSJerome Brunet .shift = 0, 11694087bd4bSJerome Brunet .width = 8, 1170004f6f46SJerome Brunet .flags = CLK_DIVIDER_ROUND_CLOSEST, 117188a4e128SJerome Brunet }, 11724087bd4bSJerome Brunet .hw.init = &(struct clk_init_data){ 11734087bd4bSJerome Brunet .name = "cts_amclk_div", 11749799d5aeSJerome Brunet .ops = &clk_regmap_divider_ops, 11750dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 11760dea3f35SAlexandre Mergnat &gxbb_cts_amclk_sel.hw 11770dea3f35SAlexandre Mergnat }, 11784087bd4bSJerome Brunet .num_parents = 1, 1179004f6f46SJerome Brunet .flags = CLK_SET_RATE_PARENT, 11804087bd4bSJerome Brunet }, 11814087bd4bSJerome Brunet }; 11824087bd4bSJerome Brunet 11837f9768a5SJerome Brunet static struct clk_regmap gxbb_cts_amclk = { 11847f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 11857f9768a5SJerome Brunet .offset = HHI_AUD_CLK_CNTL, 11864087bd4bSJerome Brunet .bit_idx = 8, 11877f9768a5SJerome Brunet }, 11884087bd4bSJerome Brunet .hw.init = &(struct clk_init_data){ 11894087bd4bSJerome Brunet .name = "cts_amclk", 11907f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 11910dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 11920dea3f35SAlexandre Mergnat &gxbb_cts_amclk_div.hw 11930dea3f35SAlexandre Mergnat }, 11944087bd4bSJerome Brunet .num_parents = 1, 11954087bd4bSJerome Brunet .flags = CLK_SET_RATE_PARENT, 11964087bd4bSJerome Brunet }, 11974087bd4bSJerome Brunet }; 11984087bd4bSJerome Brunet 11992513a28cSJerome Brunet static struct clk_regmap gxbb_cts_mclk_i958_sel = { 12002513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 12012513a28cSJerome Brunet .offset = HHI_AUD_CLK_CNTL2, 12023c277c24SJerome Brunet .mask = 0x3, 12033c277c24SJerome Brunet .shift = 25, 12043c277c24SJerome Brunet .table = (u32[]){ 1, 2, 3 }, 12059799d5aeSJerome Brunet .flags = CLK_MUX_ROUND_CLOSEST, 12062513a28cSJerome Brunet }, 12073c277c24SJerome Brunet .hw.init = &(struct clk_init_data) { 12083c277c24SJerome Brunet .name = "cts_mclk_i958_sel", 12092513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 12100dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 12110dea3f35SAlexandre Mergnat &gxbb_mpll0.hw, 12120dea3f35SAlexandre Mergnat &gxbb_mpll1.hw, 12130dea3f35SAlexandre Mergnat &gxbb_mpll2.hw, 12140dea3f35SAlexandre Mergnat }, 12153c277c24SJerome Brunet .num_parents = 3, 12163c277c24SJerome Brunet }, 12173c277c24SJerome Brunet }; 12183c277c24SJerome Brunet 1219f06ddd28SJerome Brunet static struct clk_regmap gxbb_cts_mclk_i958_div = { 1220f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1221f06ddd28SJerome Brunet .offset = HHI_AUD_CLK_CNTL2, 12223c277c24SJerome Brunet .shift = 16, 12233c277c24SJerome Brunet .width = 8, 12247605aa5bSJerome Brunet .flags = CLK_DIVIDER_ROUND_CLOSEST, 1225f06ddd28SJerome Brunet }, 12263c277c24SJerome Brunet .hw.init = &(struct clk_init_data) { 12273c277c24SJerome Brunet .name = "cts_mclk_i958_div", 1228f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 12290dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 12300dea3f35SAlexandre Mergnat &gxbb_cts_mclk_i958_sel.hw 12310dea3f35SAlexandre Mergnat }, 12323c277c24SJerome Brunet .num_parents = 1, 12337605aa5bSJerome Brunet .flags = CLK_SET_RATE_PARENT, 12343c277c24SJerome Brunet }, 12353c277c24SJerome Brunet }; 12363c277c24SJerome Brunet 12377f9768a5SJerome Brunet static struct clk_regmap gxbb_cts_mclk_i958 = { 12387f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 12397f9768a5SJerome Brunet .offset = HHI_AUD_CLK_CNTL2, 12403c277c24SJerome Brunet .bit_idx = 24, 12417f9768a5SJerome Brunet }, 12423c277c24SJerome Brunet .hw.init = &(struct clk_init_data){ 12433c277c24SJerome Brunet .name = "cts_mclk_i958", 12447f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 12450dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 12460dea3f35SAlexandre Mergnat &gxbb_cts_mclk_i958_div.hw 12470dea3f35SAlexandre Mergnat }, 12483c277c24SJerome Brunet .num_parents = 1, 12493c277c24SJerome Brunet .flags = CLK_SET_RATE_PARENT, 12503c277c24SJerome Brunet }, 12513c277c24SJerome Brunet }; 12523c277c24SJerome Brunet 12532513a28cSJerome Brunet static struct clk_regmap gxbb_cts_i958 = { 12542513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 12552513a28cSJerome Brunet .offset = HHI_AUD_CLK_CNTL2, 12567eaa44f6SJerome Brunet .mask = 0x1, 12577eaa44f6SJerome Brunet .shift = 27, 12582513a28cSJerome Brunet }, 12597eaa44f6SJerome Brunet .hw.init = &(struct clk_init_data){ 12607eaa44f6SJerome Brunet .name = "cts_i958", 12612513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 12620dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 12630dea3f35SAlexandre Mergnat &gxbb_cts_amclk.hw, 12640dea3f35SAlexandre Mergnat &gxbb_cts_mclk_i958.hw 12650dea3f35SAlexandre Mergnat }, 12667eaa44f6SJerome Brunet .num_parents = 2, 12677eaa44f6SJerome Brunet /* 12687eaa44f6SJerome Brunet *The parent is specific to origin of the audio data. Let the 12697eaa44f6SJerome Brunet * consumer choose the appropriate parent 12707eaa44f6SJerome Brunet */ 12717eaa44f6SJerome Brunet .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 12727eaa44f6SJerome Brunet }, 12737eaa44f6SJerome Brunet }; 12747eaa44f6SJerome Brunet 12750dea3f35SAlexandre Mergnat static const struct clk_parent_data gxbb_32k_clk_parent_data[] = { 12760dea3f35SAlexandre Mergnat { .fw_name = "xtal", }, 12770dea3f35SAlexandre Mergnat /* 12780dea3f35SAlexandre Mergnat * FIXME: This clock is provided by the ao clock controller but the 12790dea3f35SAlexandre Mergnat * clock is not yet part of the binding of this controller, so string 12800dea3f35SAlexandre Mergnat * name must be use to set this parent. 12810dea3f35SAlexandre Mergnat */ 12820dea3f35SAlexandre Mergnat { .name = "cts_slow_oscin", .index = -1 }, 12830dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div3.hw }, 12840dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div5.hw }, 12850dea3f35SAlexandre Mergnat }; 12860dea3f35SAlexandre Mergnat 12870dea3f35SAlexandre Mergnat static struct clk_regmap gxbb_32k_clk_sel = { 12880dea3f35SAlexandre Mergnat .data = &(struct clk_regmap_mux_data){ 12890dea3f35SAlexandre Mergnat .offset = HHI_32K_CLK_CNTL, 12900dea3f35SAlexandre Mergnat .mask = 0x3, 12910dea3f35SAlexandre Mergnat .shift = 16, 12920dea3f35SAlexandre Mergnat }, 12930dea3f35SAlexandre Mergnat .hw.init = &(struct clk_init_data){ 12940dea3f35SAlexandre Mergnat .name = "32k_clk_sel", 12950dea3f35SAlexandre Mergnat .ops = &clk_regmap_mux_ops, 12960dea3f35SAlexandre Mergnat .parent_data = gxbb_32k_clk_parent_data, 12970dea3f35SAlexandre Mergnat .num_parents = 4, 12980dea3f35SAlexandre Mergnat .flags = CLK_SET_RATE_PARENT, 12990dea3f35SAlexandre Mergnat }, 13000dea3f35SAlexandre Mergnat }; 13010dea3f35SAlexandre Mergnat 1302f06ddd28SJerome Brunet static struct clk_regmap gxbb_32k_clk_div = { 1303f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1304f06ddd28SJerome Brunet .offset = HHI_32K_CLK_CNTL, 130514c735c8SNeil Armstrong .shift = 0, 130614c735c8SNeil Armstrong .width = 14, 1307f06ddd28SJerome Brunet }, 130814c735c8SNeil Armstrong .hw.init = &(struct clk_init_data){ 130914c735c8SNeil Armstrong .name = "32k_clk_div", 1310f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 13110dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 13120dea3f35SAlexandre Mergnat &gxbb_32k_clk_sel.hw 13130dea3f35SAlexandre Mergnat }, 131414c735c8SNeil Armstrong .num_parents = 1, 131514c735c8SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST, 131614c735c8SNeil Armstrong }, 131714c735c8SNeil Armstrong }; 131814c735c8SNeil Armstrong 13197f9768a5SJerome Brunet static struct clk_regmap gxbb_32k_clk = { 13207f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 13217f9768a5SJerome Brunet .offset = HHI_32K_CLK_CNTL, 132214c735c8SNeil Armstrong .bit_idx = 15, 13237f9768a5SJerome Brunet }, 132414c735c8SNeil Armstrong .hw.init = &(struct clk_init_data){ 132514c735c8SNeil Armstrong .name = "32k_clk", 13267f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 13270dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 13280dea3f35SAlexandre Mergnat &gxbb_32k_clk_div.hw 13290dea3f35SAlexandre Mergnat }, 133014c735c8SNeil Armstrong .num_parents = 1, 133114c735c8SNeil Armstrong .flags = CLK_SET_RATE_PARENT, 133214c735c8SNeil Armstrong }, 133314c735c8SNeil Armstrong }; 133414c735c8SNeil Armstrong 13350dea3f35SAlexandre Mergnat static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data[] = { 13360dea3f35SAlexandre Mergnat { .fw_name = "xtal", }, 13370dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div2.hw }, 13380dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div3.hw }, 13390dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div5.hw }, 13400dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div7.hw }, 1341914e6e80SJerome Brunet /* 1342914e6e80SJerome Brunet * Following these parent clocks, we should also have had mpll2, mpll3 1343914e6e80SJerome Brunet * and gp0_pll but these clocks are too precious to be used here. All 1344914e6e80SJerome Brunet * the necessary rates for MMC and NAND operation can be acheived using 1345914e6e80SJerome Brunet * xtal or fclk_div clocks 1346914e6e80SJerome Brunet */ 1347914e6e80SJerome Brunet }; 1348914e6e80SJerome Brunet 1349914e6e80SJerome Brunet /* SDIO clock */ 13502513a28cSJerome Brunet static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = { 13512513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 13522513a28cSJerome Brunet .offset = HHI_SD_EMMC_CLK_CNTL, 1353914e6e80SJerome Brunet .mask = 0x7, 1354914e6e80SJerome Brunet .shift = 9, 13552513a28cSJerome Brunet }, 1356914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1357914e6e80SJerome Brunet .name = "sd_emmc_a_clk0_sel", 13582513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 13590dea3f35SAlexandre Mergnat .parent_data = gxbb_sd_emmc_clk0_parent_data, 13600dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data), 1361914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1362914e6e80SJerome Brunet }, 1363914e6e80SJerome Brunet }; 1364914e6e80SJerome Brunet 1365f06ddd28SJerome Brunet static struct clk_regmap gxbb_sd_emmc_a_clk0_div = { 1366f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1367f06ddd28SJerome Brunet .offset = HHI_SD_EMMC_CLK_CNTL, 1368914e6e80SJerome Brunet .shift = 0, 1369914e6e80SJerome Brunet .width = 7, 1370914e6e80SJerome Brunet .flags = CLK_DIVIDER_ROUND_CLOSEST, 1371f06ddd28SJerome Brunet }, 1372914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1373914e6e80SJerome Brunet .name = "sd_emmc_a_clk0_div", 1374f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 13750dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 13760dea3f35SAlexandre Mergnat &gxbb_sd_emmc_a_clk0_sel.hw 13770dea3f35SAlexandre Mergnat }, 1378914e6e80SJerome Brunet .num_parents = 1, 1379914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1380914e6e80SJerome Brunet }, 1381914e6e80SJerome Brunet }; 1382914e6e80SJerome Brunet 13837f9768a5SJerome Brunet static struct clk_regmap gxbb_sd_emmc_a_clk0 = { 13847f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 13857f9768a5SJerome Brunet .offset = HHI_SD_EMMC_CLK_CNTL, 1386914e6e80SJerome Brunet .bit_idx = 7, 13877f9768a5SJerome Brunet }, 1388914e6e80SJerome Brunet .hw.init = &(struct clk_init_data){ 1389914e6e80SJerome Brunet .name = "sd_emmc_a_clk0", 13907f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 13910dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 13920dea3f35SAlexandre Mergnat &gxbb_sd_emmc_a_clk0_div.hw 13930dea3f35SAlexandre Mergnat }, 1394914e6e80SJerome Brunet .num_parents = 1, 1395ed3fb5afSJerome Brunet .flags = CLK_SET_RATE_PARENT, 1396914e6e80SJerome Brunet }, 1397914e6e80SJerome Brunet }; 1398914e6e80SJerome Brunet 1399914e6e80SJerome Brunet /* SDcard clock */ 14002513a28cSJerome Brunet static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = { 14012513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 14022513a28cSJerome Brunet .offset = HHI_SD_EMMC_CLK_CNTL, 1403914e6e80SJerome Brunet .mask = 0x7, 1404914e6e80SJerome Brunet .shift = 25, 14052513a28cSJerome Brunet }, 1406914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1407914e6e80SJerome Brunet .name = "sd_emmc_b_clk0_sel", 14082513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 14090dea3f35SAlexandre Mergnat .parent_data = gxbb_sd_emmc_clk0_parent_data, 14100dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data), 1411914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1412914e6e80SJerome Brunet }, 1413914e6e80SJerome Brunet }; 1414914e6e80SJerome Brunet 1415f06ddd28SJerome Brunet static struct clk_regmap gxbb_sd_emmc_b_clk0_div = { 1416f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1417f06ddd28SJerome Brunet .offset = HHI_SD_EMMC_CLK_CNTL, 1418914e6e80SJerome Brunet .shift = 16, 1419914e6e80SJerome Brunet .width = 7, 1420914e6e80SJerome Brunet .flags = CLK_DIVIDER_ROUND_CLOSEST, 1421f06ddd28SJerome Brunet }, 1422914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1423914e6e80SJerome Brunet .name = "sd_emmc_b_clk0_div", 1424f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 14250dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 14260dea3f35SAlexandre Mergnat &gxbb_sd_emmc_b_clk0_sel.hw 14270dea3f35SAlexandre Mergnat }, 1428914e6e80SJerome Brunet .num_parents = 1, 1429914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1430914e6e80SJerome Brunet }, 1431914e6e80SJerome Brunet }; 1432914e6e80SJerome Brunet 14337f9768a5SJerome Brunet static struct clk_regmap gxbb_sd_emmc_b_clk0 = { 14347f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 14357f9768a5SJerome Brunet .offset = HHI_SD_EMMC_CLK_CNTL, 1436914e6e80SJerome Brunet .bit_idx = 23, 14377f9768a5SJerome Brunet }, 1438914e6e80SJerome Brunet .hw.init = &(struct clk_init_data){ 1439914e6e80SJerome Brunet .name = "sd_emmc_b_clk0", 14407f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 14410dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 14420dea3f35SAlexandre Mergnat &gxbb_sd_emmc_b_clk0_div.hw 14430dea3f35SAlexandre Mergnat }, 1444914e6e80SJerome Brunet .num_parents = 1, 1445ed3fb5afSJerome Brunet .flags = CLK_SET_RATE_PARENT, 1446914e6e80SJerome Brunet }, 1447914e6e80SJerome Brunet }; 1448914e6e80SJerome Brunet 1449914e6e80SJerome Brunet /* EMMC/NAND clock */ 14502513a28cSJerome Brunet static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = { 14512513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 14522513a28cSJerome Brunet .offset = HHI_NAND_CLK_CNTL, 1453914e6e80SJerome Brunet .mask = 0x7, 1454914e6e80SJerome Brunet .shift = 9, 14552513a28cSJerome Brunet }, 1456914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1457914e6e80SJerome Brunet .name = "sd_emmc_c_clk0_sel", 14582513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 14590dea3f35SAlexandre Mergnat .parent_data = gxbb_sd_emmc_clk0_parent_data, 14600dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data), 1461914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1462914e6e80SJerome Brunet }, 1463914e6e80SJerome Brunet }; 1464914e6e80SJerome Brunet 1465f06ddd28SJerome Brunet static struct clk_regmap gxbb_sd_emmc_c_clk0_div = { 1466f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1467f06ddd28SJerome Brunet .offset = HHI_NAND_CLK_CNTL, 1468914e6e80SJerome Brunet .shift = 0, 1469914e6e80SJerome Brunet .width = 7, 1470914e6e80SJerome Brunet .flags = CLK_DIVIDER_ROUND_CLOSEST, 1471f06ddd28SJerome Brunet }, 1472914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1473914e6e80SJerome Brunet .name = "sd_emmc_c_clk0_div", 1474f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 14750dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 14760dea3f35SAlexandre Mergnat &gxbb_sd_emmc_c_clk0_sel.hw 14770dea3f35SAlexandre Mergnat }, 1478914e6e80SJerome Brunet .num_parents = 1, 1479914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1480914e6e80SJerome Brunet }, 1481914e6e80SJerome Brunet }; 1482914e6e80SJerome Brunet 14837f9768a5SJerome Brunet static struct clk_regmap gxbb_sd_emmc_c_clk0 = { 14847f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 14857f9768a5SJerome Brunet .offset = HHI_NAND_CLK_CNTL, 1486914e6e80SJerome Brunet .bit_idx = 7, 14877f9768a5SJerome Brunet }, 1488914e6e80SJerome Brunet .hw.init = &(struct clk_init_data){ 1489914e6e80SJerome Brunet .name = "sd_emmc_c_clk0", 14907f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 14910dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 14920dea3f35SAlexandre Mergnat &gxbb_sd_emmc_c_clk0_div.hw 14930dea3f35SAlexandre Mergnat }, 1494914e6e80SJerome Brunet .num_parents = 1, 1495ed3fb5afSJerome Brunet .flags = CLK_SET_RATE_PARENT, 1496914e6e80SJerome Brunet }, 1497914e6e80SJerome Brunet }; 1498914e6e80SJerome Brunet 1499762a1f20SNeil Armstrong /* VPU Clock */ 1500762a1f20SNeil Armstrong 15010dea3f35SAlexandre Mergnat static const struct clk_hw *gxbb_vpu_parent_hws[] = { 15020dea3f35SAlexandre Mergnat &gxbb_fclk_div4.hw, 15030dea3f35SAlexandre Mergnat &gxbb_fclk_div3.hw, 15040dea3f35SAlexandre Mergnat &gxbb_fclk_div5.hw, 15050dea3f35SAlexandre Mergnat &gxbb_fclk_div7.hw, 1506762a1f20SNeil Armstrong }; 1507762a1f20SNeil Armstrong 15082513a28cSJerome Brunet static struct clk_regmap gxbb_vpu_0_sel = { 15092513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 15102513a28cSJerome Brunet .offset = HHI_VPU_CLK_CNTL, 1511762a1f20SNeil Armstrong .mask = 0x3, 1512762a1f20SNeil Armstrong .shift = 9, 15132513a28cSJerome Brunet }, 1514762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1515762a1f20SNeil Armstrong .name = "vpu_0_sel", 15162513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 1517762a1f20SNeil Armstrong /* 1518762a1f20SNeil Armstrong * bits 9:10 selects from 4 possible parents: 1519762a1f20SNeil Armstrong * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1520762a1f20SNeil Armstrong */ 15210dea3f35SAlexandre Mergnat .parent_hws = gxbb_vpu_parent_hws, 15220dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws), 1523762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1524762a1f20SNeil Armstrong }, 1525762a1f20SNeil Armstrong }; 1526762a1f20SNeil Armstrong 1527f06ddd28SJerome Brunet static struct clk_regmap gxbb_vpu_0_div = { 1528f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1529f06ddd28SJerome Brunet .offset = HHI_VPU_CLK_CNTL, 1530762a1f20SNeil Armstrong .shift = 0, 1531762a1f20SNeil Armstrong .width = 7, 1532f06ddd28SJerome Brunet }, 1533762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1534762a1f20SNeil Armstrong .name = "vpu_0_div", 1535f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 15360dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_sel.hw }, 1537762a1f20SNeil Armstrong .num_parents = 1, 1538762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT, 1539762a1f20SNeil Armstrong }, 1540762a1f20SNeil Armstrong }; 1541762a1f20SNeil Armstrong 15427f9768a5SJerome Brunet static struct clk_regmap gxbb_vpu_0 = { 15437f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 15447f9768a5SJerome Brunet .offset = HHI_VPU_CLK_CNTL, 1545762a1f20SNeil Armstrong .bit_idx = 8, 15467f9768a5SJerome Brunet }, 1547762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data) { 1548762a1f20SNeil Armstrong .name = "vpu_0", 15497f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 15500dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw }, 1551762a1f20SNeil Armstrong .num_parents = 1, 1552762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1553762a1f20SNeil Armstrong }, 1554762a1f20SNeil Armstrong }; 1555762a1f20SNeil Armstrong 15562513a28cSJerome Brunet static struct clk_regmap gxbb_vpu_1_sel = { 15572513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 15582513a28cSJerome Brunet .offset = HHI_VPU_CLK_CNTL, 1559762a1f20SNeil Armstrong .mask = 0x3, 1560762a1f20SNeil Armstrong .shift = 25, 15612513a28cSJerome Brunet }, 1562762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1563762a1f20SNeil Armstrong .name = "vpu_1_sel", 15642513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 1565762a1f20SNeil Armstrong /* 1566762a1f20SNeil Armstrong * bits 25:26 selects from 4 possible parents: 1567762a1f20SNeil Armstrong * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1568762a1f20SNeil Armstrong */ 15690dea3f35SAlexandre Mergnat .parent_hws = gxbb_vpu_parent_hws, 15700dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws), 1571762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1572762a1f20SNeil Armstrong }, 1573762a1f20SNeil Armstrong }; 1574762a1f20SNeil Armstrong 1575f06ddd28SJerome Brunet static struct clk_regmap gxbb_vpu_1_div = { 1576f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1577f06ddd28SJerome Brunet .offset = HHI_VPU_CLK_CNTL, 1578762a1f20SNeil Armstrong .shift = 16, 1579762a1f20SNeil Armstrong .width = 7, 1580f06ddd28SJerome Brunet }, 1581762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1582762a1f20SNeil Armstrong .name = "vpu_1_div", 1583f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 15840dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_sel.hw }, 1585762a1f20SNeil Armstrong .num_parents = 1, 1586762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT, 1587762a1f20SNeil Armstrong }, 1588762a1f20SNeil Armstrong }; 1589762a1f20SNeil Armstrong 15907f9768a5SJerome Brunet static struct clk_regmap gxbb_vpu_1 = { 15917f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 15927f9768a5SJerome Brunet .offset = HHI_VPU_CLK_CNTL, 1593762a1f20SNeil Armstrong .bit_idx = 24, 15947f9768a5SJerome Brunet }, 1595762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data) { 1596762a1f20SNeil Armstrong .name = "vpu_1", 15977f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 15980dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw }, 1599762a1f20SNeil Armstrong .num_parents = 1, 1600762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1601762a1f20SNeil Armstrong }, 1602762a1f20SNeil Armstrong }; 1603762a1f20SNeil Armstrong 16042513a28cSJerome Brunet static struct clk_regmap gxbb_vpu = { 16052513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 16062513a28cSJerome Brunet .offset = HHI_VPU_CLK_CNTL, 1607762a1f20SNeil Armstrong .mask = 1, 1608762a1f20SNeil Armstrong .shift = 31, 16092513a28cSJerome Brunet }, 1610762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1611762a1f20SNeil Armstrong .name = "vpu", 16122513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 1613762a1f20SNeil Armstrong /* 1614762a1f20SNeil Armstrong * bit 31 selects from 2 possible parents: 1615762a1f20SNeil Armstrong * vpu_0 or vpu_1 1616762a1f20SNeil Armstrong */ 16170dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 16180dea3f35SAlexandre Mergnat &gxbb_vpu_0.hw, 16190dea3f35SAlexandre Mergnat &gxbb_vpu_1.hw 16200dea3f35SAlexandre Mergnat }, 1621762a1f20SNeil Armstrong .num_parents = 2, 1622762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1623762a1f20SNeil Armstrong }, 1624762a1f20SNeil Armstrong }; 1625762a1f20SNeil Armstrong 1626762a1f20SNeil Armstrong /* VAPB Clock */ 1627762a1f20SNeil Armstrong 16280dea3f35SAlexandre Mergnat static const struct clk_hw *gxbb_vapb_parent_hws[] = { 16290dea3f35SAlexandre Mergnat &gxbb_fclk_div4.hw, 16300dea3f35SAlexandre Mergnat &gxbb_fclk_div3.hw, 16310dea3f35SAlexandre Mergnat &gxbb_fclk_div5.hw, 16320dea3f35SAlexandre Mergnat &gxbb_fclk_div7.hw, 1633762a1f20SNeil Armstrong }; 1634762a1f20SNeil Armstrong 16352513a28cSJerome Brunet static struct clk_regmap gxbb_vapb_0_sel = { 16362513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 16372513a28cSJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1638762a1f20SNeil Armstrong .mask = 0x3, 1639762a1f20SNeil Armstrong .shift = 9, 16402513a28cSJerome Brunet }, 1641762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1642762a1f20SNeil Armstrong .name = "vapb_0_sel", 16432513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 1644762a1f20SNeil Armstrong /* 1645762a1f20SNeil Armstrong * bits 9:10 selects from 4 possible parents: 1646762a1f20SNeil Armstrong * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1647762a1f20SNeil Armstrong */ 16480dea3f35SAlexandre Mergnat .parent_hws = gxbb_vapb_parent_hws, 16490dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws), 1650762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1651762a1f20SNeil Armstrong }, 1652762a1f20SNeil Armstrong }; 1653762a1f20SNeil Armstrong 1654f06ddd28SJerome Brunet static struct clk_regmap gxbb_vapb_0_div = { 1655f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1656f06ddd28SJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1657762a1f20SNeil Armstrong .shift = 0, 1658762a1f20SNeil Armstrong .width = 7, 1659f06ddd28SJerome Brunet }, 1660762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1661762a1f20SNeil Armstrong .name = "vapb_0_div", 1662f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 16630dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 16640dea3f35SAlexandre Mergnat &gxbb_vapb_0_sel.hw 16650dea3f35SAlexandre Mergnat }, 1666762a1f20SNeil Armstrong .num_parents = 1, 1667762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT, 1668762a1f20SNeil Armstrong }, 1669762a1f20SNeil Armstrong }; 1670762a1f20SNeil Armstrong 16717f9768a5SJerome Brunet static struct clk_regmap gxbb_vapb_0 = { 16727f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 16737f9768a5SJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1674762a1f20SNeil Armstrong .bit_idx = 8, 16757f9768a5SJerome Brunet }, 1676762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data) { 1677762a1f20SNeil Armstrong .name = "vapb_0", 16787f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 16790dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 16800dea3f35SAlexandre Mergnat &gxbb_vapb_0_div.hw 16810dea3f35SAlexandre Mergnat }, 1682762a1f20SNeil Armstrong .num_parents = 1, 1683762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1684762a1f20SNeil Armstrong }, 1685762a1f20SNeil Armstrong }; 1686762a1f20SNeil Armstrong 16872513a28cSJerome Brunet static struct clk_regmap gxbb_vapb_1_sel = { 16882513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 16892513a28cSJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1690762a1f20SNeil Armstrong .mask = 0x3, 1691762a1f20SNeil Armstrong .shift = 25, 16922513a28cSJerome Brunet }, 1693762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1694762a1f20SNeil Armstrong .name = "vapb_1_sel", 16952513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 1696762a1f20SNeil Armstrong /* 1697762a1f20SNeil Armstrong * bits 25:26 selects from 4 possible parents: 1698762a1f20SNeil Armstrong * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1699762a1f20SNeil Armstrong */ 17000dea3f35SAlexandre Mergnat .parent_hws = gxbb_vapb_parent_hws, 17010dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws), 1702762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1703762a1f20SNeil Armstrong }, 1704762a1f20SNeil Armstrong }; 1705762a1f20SNeil Armstrong 1706f06ddd28SJerome Brunet static struct clk_regmap gxbb_vapb_1_div = { 1707f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1708f06ddd28SJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1709762a1f20SNeil Armstrong .shift = 16, 1710762a1f20SNeil Armstrong .width = 7, 1711f06ddd28SJerome Brunet }, 1712762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1713762a1f20SNeil Armstrong .name = "vapb_1_div", 1714f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 17150dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 17160dea3f35SAlexandre Mergnat &gxbb_vapb_1_sel.hw 17170dea3f35SAlexandre Mergnat }, 1718762a1f20SNeil Armstrong .num_parents = 1, 1719762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT, 1720762a1f20SNeil Armstrong }, 1721762a1f20SNeil Armstrong }; 1722762a1f20SNeil Armstrong 17237f9768a5SJerome Brunet static struct clk_regmap gxbb_vapb_1 = { 17247f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 17257f9768a5SJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1726762a1f20SNeil Armstrong .bit_idx = 24, 17277f9768a5SJerome Brunet }, 1728762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data) { 1729762a1f20SNeil Armstrong .name = "vapb_1", 17307f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 17310dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 17320dea3f35SAlexandre Mergnat &gxbb_vapb_1_div.hw 17330dea3f35SAlexandre Mergnat }, 1734762a1f20SNeil Armstrong .num_parents = 1, 1735762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1736762a1f20SNeil Armstrong }, 1737762a1f20SNeil Armstrong }; 1738762a1f20SNeil Armstrong 17392513a28cSJerome Brunet static struct clk_regmap gxbb_vapb_sel = { 17402513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 17412513a28cSJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1742762a1f20SNeil Armstrong .mask = 1, 1743762a1f20SNeil Armstrong .shift = 31, 17442513a28cSJerome Brunet }, 1745762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1746762a1f20SNeil Armstrong .name = "vapb_sel", 17472513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 1748762a1f20SNeil Armstrong /* 1749762a1f20SNeil Armstrong * bit 31 selects from 2 possible parents: 1750762a1f20SNeil Armstrong * vapb_0 or vapb_1 1751762a1f20SNeil Armstrong */ 17520dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 17530dea3f35SAlexandre Mergnat &gxbb_vapb_0.hw, 17540dea3f35SAlexandre Mergnat &gxbb_vapb_1.hw 17550dea3f35SAlexandre Mergnat }, 1756762a1f20SNeil Armstrong .num_parents = 2, 1757762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1758762a1f20SNeil Armstrong }, 1759762a1f20SNeil Armstrong }; 1760762a1f20SNeil Armstrong 17617f9768a5SJerome Brunet static struct clk_regmap gxbb_vapb = { 17627f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 17637f9768a5SJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1764762a1f20SNeil Armstrong .bit_idx = 30, 17657f9768a5SJerome Brunet }, 1766762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data) { 1767762a1f20SNeil Armstrong .name = "vapb", 17687f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 17690dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vapb_sel.hw }, 1770762a1f20SNeil Armstrong .num_parents = 1, 1771762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1772762a1f20SNeil Armstrong }, 1773762a1f20SNeil Armstrong }; 1774762a1f20SNeil Armstrong 1775a8080f24SNeil Armstrong /* Video Clocks */ 1776a8080f24SNeil Armstrong 1777a8080f24SNeil Armstrong static struct clk_regmap gxbb_vid_pll_div = { 1778a8080f24SNeil Armstrong .data = &(struct meson_vid_pll_div_data){ 1779a8080f24SNeil Armstrong .val = { 1780a8080f24SNeil Armstrong .reg_off = HHI_VID_PLL_CLK_DIV, 1781a8080f24SNeil Armstrong .shift = 0, 1782a8080f24SNeil Armstrong .width = 15, 1783a8080f24SNeil Armstrong }, 1784a8080f24SNeil Armstrong .sel = { 1785a8080f24SNeil Armstrong .reg_off = HHI_VID_PLL_CLK_DIV, 1786a8080f24SNeil Armstrong .shift = 16, 1787a8080f24SNeil Armstrong .width = 2, 1788a8080f24SNeil Armstrong }, 1789a8080f24SNeil Armstrong }, 1790a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 1791a8080f24SNeil Armstrong .name = "vid_pll_div", 1792a8080f24SNeil Armstrong .ops = &meson_vid_pll_div_ro_ops, 17930dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 17940dea3f35SAlexandre Mergnat /* 17950dea3f35SAlexandre Mergnat * Note: 17960dea3f35SAlexandre Mergnat * GXL and GXBB have different hdmi_plls (with 17970dea3f35SAlexandre Mergnat * different struct clk_hw). We fallback to the global 17980dea3f35SAlexandre Mergnat * naming string mechanism so vid_pll_div picks up the 17990dea3f35SAlexandre Mergnat * appropriate one. 18000dea3f35SAlexandre Mergnat */ 18010dea3f35SAlexandre Mergnat .name = "hdmi_pll", 18020dea3f35SAlexandre Mergnat .index = -1, 18030dea3f35SAlexandre Mergnat }, 1804a8080f24SNeil Armstrong .num_parents = 1, 1805a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 1806a8080f24SNeil Armstrong }, 1807a8080f24SNeil Armstrong }; 1808a8080f24SNeil Armstrong 18090dea3f35SAlexandre Mergnat static const struct clk_parent_data gxbb_vid_pll_parent_data[] = { 18100dea3f35SAlexandre Mergnat { .hw = &gxbb_vid_pll_div.hw }, 18110dea3f35SAlexandre Mergnat /* 18120dea3f35SAlexandre Mergnat * Note: 18130dea3f35SAlexandre Mergnat * GXL and GXBB have different hdmi_plls (with 18140dea3f35SAlexandre Mergnat * different struct clk_hw). We fallback to the global 18150dea3f35SAlexandre Mergnat * naming string mechanism so vid_pll_div picks up the 18160dea3f35SAlexandre Mergnat * appropriate one. 18170dea3f35SAlexandre Mergnat */ 18180dea3f35SAlexandre Mergnat { .name = "hdmi_pll", .index = -1 }, 18190dea3f35SAlexandre Mergnat }; 1820a8080f24SNeil Armstrong 1821a8080f24SNeil Armstrong static struct clk_regmap gxbb_vid_pll_sel = { 1822a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 1823a8080f24SNeil Armstrong .offset = HHI_VID_PLL_CLK_DIV, 1824a8080f24SNeil Armstrong .mask = 0x1, 1825a8080f24SNeil Armstrong .shift = 18, 1826a8080f24SNeil Armstrong }, 1827a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 1828a8080f24SNeil Armstrong .name = "vid_pll_sel", 1829a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 1830a8080f24SNeil Armstrong /* 1831a8080f24SNeil Armstrong * bit 18 selects from 2 possible parents: 1832a8080f24SNeil Armstrong * vid_pll_div or hdmi_pll 1833a8080f24SNeil Armstrong */ 18340dea3f35SAlexandre Mergnat .parent_data = gxbb_vid_pll_parent_data, 18350dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_data), 1836a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1837a8080f24SNeil Armstrong }, 1838a8080f24SNeil Armstrong }; 1839a8080f24SNeil Armstrong 1840a8080f24SNeil Armstrong static struct clk_regmap gxbb_vid_pll = { 1841a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 1842a8080f24SNeil Armstrong .offset = HHI_VID_PLL_CLK_DIV, 1843a8080f24SNeil Armstrong .bit_idx = 19, 1844a8080f24SNeil Armstrong }, 1845a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 1846a8080f24SNeil Armstrong .name = "vid_pll", 1847a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 18480dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 18490dea3f35SAlexandre Mergnat &gxbb_vid_pll_sel.hw 18500dea3f35SAlexandre Mergnat }, 1851a8080f24SNeil Armstrong .num_parents = 1, 1852a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1853a8080f24SNeil Armstrong }, 1854a8080f24SNeil Armstrong }; 1855a8080f24SNeil Armstrong 18560dea3f35SAlexandre Mergnat static const struct clk_hw *gxbb_vclk_parent_hws[] = { 18570dea3f35SAlexandre Mergnat &gxbb_vid_pll.hw, 18580dea3f35SAlexandre Mergnat &gxbb_fclk_div4.hw, 18590dea3f35SAlexandre Mergnat &gxbb_fclk_div3.hw, 18600dea3f35SAlexandre Mergnat &gxbb_fclk_div5.hw, 18610dea3f35SAlexandre Mergnat &gxbb_vid_pll.hw, 18620dea3f35SAlexandre Mergnat &gxbb_fclk_div7.hw, 18630dea3f35SAlexandre Mergnat &gxbb_mpll1.hw, 1864a8080f24SNeil Armstrong }; 1865a8080f24SNeil Armstrong 1866a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_sel = { 1867a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 1868a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL, 1869a8080f24SNeil Armstrong .mask = 0x7, 1870a8080f24SNeil Armstrong .shift = 16, 1871a8080f24SNeil Armstrong }, 1872a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 1873a8080f24SNeil Armstrong .name = "vclk_sel", 1874a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 1875a8080f24SNeil Armstrong /* 1876a8080f24SNeil Armstrong * bits 16:18 selects from 8 possible parents: 1877a8080f24SNeil Armstrong * vid_pll, fclk_div4, fclk_div3, fclk_div5, 1878a8080f24SNeil Armstrong * vid_pll, fclk_div7, mp1 1879a8080f24SNeil Armstrong */ 18800dea3f35SAlexandre Mergnat .parent_hws = gxbb_vclk_parent_hws, 18810dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws), 1882a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1883a8080f24SNeil Armstrong }, 1884a8080f24SNeil Armstrong }; 1885a8080f24SNeil Armstrong 1886a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_sel = { 1887a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 1888a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_CNTL, 1889a8080f24SNeil Armstrong .mask = 0x7, 1890a8080f24SNeil Armstrong .shift = 16, 1891a8080f24SNeil Armstrong }, 1892a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 1893a8080f24SNeil Armstrong .name = "vclk2_sel", 1894a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 1895a8080f24SNeil Armstrong /* 1896a8080f24SNeil Armstrong * bits 16:18 selects from 8 possible parents: 1897a8080f24SNeil Armstrong * vid_pll, fclk_div4, fclk_div3, fclk_div5, 1898a8080f24SNeil Armstrong * vid_pll, fclk_div7, mp1 1899a8080f24SNeil Armstrong */ 19000dea3f35SAlexandre Mergnat .parent_hws = gxbb_vclk_parent_hws, 19010dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws), 1902a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1903a8080f24SNeil Armstrong }, 1904a8080f24SNeil Armstrong }; 1905a8080f24SNeil Armstrong 1906a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_input = { 1907a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 1908a8080f24SNeil Armstrong .offset = HHI_VID_CLK_DIV, 1909a8080f24SNeil Armstrong .bit_idx = 16, 1910a8080f24SNeil Armstrong }, 1911a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 1912a8080f24SNeil Armstrong .name = "vclk_input", 1913a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 19140dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_sel.hw }, 1915a8080f24SNeil Armstrong .num_parents = 1, 1916a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1917a8080f24SNeil Armstrong }, 1918a8080f24SNeil Armstrong }; 1919a8080f24SNeil Armstrong 1920a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_input = { 1921a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 1922a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_DIV, 1923a8080f24SNeil Armstrong .bit_idx = 16, 1924a8080f24SNeil Armstrong }, 1925a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 1926a8080f24SNeil Armstrong .name = "vclk2_input", 1927a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 19280dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_sel.hw }, 1929a8080f24SNeil Armstrong .num_parents = 1, 1930a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1931a8080f24SNeil Armstrong }, 1932a8080f24SNeil Armstrong }; 1933a8080f24SNeil Armstrong 1934a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_div = { 1935a8080f24SNeil Armstrong .data = &(struct clk_regmap_div_data){ 1936a8080f24SNeil Armstrong .offset = HHI_VID_CLK_DIV, 1937a8080f24SNeil Armstrong .shift = 0, 1938a8080f24SNeil Armstrong .width = 8, 1939a8080f24SNeil Armstrong }, 1940a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 1941a8080f24SNeil Armstrong .name = "vclk_div", 1942a8080f24SNeil Armstrong .ops = &clk_regmap_divider_ops, 19430dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 19440dea3f35SAlexandre Mergnat &gxbb_vclk_input.hw 19450dea3f35SAlexandre Mergnat }, 1946a8080f24SNeil Armstrong .num_parents = 1, 1947a8080f24SNeil Armstrong .flags = CLK_GET_RATE_NOCACHE, 1948a8080f24SNeil Armstrong }, 1949a8080f24SNeil Armstrong }; 1950a8080f24SNeil Armstrong 1951a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_div = { 1952a8080f24SNeil Armstrong .data = &(struct clk_regmap_div_data){ 1953a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_DIV, 1954a8080f24SNeil Armstrong .shift = 0, 1955a8080f24SNeil Armstrong .width = 8, 1956a8080f24SNeil Armstrong }, 1957a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 1958a8080f24SNeil Armstrong .name = "vclk2_div", 1959a8080f24SNeil Armstrong .ops = &clk_regmap_divider_ops, 19600dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 19610dea3f35SAlexandre Mergnat &gxbb_vclk2_input.hw 19620dea3f35SAlexandre Mergnat }, 1963a8080f24SNeil Armstrong .num_parents = 1, 1964a8080f24SNeil Armstrong .flags = CLK_GET_RATE_NOCACHE, 1965a8080f24SNeil Armstrong }, 1966a8080f24SNeil Armstrong }; 1967a8080f24SNeil Armstrong 1968a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk = { 1969a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 1970a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL, 1971a8080f24SNeil Armstrong .bit_idx = 19, 1972a8080f24SNeil Armstrong }, 1973a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 1974a8080f24SNeil Armstrong .name = "vclk", 1975a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 19760dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_div.hw }, 1977a8080f24SNeil Armstrong .num_parents = 1, 1978a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1979a8080f24SNeil Armstrong }, 1980a8080f24SNeil Armstrong }; 1981a8080f24SNeil Armstrong 1982a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2 = { 1983a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 1984a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_CNTL, 1985a8080f24SNeil Armstrong .bit_idx = 19, 1986a8080f24SNeil Armstrong }, 1987a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 1988a8080f24SNeil Armstrong .name = "vclk2", 1989a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 19900dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_div.hw }, 1991a8080f24SNeil Armstrong .num_parents = 1, 1992a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1993a8080f24SNeil Armstrong }, 1994a8080f24SNeil Armstrong }; 1995a8080f24SNeil Armstrong 1996a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_div1 = { 1997a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 1998a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL, 1999a8080f24SNeil Armstrong .bit_idx = 0, 2000a8080f24SNeil Armstrong }, 2001a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2002a8080f24SNeil Armstrong .name = "vclk_div1", 2003a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 20040dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2005a8080f24SNeil Armstrong .num_parents = 1, 2006a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2007a8080f24SNeil Armstrong }, 2008a8080f24SNeil Armstrong }; 2009a8080f24SNeil Armstrong 2010a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_div2_en = { 2011a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2012a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL, 2013a8080f24SNeil Armstrong .bit_idx = 1, 2014a8080f24SNeil Armstrong }, 2015a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2016a8080f24SNeil Armstrong .name = "vclk_div2_en", 2017a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 20180dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2019a8080f24SNeil Armstrong .num_parents = 1, 2020a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2021a8080f24SNeil Armstrong }, 2022a8080f24SNeil Armstrong }; 2023a8080f24SNeil Armstrong 2024a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_div4_en = { 2025a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2026a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL, 2027a8080f24SNeil Armstrong .bit_idx = 2, 2028a8080f24SNeil Armstrong }, 2029a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2030a8080f24SNeil Armstrong .name = "vclk_div4_en", 2031a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 20320dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2033a8080f24SNeil Armstrong .num_parents = 1, 2034a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2035a8080f24SNeil Armstrong }, 2036a8080f24SNeil Armstrong }; 2037a8080f24SNeil Armstrong 2038a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_div6_en = { 2039a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2040a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL, 2041a8080f24SNeil Armstrong .bit_idx = 3, 2042a8080f24SNeil Armstrong }, 2043a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2044a8080f24SNeil Armstrong .name = "vclk_div6_en", 2045a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 20460dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2047a8080f24SNeil Armstrong .num_parents = 1, 2048a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2049a8080f24SNeil Armstrong }, 2050a8080f24SNeil Armstrong }; 2051a8080f24SNeil Armstrong 2052a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_div12_en = { 2053a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2054a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL, 2055a8080f24SNeil Armstrong .bit_idx = 4, 2056a8080f24SNeil Armstrong }, 2057a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2058a8080f24SNeil Armstrong .name = "vclk_div12_en", 2059a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 20600dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2061a8080f24SNeil Armstrong .num_parents = 1, 2062a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2063a8080f24SNeil Armstrong }, 2064a8080f24SNeil Armstrong }; 2065a8080f24SNeil Armstrong 2066a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_div1 = { 2067a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2068a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_CNTL, 2069a8080f24SNeil Armstrong .bit_idx = 0, 2070a8080f24SNeil Armstrong }, 2071a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2072a8080f24SNeil Armstrong .name = "vclk2_div1", 2073a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 20740dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2075a8080f24SNeil Armstrong .num_parents = 1, 2076a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2077a8080f24SNeil Armstrong }, 2078a8080f24SNeil Armstrong }; 2079a8080f24SNeil Armstrong 2080a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_div2_en = { 2081a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2082a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_CNTL, 2083a8080f24SNeil Armstrong .bit_idx = 1, 2084a8080f24SNeil Armstrong }, 2085a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2086a8080f24SNeil Armstrong .name = "vclk2_div2_en", 2087a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 20880dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2089a8080f24SNeil Armstrong .num_parents = 1, 2090a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2091a8080f24SNeil Armstrong }, 2092a8080f24SNeil Armstrong }; 2093a8080f24SNeil Armstrong 2094a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_div4_en = { 2095a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2096a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_CNTL, 2097a8080f24SNeil Armstrong .bit_idx = 2, 2098a8080f24SNeil Armstrong }, 2099a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2100a8080f24SNeil Armstrong .name = "vclk2_div4_en", 2101a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 21020dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2103a8080f24SNeil Armstrong .num_parents = 1, 2104a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2105a8080f24SNeil Armstrong }, 2106a8080f24SNeil Armstrong }; 2107a8080f24SNeil Armstrong 2108a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_div6_en = { 2109a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2110a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_CNTL, 2111a8080f24SNeil Armstrong .bit_idx = 3, 2112a8080f24SNeil Armstrong }, 2113a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2114a8080f24SNeil Armstrong .name = "vclk2_div6_en", 2115a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 21160dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2117a8080f24SNeil Armstrong .num_parents = 1, 2118a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2119a8080f24SNeil Armstrong }, 2120a8080f24SNeil Armstrong }; 2121a8080f24SNeil Armstrong 2122a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_div12_en = { 2123a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2124a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_CNTL, 2125a8080f24SNeil Armstrong .bit_idx = 4, 2126a8080f24SNeil Armstrong }, 2127a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2128a8080f24SNeil Armstrong .name = "vclk2_div12_en", 2129a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 21300dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2131a8080f24SNeil Armstrong .num_parents = 1, 2132a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2133a8080f24SNeil Armstrong }, 2134a8080f24SNeil Armstrong }; 2135a8080f24SNeil Armstrong 2136a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk_div2 = { 2137a8080f24SNeil Armstrong .mult = 1, 2138a8080f24SNeil Armstrong .div = 2, 2139a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2140a8080f24SNeil Armstrong .name = "vclk_div2", 2141a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 21420dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 21430dea3f35SAlexandre Mergnat &gxbb_vclk_div2_en.hw 21440dea3f35SAlexandre Mergnat }, 2145a8080f24SNeil Armstrong .num_parents = 1, 2146a8080f24SNeil Armstrong }, 2147a8080f24SNeil Armstrong }; 2148a8080f24SNeil Armstrong 2149a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk_div4 = { 2150a8080f24SNeil Armstrong .mult = 1, 2151a8080f24SNeil Armstrong .div = 4, 2152a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2153a8080f24SNeil Armstrong .name = "vclk_div4", 2154a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 21550dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 21560dea3f35SAlexandre Mergnat &gxbb_vclk_div4_en.hw 21570dea3f35SAlexandre Mergnat }, 2158a8080f24SNeil Armstrong .num_parents = 1, 2159a8080f24SNeil Armstrong }, 2160a8080f24SNeil Armstrong }; 2161a8080f24SNeil Armstrong 2162a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk_div6 = { 2163a8080f24SNeil Armstrong .mult = 1, 2164a8080f24SNeil Armstrong .div = 6, 2165a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2166a8080f24SNeil Armstrong .name = "vclk_div6", 2167a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 21680dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 21690dea3f35SAlexandre Mergnat &gxbb_vclk_div6_en.hw 21700dea3f35SAlexandre Mergnat }, 2171a8080f24SNeil Armstrong .num_parents = 1, 2172a8080f24SNeil Armstrong }, 2173a8080f24SNeil Armstrong }; 2174a8080f24SNeil Armstrong 2175a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk_div12 = { 2176a8080f24SNeil Armstrong .mult = 1, 2177a8080f24SNeil Armstrong .div = 12, 2178a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2179a8080f24SNeil Armstrong .name = "vclk_div12", 2180a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 21810dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 21820dea3f35SAlexandre Mergnat &gxbb_vclk_div12_en.hw 21830dea3f35SAlexandre Mergnat }, 2184a8080f24SNeil Armstrong .num_parents = 1, 2185a8080f24SNeil Armstrong }, 2186a8080f24SNeil Armstrong }; 2187a8080f24SNeil Armstrong 2188a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk2_div2 = { 2189a8080f24SNeil Armstrong .mult = 1, 2190a8080f24SNeil Armstrong .div = 2, 2191a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2192a8080f24SNeil Armstrong .name = "vclk2_div2", 2193a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 21940dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 21950dea3f35SAlexandre Mergnat &gxbb_vclk2_div2_en.hw 21960dea3f35SAlexandre Mergnat }, 2197a8080f24SNeil Armstrong .num_parents = 1, 2198a8080f24SNeil Armstrong }, 2199a8080f24SNeil Armstrong }; 2200a8080f24SNeil Armstrong 2201a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk2_div4 = { 2202a8080f24SNeil Armstrong .mult = 1, 2203a8080f24SNeil Armstrong .div = 4, 2204a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2205a8080f24SNeil Armstrong .name = "vclk2_div4", 2206a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 22070dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 22080dea3f35SAlexandre Mergnat &gxbb_vclk2_div4_en.hw 22090dea3f35SAlexandre Mergnat }, 2210a8080f24SNeil Armstrong .num_parents = 1, 2211a8080f24SNeil Armstrong }, 2212a8080f24SNeil Armstrong }; 2213a8080f24SNeil Armstrong 2214a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk2_div6 = { 2215a8080f24SNeil Armstrong .mult = 1, 2216a8080f24SNeil Armstrong .div = 6, 2217a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2218a8080f24SNeil Armstrong .name = "vclk2_div6", 2219a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 22200dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 22210dea3f35SAlexandre Mergnat &gxbb_vclk2_div6_en.hw 22220dea3f35SAlexandre Mergnat }, 2223a8080f24SNeil Armstrong .num_parents = 1, 2224a8080f24SNeil Armstrong }, 2225a8080f24SNeil Armstrong }; 2226a8080f24SNeil Armstrong 2227a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk2_div12 = { 2228a8080f24SNeil Armstrong .mult = 1, 2229a8080f24SNeil Armstrong .div = 12, 2230a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2231a8080f24SNeil Armstrong .name = "vclk2_div12", 2232a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 22330dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 22340dea3f35SAlexandre Mergnat &gxbb_vclk2_div12_en.hw 22350dea3f35SAlexandre Mergnat }, 2236a8080f24SNeil Armstrong .num_parents = 1, 2237a8080f24SNeil Armstrong }, 2238a8080f24SNeil Armstrong }; 2239a8080f24SNeil Armstrong 2240a8080f24SNeil Armstrong static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 22410dea3f35SAlexandre Mergnat static const struct clk_hw *gxbb_cts_parent_hws[] = { 22420dea3f35SAlexandre Mergnat &gxbb_vclk_div1.hw, 22430dea3f35SAlexandre Mergnat &gxbb_vclk_div2.hw, 22440dea3f35SAlexandre Mergnat &gxbb_vclk_div4.hw, 22450dea3f35SAlexandre Mergnat &gxbb_vclk_div6.hw, 22460dea3f35SAlexandre Mergnat &gxbb_vclk_div12.hw, 22470dea3f35SAlexandre Mergnat &gxbb_vclk2_div1.hw, 22480dea3f35SAlexandre Mergnat &gxbb_vclk2_div2.hw, 22490dea3f35SAlexandre Mergnat &gxbb_vclk2_div4.hw, 22500dea3f35SAlexandre Mergnat &gxbb_vclk2_div6.hw, 22510dea3f35SAlexandre Mergnat &gxbb_vclk2_div12.hw, 2252a8080f24SNeil Armstrong }; 2253a8080f24SNeil Armstrong 2254a8080f24SNeil Armstrong static struct clk_regmap gxbb_cts_enci_sel = { 2255a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 2256a8080f24SNeil Armstrong .offset = HHI_VID_CLK_DIV, 2257a8080f24SNeil Armstrong .mask = 0xf, 2258a8080f24SNeil Armstrong .shift = 28, 2259a8080f24SNeil Armstrong .table = mux_table_cts_sel, 2260a8080f24SNeil Armstrong }, 2261a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2262a8080f24SNeil Armstrong .name = "cts_enci_sel", 2263a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 22640dea3f35SAlexandre Mergnat .parent_hws = gxbb_cts_parent_hws, 22650dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws), 2266a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2267a8080f24SNeil Armstrong }, 2268a8080f24SNeil Armstrong }; 2269a8080f24SNeil Armstrong 2270a8080f24SNeil Armstrong static struct clk_regmap gxbb_cts_encp_sel = { 2271a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 2272a8080f24SNeil Armstrong .offset = HHI_VID_CLK_DIV, 2273a8080f24SNeil Armstrong .mask = 0xf, 2274a8080f24SNeil Armstrong .shift = 20, 2275a8080f24SNeil Armstrong .table = mux_table_cts_sel, 2276a8080f24SNeil Armstrong }, 2277a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2278a8080f24SNeil Armstrong .name = "cts_encp_sel", 2279a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 22800dea3f35SAlexandre Mergnat .parent_hws = gxbb_cts_parent_hws, 22810dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws), 2282a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2283a8080f24SNeil Armstrong }, 2284a8080f24SNeil Armstrong }; 2285a8080f24SNeil Armstrong 2286a8080f24SNeil Armstrong static struct clk_regmap gxbb_cts_vdac_sel = { 2287a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 2288a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_DIV, 2289a8080f24SNeil Armstrong .mask = 0xf, 2290a8080f24SNeil Armstrong .shift = 28, 2291a8080f24SNeil Armstrong .table = mux_table_cts_sel, 2292a8080f24SNeil Armstrong }, 2293a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2294a8080f24SNeil Armstrong .name = "cts_vdac_sel", 2295a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 22960dea3f35SAlexandre Mergnat .parent_hws = gxbb_cts_parent_hws, 22970dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws), 2298a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2299a8080f24SNeil Armstrong }, 2300a8080f24SNeil Armstrong }; 2301a8080f24SNeil Armstrong 2302a8080f24SNeil Armstrong /* TOFIX: add support for cts_tcon */ 2303a8080f24SNeil Armstrong static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 23040dea3f35SAlexandre Mergnat static const struct clk_hw *gxbb_cts_hdmi_tx_parent_hws[] = { 23050dea3f35SAlexandre Mergnat &gxbb_vclk_div1.hw, 23060dea3f35SAlexandre Mergnat &gxbb_vclk_div2.hw, 23070dea3f35SAlexandre Mergnat &gxbb_vclk_div4.hw, 23080dea3f35SAlexandre Mergnat &gxbb_vclk_div6.hw, 23090dea3f35SAlexandre Mergnat &gxbb_vclk_div12.hw, 23100dea3f35SAlexandre Mergnat &gxbb_vclk2_div1.hw, 23110dea3f35SAlexandre Mergnat &gxbb_vclk2_div2.hw, 23120dea3f35SAlexandre Mergnat &gxbb_vclk2_div4.hw, 23130dea3f35SAlexandre Mergnat &gxbb_vclk2_div6.hw, 23140dea3f35SAlexandre Mergnat &gxbb_vclk2_div12.hw, 2315a8080f24SNeil Armstrong }; 2316a8080f24SNeil Armstrong 2317a8080f24SNeil Armstrong static struct clk_regmap gxbb_hdmi_tx_sel = { 2318a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 2319a8080f24SNeil Armstrong .offset = HHI_HDMI_CLK_CNTL, 2320a8080f24SNeil Armstrong .mask = 0xf, 2321a8080f24SNeil Armstrong .shift = 16, 2322a8080f24SNeil Armstrong .table = mux_table_hdmi_tx_sel, 2323a8080f24SNeil Armstrong }, 2324a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2325a8080f24SNeil Armstrong .name = "hdmi_tx_sel", 2326a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 2327a8080f24SNeil Armstrong /* 2328a8080f24SNeil Armstrong * bits 31:28 selects from 12 possible parents: 2329a8080f24SNeil Armstrong * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12 2330a8080f24SNeil Armstrong * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12, 2331a8080f24SNeil Armstrong * cts_tcon 2332a8080f24SNeil Armstrong */ 23330dea3f35SAlexandre Mergnat .parent_hws = gxbb_cts_hdmi_tx_parent_hws, 23340dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_hws), 2335a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2336a8080f24SNeil Armstrong }, 2337a8080f24SNeil Armstrong }; 2338a8080f24SNeil Armstrong 2339a8080f24SNeil Armstrong static struct clk_regmap gxbb_cts_enci = { 2340a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2341a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL2, 2342a8080f24SNeil Armstrong .bit_idx = 0, 2343a8080f24SNeil Armstrong }, 2344a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2345a8080f24SNeil Armstrong .name = "cts_enci", 2346a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 23470dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 23480dea3f35SAlexandre Mergnat &gxbb_cts_enci_sel.hw 23490dea3f35SAlexandre Mergnat }, 2350a8080f24SNeil Armstrong .num_parents = 1, 2351a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2352a8080f24SNeil Armstrong }, 2353a8080f24SNeil Armstrong }; 2354a8080f24SNeil Armstrong 2355a8080f24SNeil Armstrong static struct clk_regmap gxbb_cts_encp = { 2356a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2357a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL2, 2358a8080f24SNeil Armstrong .bit_idx = 2, 2359a8080f24SNeil Armstrong }, 2360a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2361a8080f24SNeil Armstrong .name = "cts_encp", 2362a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 23630dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 23640dea3f35SAlexandre Mergnat &gxbb_cts_encp_sel.hw 23650dea3f35SAlexandre Mergnat }, 2366a8080f24SNeil Armstrong .num_parents = 1, 2367a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2368a8080f24SNeil Armstrong }, 2369a8080f24SNeil Armstrong }; 2370a8080f24SNeil Armstrong 2371a8080f24SNeil Armstrong static struct clk_regmap gxbb_cts_vdac = { 2372a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2373a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL2, 2374a8080f24SNeil Armstrong .bit_idx = 4, 2375a8080f24SNeil Armstrong }, 2376a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2377a8080f24SNeil Armstrong .name = "cts_vdac", 2378a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 23790dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 23800dea3f35SAlexandre Mergnat &gxbb_cts_vdac_sel.hw 23810dea3f35SAlexandre Mergnat }, 2382a8080f24SNeil Armstrong .num_parents = 1, 2383a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2384a8080f24SNeil Armstrong }, 2385a8080f24SNeil Armstrong }; 2386a8080f24SNeil Armstrong 2387a8080f24SNeil Armstrong static struct clk_regmap gxbb_hdmi_tx = { 2388a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2389a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL2, 2390a8080f24SNeil Armstrong .bit_idx = 5, 2391a8080f24SNeil Armstrong }, 2392a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2393a8080f24SNeil Armstrong .name = "hdmi_tx", 2394a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 23950dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 23960dea3f35SAlexandre Mergnat &gxbb_hdmi_tx_sel.hw 23970dea3f35SAlexandre Mergnat }, 2398a8080f24SNeil Armstrong .num_parents = 1, 2399a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2400a8080f24SNeil Armstrong }, 2401a8080f24SNeil Armstrong }; 2402a8080f24SNeil Armstrong 2403a8080f24SNeil Armstrong /* HDMI Clocks */ 2404a8080f24SNeil Armstrong 24050dea3f35SAlexandre Mergnat static const struct clk_parent_data gxbb_hdmi_parent_data[] = { 24060dea3f35SAlexandre Mergnat { .fw_name = "xtal", }, 24070dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div4.hw }, 24080dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div3.hw }, 24090dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div5.hw }, 2410a8080f24SNeil Armstrong }; 2411a8080f24SNeil Armstrong 2412a8080f24SNeil Armstrong static struct clk_regmap gxbb_hdmi_sel = { 2413a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 2414a8080f24SNeil Armstrong .offset = HHI_HDMI_CLK_CNTL, 2415a8080f24SNeil Armstrong .mask = 0x3, 2416a8080f24SNeil Armstrong .shift = 9, 2417a8080f24SNeil Armstrong .flags = CLK_MUX_ROUND_CLOSEST, 2418a8080f24SNeil Armstrong }, 2419a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2420a8080f24SNeil Armstrong .name = "hdmi_sel", 2421a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 24220dea3f35SAlexandre Mergnat .parent_data = gxbb_hdmi_parent_data, 24230dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_hdmi_parent_data), 2424a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2425a8080f24SNeil Armstrong }, 2426a8080f24SNeil Armstrong }; 2427a8080f24SNeil Armstrong 2428a8080f24SNeil Armstrong static struct clk_regmap gxbb_hdmi_div = { 2429a8080f24SNeil Armstrong .data = &(struct clk_regmap_div_data){ 2430a8080f24SNeil Armstrong .offset = HHI_HDMI_CLK_CNTL, 2431a8080f24SNeil Armstrong .shift = 0, 2432a8080f24SNeil Armstrong .width = 7, 2433a8080f24SNeil Armstrong }, 2434a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2435a8080f24SNeil Armstrong .name = "hdmi_div", 2436a8080f24SNeil Armstrong .ops = &clk_regmap_divider_ops, 24370dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_sel.hw }, 2438a8080f24SNeil Armstrong .num_parents = 1, 2439a8080f24SNeil Armstrong .flags = CLK_GET_RATE_NOCACHE, 2440a8080f24SNeil Armstrong }, 2441a8080f24SNeil Armstrong }; 2442a8080f24SNeil Armstrong 2443a8080f24SNeil Armstrong static struct clk_regmap gxbb_hdmi = { 2444a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2445a8080f24SNeil Armstrong .offset = HHI_HDMI_CLK_CNTL, 2446a8080f24SNeil Armstrong .bit_idx = 8, 2447a8080f24SNeil Armstrong }, 2448a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2449a8080f24SNeil Armstrong .name = "hdmi", 2450a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 24510dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_div.hw }, 2452a8080f24SNeil Armstrong .num_parents = 1, 2453a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2454a8080f24SNeil Armstrong }, 2455a8080f24SNeil Armstrong }; 2456a8080f24SNeil Armstrong 2457a565242eSMaxime Jourdan /* VDEC clocks */ 2458a565242eSMaxime Jourdan 24590dea3f35SAlexandre Mergnat static const struct clk_hw *gxbb_vdec_parent_hws[] = { 24600dea3f35SAlexandre Mergnat &gxbb_fclk_div4.hw, 24610dea3f35SAlexandre Mergnat &gxbb_fclk_div3.hw, 24620dea3f35SAlexandre Mergnat &gxbb_fclk_div5.hw, 24630dea3f35SAlexandre Mergnat &gxbb_fclk_div7.hw, 2464a565242eSMaxime Jourdan }; 2465a565242eSMaxime Jourdan 2466a565242eSMaxime Jourdan static struct clk_regmap gxbb_vdec_1_sel = { 2467a565242eSMaxime Jourdan .data = &(struct clk_regmap_mux_data){ 2468a565242eSMaxime Jourdan .offset = HHI_VDEC_CLK_CNTL, 2469a565242eSMaxime Jourdan .mask = 0x3, 2470a565242eSMaxime Jourdan .shift = 9, 2471a565242eSMaxime Jourdan .flags = CLK_MUX_ROUND_CLOSEST, 2472a565242eSMaxime Jourdan }, 2473a565242eSMaxime Jourdan .hw.init = &(struct clk_init_data){ 2474a565242eSMaxime Jourdan .name = "vdec_1_sel", 2475a565242eSMaxime Jourdan .ops = &clk_regmap_mux_ops, 24760dea3f35SAlexandre Mergnat .parent_hws = gxbb_vdec_parent_hws, 24770dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws), 2478a565242eSMaxime Jourdan .flags = CLK_SET_RATE_PARENT, 2479a565242eSMaxime Jourdan }, 2480a565242eSMaxime Jourdan }; 2481a565242eSMaxime Jourdan 2482a565242eSMaxime Jourdan static struct clk_regmap gxbb_vdec_1_div = { 2483a565242eSMaxime Jourdan .data = &(struct clk_regmap_div_data){ 2484a565242eSMaxime Jourdan .offset = HHI_VDEC_CLK_CNTL, 2485a565242eSMaxime Jourdan .shift = 0, 2486a565242eSMaxime Jourdan .width = 7, 24879b70c697SMaxime Jourdan .flags = CLK_DIVIDER_ROUND_CLOSEST, 2488a565242eSMaxime Jourdan }, 2489a565242eSMaxime Jourdan .hw.init = &(struct clk_init_data){ 2490a565242eSMaxime Jourdan .name = "vdec_1_div", 2491a565242eSMaxime Jourdan .ops = &clk_regmap_divider_ops, 24920dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 24930dea3f35SAlexandre Mergnat &gxbb_vdec_1_sel.hw 24940dea3f35SAlexandre Mergnat }, 2495a565242eSMaxime Jourdan .num_parents = 1, 2496a565242eSMaxime Jourdan .flags = CLK_SET_RATE_PARENT, 2497a565242eSMaxime Jourdan }, 2498a565242eSMaxime Jourdan }; 2499a565242eSMaxime Jourdan 2500a565242eSMaxime Jourdan static struct clk_regmap gxbb_vdec_1 = { 2501a565242eSMaxime Jourdan .data = &(struct clk_regmap_gate_data){ 2502a565242eSMaxime Jourdan .offset = HHI_VDEC_CLK_CNTL, 2503a565242eSMaxime Jourdan .bit_idx = 8, 2504a565242eSMaxime Jourdan }, 2505a565242eSMaxime Jourdan .hw.init = &(struct clk_init_data) { 2506a565242eSMaxime Jourdan .name = "vdec_1", 2507a565242eSMaxime Jourdan .ops = &clk_regmap_gate_ops, 25080dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 25090dea3f35SAlexandre Mergnat &gxbb_vdec_1_div.hw 25100dea3f35SAlexandre Mergnat }, 2511a565242eSMaxime Jourdan .num_parents = 1, 2512a565242eSMaxime Jourdan .flags = CLK_SET_RATE_PARENT, 2513a565242eSMaxime Jourdan }, 2514a565242eSMaxime Jourdan }; 2515a565242eSMaxime Jourdan 2516a565242eSMaxime Jourdan static struct clk_regmap gxbb_vdec_hevc_sel = { 2517a565242eSMaxime Jourdan .data = &(struct clk_regmap_mux_data){ 2518a565242eSMaxime Jourdan .offset = HHI_VDEC2_CLK_CNTL, 2519a565242eSMaxime Jourdan .mask = 0x3, 2520a565242eSMaxime Jourdan .shift = 25, 2521a565242eSMaxime Jourdan .flags = CLK_MUX_ROUND_CLOSEST, 2522a565242eSMaxime Jourdan }, 2523a565242eSMaxime Jourdan .hw.init = &(struct clk_init_data){ 2524a565242eSMaxime Jourdan .name = "vdec_hevc_sel", 2525a565242eSMaxime Jourdan .ops = &clk_regmap_mux_ops, 25260dea3f35SAlexandre Mergnat .parent_hws = gxbb_vdec_parent_hws, 25270dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws), 2528a565242eSMaxime Jourdan .flags = CLK_SET_RATE_PARENT, 2529a565242eSMaxime Jourdan }, 2530a565242eSMaxime Jourdan }; 2531a565242eSMaxime Jourdan 2532a565242eSMaxime Jourdan static struct clk_regmap gxbb_vdec_hevc_div = { 2533a565242eSMaxime Jourdan .data = &(struct clk_regmap_div_data){ 2534a565242eSMaxime Jourdan .offset = HHI_VDEC2_CLK_CNTL, 2535a565242eSMaxime Jourdan .shift = 16, 2536a565242eSMaxime Jourdan .width = 7, 25379b70c697SMaxime Jourdan .flags = CLK_DIVIDER_ROUND_CLOSEST, 2538a565242eSMaxime Jourdan }, 2539a565242eSMaxime Jourdan .hw.init = &(struct clk_init_data){ 2540a565242eSMaxime Jourdan .name = "vdec_hevc_div", 2541a565242eSMaxime Jourdan .ops = &clk_regmap_divider_ops, 25420dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 25430dea3f35SAlexandre Mergnat &gxbb_vdec_hevc_sel.hw 25440dea3f35SAlexandre Mergnat }, 2545a565242eSMaxime Jourdan .num_parents = 1, 2546a565242eSMaxime Jourdan .flags = CLK_SET_RATE_PARENT, 2547a565242eSMaxime Jourdan }, 2548a565242eSMaxime Jourdan }; 2549a565242eSMaxime Jourdan 2550a565242eSMaxime Jourdan static struct clk_regmap gxbb_vdec_hevc = { 2551a565242eSMaxime Jourdan .data = &(struct clk_regmap_gate_data){ 2552a565242eSMaxime Jourdan .offset = HHI_VDEC2_CLK_CNTL, 2553a565242eSMaxime Jourdan .bit_idx = 24, 2554a565242eSMaxime Jourdan }, 2555a565242eSMaxime Jourdan .hw.init = &(struct clk_init_data) { 2556a565242eSMaxime Jourdan .name = "vdec_hevc", 2557a565242eSMaxime Jourdan .ops = &clk_regmap_gate_ops, 25580dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 25590dea3f35SAlexandre Mergnat &gxbb_vdec_hevc_div.hw 25600dea3f35SAlexandre Mergnat }, 2561a565242eSMaxime Jourdan .num_parents = 1, 2562a565242eSMaxime Jourdan .flags = CLK_SET_RATE_PARENT, 2563a565242eSMaxime Jourdan }, 2564a565242eSMaxime Jourdan }; 2565a565242eSMaxime Jourdan 25667df533a7SJerome Brunet static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8, 25677df533a7SJerome Brunet 9, 10, 11, 13, 14, }; 25680dea3f35SAlexandre Mergnat static const struct clk_parent_data gen_clk_parent_data[] = { 25690dea3f35SAlexandre Mergnat { .fw_name = "xtal", }, 25700dea3f35SAlexandre Mergnat { .hw = &gxbb_vdec_1.hw }, 25710dea3f35SAlexandre Mergnat { .hw = &gxbb_vdec_hevc.hw }, 25720dea3f35SAlexandre Mergnat { .hw = &gxbb_mpll0.hw }, 25730dea3f35SAlexandre Mergnat { .hw = &gxbb_mpll1.hw }, 25740dea3f35SAlexandre Mergnat { .hw = &gxbb_mpll2.hw }, 25750dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div4.hw }, 25760dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div3.hw }, 25770dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div5.hw }, 25780dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div7.hw }, 25790dea3f35SAlexandre Mergnat { .hw = &gxbb_gp0_pll.hw }, 25807df533a7SJerome Brunet }; 25817df533a7SJerome Brunet 25827df533a7SJerome Brunet static struct clk_regmap gxbb_gen_clk_sel = { 25837df533a7SJerome Brunet .data = &(struct clk_regmap_mux_data){ 25847df533a7SJerome Brunet .offset = HHI_GEN_CLK_CNTL, 25857df533a7SJerome Brunet .mask = 0xf, 25867df533a7SJerome Brunet .shift = 12, 25877df533a7SJerome Brunet .table = mux_table_gen_clk, 25887df533a7SJerome Brunet }, 25897df533a7SJerome Brunet .hw.init = &(struct clk_init_data){ 25907df533a7SJerome Brunet .name = "gen_clk_sel", 25917df533a7SJerome Brunet .ops = &clk_regmap_mux_ops, 25927df533a7SJerome Brunet /* 25937df533a7SJerome Brunet * bits 15:12 selects from 14 possible parents: 25947df533a7SJerome Brunet * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt], 25957df533a7SJerome Brunet * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4, 25967df533a7SJerome Brunet * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll 25977df533a7SJerome Brunet */ 25980dea3f35SAlexandre Mergnat .parent_data = gen_clk_parent_data, 25990dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gen_clk_parent_data), 26007df533a7SJerome Brunet }, 26017df533a7SJerome Brunet }; 26027df533a7SJerome Brunet 26037df533a7SJerome Brunet static struct clk_regmap gxbb_gen_clk_div = { 26047df533a7SJerome Brunet .data = &(struct clk_regmap_div_data){ 26057df533a7SJerome Brunet .offset = HHI_GEN_CLK_CNTL, 26067df533a7SJerome Brunet .shift = 0, 26077df533a7SJerome Brunet .width = 11, 26087df533a7SJerome Brunet }, 26097df533a7SJerome Brunet .hw.init = &(struct clk_init_data){ 26107df533a7SJerome Brunet .name = "gen_clk_div", 26117df533a7SJerome Brunet .ops = &clk_regmap_divider_ops, 26120dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 26130dea3f35SAlexandre Mergnat &gxbb_gen_clk_sel.hw 26140dea3f35SAlexandre Mergnat }, 26157df533a7SJerome Brunet .num_parents = 1, 26167df533a7SJerome Brunet .flags = CLK_SET_RATE_PARENT, 26177df533a7SJerome Brunet }, 26187df533a7SJerome Brunet }; 26197df533a7SJerome Brunet 26207df533a7SJerome Brunet static struct clk_regmap gxbb_gen_clk = { 26217df533a7SJerome Brunet .data = &(struct clk_regmap_gate_data){ 26227df533a7SJerome Brunet .offset = HHI_GEN_CLK_CNTL, 26237df533a7SJerome Brunet .bit_idx = 7, 26247df533a7SJerome Brunet }, 26257df533a7SJerome Brunet .hw.init = &(struct clk_init_data){ 26267df533a7SJerome Brunet .name = "gen_clk", 26277df533a7SJerome Brunet .ops = &clk_regmap_gate_ops, 26280dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 26290dea3f35SAlexandre Mergnat &gxbb_gen_clk_div.hw 26300dea3f35SAlexandre Mergnat }, 26317df533a7SJerome Brunet .num_parents = 1, 26327df533a7SJerome Brunet .flags = CLK_SET_RATE_PARENT, 26337df533a7SJerome Brunet }, 26347df533a7SJerome Brunet }; 26357df533a7SJerome Brunet 26363a36044eSAlexandre Mergnat #define MESON_GATE(_name, _reg, _bit) \ 26373a36044eSAlexandre Mergnat MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw) 26383a36044eSAlexandre Mergnat 2639738f66d3SMichael Turquette /* Everything Else (EE) domain gates */ 26407ba64d82SAlexander Müller static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); 26417ba64d82SAlexander Müller static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); 26427ba64d82SAlexander Müller static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5); 26437ba64d82SAlexander Müller static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6); 26447ba64d82SAlexander Müller static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7); 26457ba64d82SAlexander Müller static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8); 26467ba64d82SAlexander Müller static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9); 264775eccf5eSYixun Lan static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10); 26487ba64d82SAlexander Müller static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11); 26497ba64d82SAlexander Müller static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12); 26507ba64d82SAlexander Müller static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13); 26517ba64d82SAlexander Müller static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14); 26527ba64d82SAlexander Müller static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15); 26537ba64d82SAlexander Müller static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16); 26547ba64d82SAlexander Müller static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17); 26557ba64d82SAlexander Müller static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18); 26567ba64d82SAlexander Müller static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19); 26577ba64d82SAlexander Müller static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23); 26587ba64d82SAlexander Müller static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24); 26597ba64d82SAlexander Müller static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25); 26607ba64d82SAlexander Müller static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26); 266173c7ddd8SJerome Brunet static MESON_GATE(gxl_acodec, HHI_GCLK_MPEG0, 28); 26627ba64d82SAlexander Müller static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30); 2663738f66d3SMichael Turquette 26647ba64d82SAlexander Müller static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2); 26657ba64d82SAlexander Müller static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3); 26667ba64d82SAlexander Müller static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4); 26677ba64d82SAlexander Müller static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14); 26687ba64d82SAlexander Müller static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15); 26697ba64d82SAlexander Müller static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16); 26707ba64d82SAlexander Müller static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20); 26717ba64d82SAlexander Müller static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21); 26727ba64d82SAlexander Müller static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22); 26737ba64d82SAlexander Müller static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23); 26747ba64d82SAlexander Müller static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24); 26757ba64d82SAlexander Müller static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25); 26767ba64d82SAlexander Müller static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26); 26777ba64d82SAlexander Müller static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28); 26787ba64d82SAlexander Müller static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29); 26797ba64d82SAlexander Müller static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30); 26807ba64d82SAlexander Müller static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31); 2681738f66d3SMichael Turquette 26827ba64d82SAlexander Müller static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1); 26837ba64d82SAlexander Müller static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 26847ba64d82SAlexander Müller static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); 26857ba64d82SAlexander Müller static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4); 26867ba64d82SAlexander Müller static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); 26877ba64d82SAlexander Müller static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); 26887ba64d82SAlexander Müller static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11); 26897ba64d82SAlexander Müller static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12); 26907ba64d82SAlexander Müller static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15); 269175eccf5eSYixun Lan static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22); 26927ba64d82SAlexander Müller static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25); 26937ba64d82SAlexander Müller static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 26947ba64d82SAlexander Müller static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29); 2695738f66d3SMichael Turquette 26967ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1); 26977ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2); 26987ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3); 26997ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4); 27007ba64d82SAlexander Müller static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8); 27017ba64d82SAlexander Müller static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9); 27027ba64d82SAlexander Müller static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10); 27037ba64d82SAlexander Müller static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14); 27047ba64d82SAlexander Müller static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16); 27057ba64d82SAlexander Müller static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20); 27067ba64d82SAlexander Müller static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21); 27077ba64d82SAlexander Müller static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22); 27087ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24); 27097ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25); 27107ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26); 27117ba64d82SAlexander Müller static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31); 2712738f66d3SMichael Turquette 2713738f66d3SMichael Turquette /* Always On (AO) domain gates */ 2714738f66d3SMichael Turquette 27157ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0); 27167ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1); 27177ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2); 27187ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3); 27197ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4); 2720738f66d3SMichael Turquette 272183b89a75SJerome Brunet /* AIU gates */ 272283b89a75SJerome Brunet static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw); 272383b89a75SJerome Brunet static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw); 272483b89a75SJerome Brunet static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw); 272583b89a75SJerome Brunet static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw); 272683b89a75SJerome Brunet static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw); 272783b89a75SJerome Brunet static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw); 272883b89a75SJerome Brunet static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw); 272983b89a75SJerome Brunet static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw); 273083b89a75SJerome Brunet 2731738f66d3SMichael Turquette /* Array of all clocks provided by this provider */ 2732738f66d3SMichael Turquette 2733141fbc27SNeil Armstrong static struct clk_hw *gxbb_hw_clks[] = { 2734738f66d3SMichael Turquette [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 2735738f66d3SMichael Turquette [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, 2736738f66d3SMichael Turquette [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 2737738f66d3SMichael Turquette [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 2738738f66d3SMichael Turquette [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 2739738f66d3SMichael Turquette [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 2740738f66d3SMichael Turquette [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 2741738f66d3SMichael Turquette [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 2742738f66d3SMichael Turquette [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 2743738f66d3SMichael Turquette [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 2744738f66d3SMichael Turquette [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 2745738f66d3SMichael Turquette [CLKID_CLK81] = &gxbb_clk81.hw, 2746738f66d3SMichael Turquette [CLKID_MPLL0] = &gxbb_mpll0.hw, 2747738f66d3SMichael Turquette [CLKID_MPLL1] = &gxbb_mpll1.hw, 2748738f66d3SMichael Turquette [CLKID_MPLL2] = &gxbb_mpll2.hw, 2749738f66d3SMichael Turquette [CLKID_DDR] = &gxbb_ddr.hw, 2750738f66d3SMichael Turquette [CLKID_DOS] = &gxbb_dos.hw, 2751738f66d3SMichael Turquette [CLKID_ISA] = &gxbb_isa.hw, 2752738f66d3SMichael Turquette [CLKID_PL301] = &gxbb_pl301.hw, 2753738f66d3SMichael Turquette [CLKID_PERIPHS] = &gxbb_periphs.hw, 2754738f66d3SMichael Turquette [CLKID_SPICC] = &gxbb_spicc.hw, 2755738f66d3SMichael Turquette [CLKID_I2C] = &gxbb_i2c.hw, 2756738f66d3SMichael Turquette [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 2757738f66d3SMichael Turquette [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 2758738f66d3SMichael Turquette [CLKID_RNG0] = &gxbb_rng0.hw, 2759738f66d3SMichael Turquette [CLKID_UART0] = &gxbb_uart0.hw, 2760738f66d3SMichael Turquette [CLKID_SDHC] = &gxbb_sdhc.hw, 2761738f66d3SMichael Turquette [CLKID_STREAM] = &gxbb_stream.hw, 2762738f66d3SMichael Turquette [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 2763738f66d3SMichael Turquette [CLKID_SDIO] = &gxbb_sdio.hw, 2764738f66d3SMichael Turquette [CLKID_ABUF] = &gxbb_abuf.hw, 2765738f66d3SMichael Turquette [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 2766738f66d3SMichael Turquette [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 2767738f66d3SMichael Turquette [CLKID_SPI] = &gxbb_spi.hw, 2768738f66d3SMichael Turquette [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 2769738f66d3SMichael Turquette [CLKID_ETH] = &gxbb_eth.hw, 2770738f66d3SMichael Turquette [CLKID_DEMUX] = &gxbb_demux.hw, 2771738f66d3SMichael Turquette [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 2772738f66d3SMichael Turquette [CLKID_IEC958] = &gxbb_iec958.hw, 2773738f66d3SMichael Turquette [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 2774738f66d3SMichael Turquette [CLKID_AMCLK] = &gxbb_amclk.hw, 2775738f66d3SMichael Turquette [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 2776738f66d3SMichael Turquette [CLKID_MIXER] = &gxbb_mixer.hw, 2777738f66d3SMichael Turquette [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 2778738f66d3SMichael Turquette [CLKID_ADC] = &gxbb_adc.hw, 2779738f66d3SMichael Turquette [CLKID_BLKMV] = &gxbb_blkmv.hw, 2780738f66d3SMichael Turquette [CLKID_AIU] = &gxbb_aiu.hw, 2781738f66d3SMichael Turquette [CLKID_UART1] = &gxbb_uart1.hw, 2782738f66d3SMichael Turquette [CLKID_G2D] = &gxbb_g2d.hw, 2783738f66d3SMichael Turquette [CLKID_USB0] = &gxbb_usb0.hw, 2784738f66d3SMichael Turquette [CLKID_USB1] = &gxbb_usb1.hw, 2785738f66d3SMichael Turquette [CLKID_RESET] = &gxbb_reset.hw, 2786738f66d3SMichael Turquette [CLKID_NAND] = &gxbb_nand.hw, 2787738f66d3SMichael Turquette [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 2788738f66d3SMichael Turquette [CLKID_USB] = &gxbb_usb.hw, 2789738f66d3SMichael Turquette [CLKID_VDIN1] = &gxbb_vdin1.hw, 2790738f66d3SMichael Turquette [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 2791738f66d3SMichael Turquette [CLKID_EFUSE] = &gxbb_efuse.hw, 2792738f66d3SMichael Turquette [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 2793738f66d3SMichael Turquette [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 2794738f66d3SMichael Turquette [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 2795738f66d3SMichael Turquette [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 2796738f66d3SMichael Turquette [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 2797738f66d3SMichael Turquette [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 2798738f66d3SMichael Turquette [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 2799738f66d3SMichael Turquette [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 2800738f66d3SMichael Turquette [CLKID_DVIN] = &gxbb_dvin.hw, 2801738f66d3SMichael Turquette [CLKID_UART2] = &gxbb_uart2.hw, 2802738f66d3SMichael Turquette [CLKID_SANA] = &gxbb_sana.hw, 2803738f66d3SMichael Turquette [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 2804738f66d3SMichael Turquette [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 2805738f66d3SMichael Turquette [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 2806738f66d3SMichael Turquette [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 2807738f66d3SMichael Turquette [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 2808738f66d3SMichael Turquette [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 2809738f66d3SMichael Turquette [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 2810738f66d3SMichael Turquette [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 2811738f66d3SMichael Turquette [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 2812738f66d3SMichael Turquette [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 2813738f66d3SMichael Turquette [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 2814738f66d3SMichael Turquette [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 2815738f66d3SMichael Turquette [CLKID_ENC480P] = &gxbb_enc480p.hw, 2816738f66d3SMichael Turquette [CLKID_RNG1] = &gxbb_rng1.hw, 2817738f66d3SMichael Turquette [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 2818738f66d3SMichael Turquette [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 2819738f66d3SMichael Turquette [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 2820738f66d3SMichael Turquette [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 2821738f66d3SMichael Turquette [CLKID_EDP] = &gxbb_edp.hw, 2822738f66d3SMichael Turquette [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 2823738f66d3SMichael Turquette [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 2824738f66d3SMichael Turquette [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 2825738f66d3SMichael Turquette [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 2826738f66d3SMichael Turquette [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 282733608dcdSKevin Hilman [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 282833608dcdSKevin Hilman [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 282933608dcdSKevin Hilman [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 283033d0fcdfSMartin Blumenstingl [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 283133d0fcdfSMartin Blumenstingl [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 283233d0fcdfSMartin Blumenstingl [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 2833fac9a55bSNeil Armstrong [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 2834fac9a55bSNeil Armstrong [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 2835fac9a55bSNeil Armstrong [CLKID_MALI_0] = &gxbb_mali_0.hw, 2836fac9a55bSNeil Armstrong [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 2837fac9a55bSNeil Armstrong [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 2838fac9a55bSNeil Armstrong [CLKID_MALI_1] = &gxbb_mali_1.hw, 2839fac9a55bSNeil Armstrong [CLKID_MALI] = &gxbb_mali.hw, 28404087bd4bSJerome Brunet [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 28414087bd4bSJerome Brunet [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 28424087bd4bSJerome Brunet [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 28433c277c24SJerome Brunet [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 28443c277c24SJerome Brunet [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 28453c277c24SJerome Brunet [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 28467eaa44f6SJerome Brunet [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 284714c735c8SNeil Armstrong [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 284814c735c8SNeil Armstrong [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 284914c735c8SNeil Armstrong [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 2850914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 2851914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 2852914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 2853914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 2854914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 2855914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 2856914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 2857914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 2858914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 2859762a1f20SNeil Armstrong [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 2860762a1f20SNeil Armstrong [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 2861762a1f20SNeil Armstrong [CLKID_VPU_0] = &gxbb_vpu_0.hw, 2862762a1f20SNeil Armstrong [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 2863762a1f20SNeil Armstrong [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 2864762a1f20SNeil Armstrong [CLKID_VPU_1] = &gxbb_vpu_1.hw, 2865762a1f20SNeil Armstrong [CLKID_VPU] = &gxbb_vpu.hw, 2866762a1f20SNeil Armstrong [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 2867762a1f20SNeil Armstrong [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 2868762a1f20SNeil Armstrong [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 2869762a1f20SNeil Armstrong [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 2870762a1f20SNeil Armstrong [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 2871762a1f20SNeil Armstrong [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 2872762a1f20SNeil Armstrong [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 2873762a1f20SNeil Armstrong [CLKID_VAPB] = &gxbb_vapb.hw, 28743c4fe763SJerome Brunet [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw, 2875d610b54fSJerome Brunet [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw, 2876d610b54fSJerome Brunet [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 2877d610b54fSJerome Brunet [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 2878513b67acSJerome Brunet [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 287905f81440SJerome Brunet [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 288005f81440SJerome Brunet [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 288105f81440SJerome Brunet [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 288205f81440SJerome Brunet [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 288305f81440SJerome Brunet [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 2884a565242eSMaxime Jourdan [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 2885a565242eSMaxime Jourdan [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 2886a565242eSMaxime Jourdan [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 2887a565242eSMaxime Jourdan [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 2888a565242eSMaxime Jourdan [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 2889a565242eSMaxime Jourdan [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 28907df533a7SJerome Brunet [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 28917df533a7SJerome Brunet [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 28927df533a7SJerome Brunet [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 289387173557SJerome Brunet [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw, 289487173557SJerome Brunet [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw, 289587173557SJerome Brunet [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw, 289687173557SJerome Brunet [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw, 289787173557SJerome Brunet [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw, 289887173557SJerome Brunet [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw, 2899a8080f24SNeil Armstrong [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw, 2900a8080f24SNeil Armstrong [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw, 2901a8080f24SNeil Armstrong [CLKID_VID_PLL] = &gxbb_vid_pll.hw, 2902a8080f24SNeil Armstrong [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw, 2903a8080f24SNeil Armstrong [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw, 2904a8080f24SNeil Armstrong [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw, 2905a8080f24SNeil Armstrong [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw, 2906a8080f24SNeil Armstrong [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw, 2907a8080f24SNeil Armstrong [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw, 2908a8080f24SNeil Armstrong [CLKID_VCLK] = &gxbb_vclk.hw, 2909a8080f24SNeil Armstrong [CLKID_VCLK2] = &gxbb_vclk2.hw, 2910a8080f24SNeil Armstrong [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw, 2911a8080f24SNeil Armstrong [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw, 2912a8080f24SNeil Armstrong [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw, 2913a8080f24SNeil Armstrong [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw, 2914a8080f24SNeil Armstrong [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw, 2915a8080f24SNeil Armstrong [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw, 2916a8080f24SNeil Armstrong [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw, 2917a8080f24SNeil Armstrong [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw, 2918a8080f24SNeil Armstrong [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw, 2919a8080f24SNeil Armstrong [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw, 2920a8080f24SNeil Armstrong [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw, 2921a8080f24SNeil Armstrong [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw, 2922a8080f24SNeil Armstrong [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw, 2923a8080f24SNeil Armstrong [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw, 2924a8080f24SNeil Armstrong [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw, 2925a8080f24SNeil Armstrong [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw, 2926a8080f24SNeil Armstrong [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw, 2927a8080f24SNeil Armstrong [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw, 2928a8080f24SNeil Armstrong [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw, 2929a8080f24SNeil Armstrong [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw, 2930a8080f24SNeil Armstrong [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw, 2931a8080f24SNeil Armstrong [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw, 2932a8080f24SNeil Armstrong [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw, 2933a8080f24SNeil Armstrong [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw, 2934a8080f24SNeil Armstrong [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw, 2935a8080f24SNeil Armstrong [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw, 2936a8080f24SNeil Armstrong [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw, 2937a8080f24SNeil Armstrong [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw, 2938a8080f24SNeil Armstrong [CLKID_HDMI] = &gxbb_hdmi.hw, 2939738f66d3SMichael Turquette }; 2940738f66d3SMichael Turquette 2941141fbc27SNeil Armstrong static struct clk_hw *gxl_hw_clks[] = { 29420d48fc55SNeil Armstrong [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 294369d92293SJerome Brunet [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw, 29440d48fc55SNeil Armstrong [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 29450d48fc55SNeil Armstrong [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 29460d48fc55SNeil Armstrong [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 29470d48fc55SNeil Armstrong [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 29480d48fc55SNeil Armstrong [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 29490d48fc55SNeil Armstrong [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 295087173557SJerome Brunet [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 29510d48fc55SNeil Armstrong [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 29520d48fc55SNeil Armstrong [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 29530d48fc55SNeil Armstrong [CLKID_CLK81] = &gxbb_clk81.hw, 29540d48fc55SNeil Armstrong [CLKID_MPLL0] = &gxbb_mpll0.hw, 29550d48fc55SNeil Armstrong [CLKID_MPLL1] = &gxbb_mpll1.hw, 29560d48fc55SNeil Armstrong [CLKID_MPLL2] = &gxbb_mpll2.hw, 29570d48fc55SNeil Armstrong [CLKID_DDR] = &gxbb_ddr.hw, 29580d48fc55SNeil Armstrong [CLKID_DOS] = &gxbb_dos.hw, 29590d48fc55SNeil Armstrong [CLKID_ISA] = &gxbb_isa.hw, 29600d48fc55SNeil Armstrong [CLKID_PL301] = &gxbb_pl301.hw, 29610d48fc55SNeil Armstrong [CLKID_PERIPHS] = &gxbb_periphs.hw, 29620d48fc55SNeil Armstrong [CLKID_SPICC] = &gxbb_spicc.hw, 29630d48fc55SNeil Armstrong [CLKID_I2C] = &gxbb_i2c.hw, 29640d48fc55SNeil Armstrong [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 29650d48fc55SNeil Armstrong [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 29660d48fc55SNeil Armstrong [CLKID_RNG0] = &gxbb_rng0.hw, 29670d48fc55SNeil Armstrong [CLKID_UART0] = &gxbb_uart0.hw, 29680d48fc55SNeil Armstrong [CLKID_SDHC] = &gxbb_sdhc.hw, 29690d48fc55SNeil Armstrong [CLKID_STREAM] = &gxbb_stream.hw, 29700d48fc55SNeil Armstrong [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 29710d48fc55SNeil Armstrong [CLKID_SDIO] = &gxbb_sdio.hw, 29720d48fc55SNeil Armstrong [CLKID_ABUF] = &gxbb_abuf.hw, 29730d48fc55SNeil Armstrong [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 29740d48fc55SNeil Armstrong [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 29750d48fc55SNeil Armstrong [CLKID_SPI] = &gxbb_spi.hw, 29760d48fc55SNeil Armstrong [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 29770d48fc55SNeil Armstrong [CLKID_ETH] = &gxbb_eth.hw, 29780d48fc55SNeil Armstrong [CLKID_DEMUX] = &gxbb_demux.hw, 29790d48fc55SNeil Armstrong [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 29800d48fc55SNeil Armstrong [CLKID_IEC958] = &gxbb_iec958.hw, 29810d48fc55SNeil Armstrong [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 29820d48fc55SNeil Armstrong [CLKID_AMCLK] = &gxbb_amclk.hw, 29830d48fc55SNeil Armstrong [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 29840d48fc55SNeil Armstrong [CLKID_MIXER] = &gxbb_mixer.hw, 29850d48fc55SNeil Armstrong [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 29860d48fc55SNeil Armstrong [CLKID_ADC] = &gxbb_adc.hw, 29870d48fc55SNeil Armstrong [CLKID_BLKMV] = &gxbb_blkmv.hw, 29880d48fc55SNeil Armstrong [CLKID_AIU] = &gxbb_aiu.hw, 29890d48fc55SNeil Armstrong [CLKID_UART1] = &gxbb_uart1.hw, 29900d48fc55SNeil Armstrong [CLKID_G2D] = &gxbb_g2d.hw, 29910d48fc55SNeil Armstrong [CLKID_USB0] = &gxbb_usb0.hw, 29920d48fc55SNeil Armstrong [CLKID_USB1] = &gxbb_usb1.hw, 29930d48fc55SNeil Armstrong [CLKID_RESET] = &gxbb_reset.hw, 29940d48fc55SNeil Armstrong [CLKID_NAND] = &gxbb_nand.hw, 29950d48fc55SNeil Armstrong [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 29960d48fc55SNeil Armstrong [CLKID_USB] = &gxbb_usb.hw, 29970d48fc55SNeil Armstrong [CLKID_VDIN1] = &gxbb_vdin1.hw, 29980d48fc55SNeil Armstrong [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 29990d48fc55SNeil Armstrong [CLKID_EFUSE] = &gxbb_efuse.hw, 30000d48fc55SNeil Armstrong [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 30010d48fc55SNeil Armstrong [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 30020d48fc55SNeil Armstrong [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 30030d48fc55SNeil Armstrong [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 30040d48fc55SNeil Armstrong [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 30050d48fc55SNeil Armstrong [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 30060d48fc55SNeil Armstrong [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 30070d48fc55SNeil Armstrong [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 30080d48fc55SNeil Armstrong [CLKID_DVIN] = &gxbb_dvin.hw, 30090d48fc55SNeil Armstrong [CLKID_UART2] = &gxbb_uart2.hw, 30100d48fc55SNeil Armstrong [CLKID_SANA] = &gxbb_sana.hw, 30110d48fc55SNeil Armstrong [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 30120d48fc55SNeil Armstrong [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 30130d48fc55SNeil Armstrong [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 30140d48fc55SNeil Armstrong [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 30150d48fc55SNeil Armstrong [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 30160d48fc55SNeil Armstrong [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 30170d48fc55SNeil Armstrong [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 30180d48fc55SNeil Armstrong [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 30190d48fc55SNeil Armstrong [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 30200d48fc55SNeil Armstrong [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 30210d48fc55SNeil Armstrong [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 30220d48fc55SNeil Armstrong [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 30230d48fc55SNeil Armstrong [CLKID_ENC480P] = &gxbb_enc480p.hw, 30240d48fc55SNeil Armstrong [CLKID_RNG1] = &gxbb_rng1.hw, 30250d48fc55SNeil Armstrong [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 30260d48fc55SNeil Armstrong [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 30270d48fc55SNeil Armstrong [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 30280d48fc55SNeil Armstrong [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 30290d48fc55SNeil Armstrong [CLKID_EDP] = &gxbb_edp.hw, 30300d48fc55SNeil Armstrong [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 30310d48fc55SNeil Armstrong [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 30320d48fc55SNeil Armstrong [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 30330d48fc55SNeil Armstrong [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 30340d48fc55SNeil Armstrong [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 30350d48fc55SNeil Armstrong [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 30360d48fc55SNeil Armstrong [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 30370d48fc55SNeil Armstrong [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 30380d48fc55SNeil Armstrong [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 30390d48fc55SNeil Armstrong [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 30400d48fc55SNeil Armstrong [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 30410d48fc55SNeil Armstrong [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 30420d48fc55SNeil Armstrong [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 30430d48fc55SNeil Armstrong [CLKID_MALI_0] = &gxbb_mali_0.hw, 30440d48fc55SNeil Armstrong [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 30450d48fc55SNeil Armstrong [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 30460d48fc55SNeil Armstrong [CLKID_MALI_1] = &gxbb_mali_1.hw, 30470d48fc55SNeil Armstrong [CLKID_MALI] = &gxbb_mali.hw, 30484087bd4bSJerome Brunet [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 30494087bd4bSJerome Brunet [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 30504087bd4bSJerome Brunet [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 30513c277c24SJerome Brunet [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 30523c277c24SJerome Brunet [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 30533c277c24SJerome Brunet [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 30547eaa44f6SJerome Brunet [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 305514c735c8SNeil Armstrong [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 305614c735c8SNeil Armstrong [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 305714c735c8SNeil Armstrong [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 3058914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 3059914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 3060914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 3061914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 3062914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 3063914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 3064914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 3065914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 3066914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 3067762a1f20SNeil Armstrong [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 3068762a1f20SNeil Armstrong [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 3069762a1f20SNeil Armstrong [CLKID_VPU_0] = &gxbb_vpu_0.hw, 3070762a1f20SNeil Armstrong [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 3071762a1f20SNeil Armstrong [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 3072762a1f20SNeil Armstrong [CLKID_VPU_1] = &gxbb_vpu_1.hw, 3073762a1f20SNeil Armstrong [CLKID_VPU] = &gxbb_vpu.hw, 3074762a1f20SNeil Armstrong [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 3075762a1f20SNeil Armstrong [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 3076762a1f20SNeil Armstrong [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 3077762a1f20SNeil Armstrong [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 3078762a1f20SNeil Armstrong [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 3079762a1f20SNeil Armstrong [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 3080762a1f20SNeil Armstrong [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 3081762a1f20SNeil Armstrong [CLKID_VAPB] = &gxbb_vapb.hw, 3082ff54938dSMartin Blumenstingl [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw, 3083d610b54fSJerome Brunet [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 3084d610b54fSJerome Brunet [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 3085513b67acSJerome Brunet [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 308605f81440SJerome Brunet [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 308705f81440SJerome Brunet [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 308805f81440SJerome Brunet [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 308905f81440SJerome Brunet [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 309005f81440SJerome Brunet [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 3091a565242eSMaxime Jourdan [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 3092a565242eSMaxime Jourdan [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 3093a565242eSMaxime Jourdan [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 3094a565242eSMaxime Jourdan [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 3095a565242eSMaxime Jourdan [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 3096a565242eSMaxime Jourdan [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 30977df533a7SJerome Brunet [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 30987df533a7SJerome Brunet [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 30997df533a7SJerome Brunet [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 310087173557SJerome Brunet [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw, 31010058502fSNeil Armstrong [CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw, 310287173557SJerome Brunet [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw, 310387173557SJerome Brunet [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw, 310487173557SJerome Brunet [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw, 310587173557SJerome Brunet [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw, 3106a8080f24SNeil Armstrong [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw, 3107a8080f24SNeil Armstrong [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw, 3108a8080f24SNeil Armstrong [CLKID_VID_PLL] = &gxbb_vid_pll.hw, 3109a8080f24SNeil Armstrong [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw, 3110a8080f24SNeil Armstrong [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw, 3111a8080f24SNeil Armstrong [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw, 3112a8080f24SNeil Armstrong [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw, 3113a8080f24SNeil Armstrong [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw, 3114a8080f24SNeil Armstrong [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw, 3115a8080f24SNeil Armstrong [CLKID_VCLK] = &gxbb_vclk.hw, 3116a8080f24SNeil Armstrong [CLKID_VCLK2] = &gxbb_vclk2.hw, 3117a8080f24SNeil Armstrong [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw, 3118a8080f24SNeil Armstrong [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw, 3119a8080f24SNeil Armstrong [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw, 3120a8080f24SNeil Armstrong [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw, 3121a8080f24SNeil Armstrong [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw, 3122a8080f24SNeil Armstrong [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw, 3123a8080f24SNeil Armstrong [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw, 3124a8080f24SNeil Armstrong [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw, 3125a8080f24SNeil Armstrong [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw, 3126a8080f24SNeil Armstrong [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw, 3127a8080f24SNeil Armstrong [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw, 3128a8080f24SNeil Armstrong [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw, 3129a8080f24SNeil Armstrong [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw, 3130a8080f24SNeil Armstrong [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw, 3131a8080f24SNeil Armstrong [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw, 3132a8080f24SNeil Armstrong [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw, 3133a8080f24SNeil Armstrong [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw, 3134a8080f24SNeil Armstrong [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw, 3135a8080f24SNeil Armstrong [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw, 3136a8080f24SNeil Armstrong [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw, 3137a8080f24SNeil Armstrong [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw, 3138a8080f24SNeil Armstrong [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw, 3139a8080f24SNeil Armstrong [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw, 3140a8080f24SNeil Armstrong [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw, 3141a8080f24SNeil Armstrong [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw, 3142a8080f24SNeil Armstrong [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw, 3143a8080f24SNeil Armstrong [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw, 3144a8080f24SNeil Armstrong [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw, 3145a8080f24SNeil Armstrong [CLKID_HDMI] = &gxbb_hdmi.hw, 314673c7ddd8SJerome Brunet [CLKID_ACODEC] = &gxl_acodec.hw, 31470d48fc55SNeil Armstrong }; 31480d48fc55SNeil Armstrong 3149722825dcSJerome Brunet static struct clk_regmap *const gxbb_clk_regmaps[] = { 3150738f66d3SMichael Turquette &gxbb_clk81, 3151738f66d3SMichael Turquette &gxbb_ddr, 3152738f66d3SMichael Turquette &gxbb_dos, 3153738f66d3SMichael Turquette &gxbb_isa, 3154738f66d3SMichael Turquette &gxbb_pl301, 3155738f66d3SMichael Turquette &gxbb_periphs, 3156738f66d3SMichael Turquette &gxbb_spicc, 3157738f66d3SMichael Turquette &gxbb_i2c, 3158738f66d3SMichael Turquette &gxbb_sar_adc, 3159738f66d3SMichael Turquette &gxbb_smart_card, 3160738f66d3SMichael Turquette &gxbb_rng0, 3161738f66d3SMichael Turquette &gxbb_uart0, 3162738f66d3SMichael Turquette &gxbb_sdhc, 3163738f66d3SMichael Turquette &gxbb_stream, 3164738f66d3SMichael Turquette &gxbb_async_fifo, 3165738f66d3SMichael Turquette &gxbb_sdio, 3166738f66d3SMichael Turquette &gxbb_abuf, 3167738f66d3SMichael Turquette &gxbb_hiu_iface, 3168738f66d3SMichael Turquette &gxbb_assist_misc, 3169738f66d3SMichael Turquette &gxbb_spi, 3170738f66d3SMichael Turquette &gxbb_i2s_spdif, 3171738f66d3SMichael Turquette &gxbb_eth, 3172738f66d3SMichael Turquette &gxbb_demux, 3173738f66d3SMichael Turquette &gxbb_aiu_glue, 3174738f66d3SMichael Turquette &gxbb_iec958, 3175738f66d3SMichael Turquette &gxbb_i2s_out, 3176738f66d3SMichael Turquette &gxbb_amclk, 3177738f66d3SMichael Turquette &gxbb_aififo2, 3178738f66d3SMichael Turquette &gxbb_mixer, 3179738f66d3SMichael Turquette &gxbb_mixer_iface, 3180738f66d3SMichael Turquette &gxbb_adc, 3181738f66d3SMichael Turquette &gxbb_blkmv, 3182738f66d3SMichael Turquette &gxbb_aiu, 3183738f66d3SMichael Turquette &gxbb_uart1, 3184738f66d3SMichael Turquette &gxbb_g2d, 3185738f66d3SMichael Turquette &gxbb_usb0, 3186738f66d3SMichael Turquette &gxbb_usb1, 3187738f66d3SMichael Turquette &gxbb_reset, 3188738f66d3SMichael Turquette &gxbb_nand, 3189738f66d3SMichael Turquette &gxbb_dos_parser, 3190738f66d3SMichael Turquette &gxbb_usb, 3191738f66d3SMichael Turquette &gxbb_vdin1, 3192738f66d3SMichael Turquette &gxbb_ahb_arb0, 3193738f66d3SMichael Turquette &gxbb_efuse, 3194738f66d3SMichael Turquette &gxbb_boot_rom, 3195738f66d3SMichael Turquette &gxbb_ahb_data_bus, 3196738f66d3SMichael Turquette &gxbb_ahb_ctrl_bus, 3197738f66d3SMichael Turquette &gxbb_hdmi_intr_sync, 3198738f66d3SMichael Turquette &gxbb_hdmi_pclk, 3199738f66d3SMichael Turquette &gxbb_usb1_ddr_bridge, 3200738f66d3SMichael Turquette &gxbb_usb0_ddr_bridge, 3201738f66d3SMichael Turquette &gxbb_mmc_pclk, 3202738f66d3SMichael Turquette &gxbb_dvin, 3203738f66d3SMichael Turquette &gxbb_uart2, 3204738f66d3SMichael Turquette &gxbb_sana, 3205738f66d3SMichael Turquette &gxbb_vpu_intr, 3206738f66d3SMichael Turquette &gxbb_sec_ahb_ahb3_bridge, 3207738f66d3SMichael Turquette &gxbb_clk81_a53, 3208738f66d3SMichael Turquette &gxbb_vclk2_venci0, 3209738f66d3SMichael Turquette &gxbb_vclk2_venci1, 3210738f66d3SMichael Turquette &gxbb_vclk2_vencp0, 3211738f66d3SMichael Turquette &gxbb_vclk2_vencp1, 3212738f66d3SMichael Turquette &gxbb_gclk_venci_int0, 3213738f66d3SMichael Turquette &gxbb_gclk_vencp_int, 3214738f66d3SMichael Turquette &gxbb_dac_clk, 3215738f66d3SMichael Turquette &gxbb_aoclk_gate, 3216738f66d3SMichael Turquette &gxbb_iec958_gate, 3217738f66d3SMichael Turquette &gxbb_enc480p, 3218738f66d3SMichael Turquette &gxbb_rng1, 3219738f66d3SMichael Turquette &gxbb_gclk_venci_int1, 3220738f66d3SMichael Turquette &gxbb_vclk2_venclmcc, 3221738f66d3SMichael Turquette &gxbb_vclk2_vencl, 3222738f66d3SMichael Turquette &gxbb_vclk_other, 3223738f66d3SMichael Turquette &gxbb_edp, 3224738f66d3SMichael Turquette &gxbb_ao_media_cpu, 3225738f66d3SMichael Turquette &gxbb_ao_ahb_sram, 3226738f66d3SMichael Turquette &gxbb_ao_ahb_bus, 3227738f66d3SMichael Turquette &gxbb_ao_iface, 3228738f66d3SMichael Turquette &gxbb_ao_i2c, 322933608dcdSKevin Hilman &gxbb_emmc_a, 323033608dcdSKevin Hilman &gxbb_emmc_b, 323133608dcdSKevin Hilman &gxbb_emmc_c, 323233d0fcdfSMartin Blumenstingl &gxbb_sar_adc_clk, 3233fac9a55bSNeil Armstrong &gxbb_mali_0, 3234fac9a55bSNeil Armstrong &gxbb_mali_1, 32354087bd4bSJerome Brunet &gxbb_cts_amclk, 32363c277c24SJerome Brunet &gxbb_cts_mclk_i958, 323714c735c8SNeil Armstrong &gxbb_32k_clk, 3238914e6e80SJerome Brunet &gxbb_sd_emmc_a_clk0, 3239914e6e80SJerome Brunet &gxbb_sd_emmc_b_clk0, 3240914e6e80SJerome Brunet &gxbb_sd_emmc_c_clk0, 3241762a1f20SNeil Armstrong &gxbb_vpu_0, 3242762a1f20SNeil Armstrong &gxbb_vpu_1, 3243762a1f20SNeil Armstrong &gxbb_vapb_0, 3244762a1f20SNeil Armstrong &gxbb_vapb_1, 3245762a1f20SNeil Armstrong &gxbb_vapb, 3246f06ddd28SJerome Brunet &gxbb_mpeg_clk_div, 3247f06ddd28SJerome Brunet &gxbb_sar_adc_clk_div, 3248f06ddd28SJerome Brunet &gxbb_mali_0_div, 3249f06ddd28SJerome Brunet &gxbb_mali_1_div, 3250f06ddd28SJerome Brunet &gxbb_cts_mclk_i958_div, 3251f06ddd28SJerome Brunet &gxbb_32k_clk_div, 3252f06ddd28SJerome Brunet &gxbb_sd_emmc_a_clk0_div, 3253f06ddd28SJerome Brunet &gxbb_sd_emmc_b_clk0_div, 3254f06ddd28SJerome Brunet &gxbb_sd_emmc_c_clk0_div, 3255f06ddd28SJerome Brunet &gxbb_vpu_0_div, 3256f06ddd28SJerome Brunet &gxbb_vpu_1_div, 3257f06ddd28SJerome Brunet &gxbb_vapb_0_div, 3258f06ddd28SJerome Brunet &gxbb_vapb_1_div, 32592513a28cSJerome Brunet &gxbb_mpeg_clk_sel, 32602513a28cSJerome Brunet &gxbb_sar_adc_clk_sel, 32612513a28cSJerome Brunet &gxbb_mali_0_sel, 32622513a28cSJerome Brunet &gxbb_mali_1_sel, 32632513a28cSJerome Brunet &gxbb_mali, 32642513a28cSJerome Brunet &gxbb_cts_amclk_sel, 32652513a28cSJerome Brunet &gxbb_cts_mclk_i958_sel, 32662513a28cSJerome Brunet &gxbb_cts_i958, 32672513a28cSJerome Brunet &gxbb_32k_clk_sel, 32682513a28cSJerome Brunet &gxbb_sd_emmc_a_clk0_sel, 32692513a28cSJerome Brunet &gxbb_sd_emmc_b_clk0_sel, 32702513a28cSJerome Brunet &gxbb_sd_emmc_c_clk0_sel, 32712513a28cSJerome Brunet &gxbb_vpu_0_sel, 32722513a28cSJerome Brunet &gxbb_vpu_1_sel, 32732513a28cSJerome Brunet &gxbb_vpu, 32742513a28cSJerome Brunet &gxbb_vapb_0_sel, 32752513a28cSJerome Brunet &gxbb_vapb_1_sel, 32762513a28cSJerome Brunet &gxbb_vapb_sel, 3277c763e61aSJerome Brunet &gxbb_mpll0, 3278c763e61aSJerome Brunet &gxbb_mpll1, 3279c763e61aSJerome Brunet &gxbb_mpll2, 3280d610b54fSJerome Brunet &gxbb_mpll0_div, 3281d610b54fSJerome Brunet &gxbb_mpll1_div, 3282d610b54fSJerome Brunet &gxbb_mpll2_div, 328388a4e128SJerome Brunet &gxbb_cts_amclk_div, 3284722825dcSJerome Brunet &gxbb_fixed_pll, 3285722825dcSJerome Brunet &gxbb_sys_pll, 3286513b67acSJerome Brunet &gxbb_mpll_prediv, 328705f81440SJerome Brunet &gxbb_fclk_div2, 328805f81440SJerome Brunet &gxbb_fclk_div3, 328905f81440SJerome Brunet &gxbb_fclk_div4, 329005f81440SJerome Brunet &gxbb_fclk_div5, 329105f81440SJerome Brunet &gxbb_fclk_div7, 3292a565242eSMaxime Jourdan &gxbb_vdec_1_sel, 3293a565242eSMaxime Jourdan &gxbb_vdec_1_div, 3294a565242eSMaxime Jourdan &gxbb_vdec_1, 3295a565242eSMaxime Jourdan &gxbb_vdec_hevc_sel, 3296a565242eSMaxime Jourdan &gxbb_vdec_hevc_div, 3297a565242eSMaxime Jourdan &gxbb_vdec_hevc, 32987df533a7SJerome Brunet &gxbb_gen_clk_sel, 32997df533a7SJerome Brunet &gxbb_gen_clk_div, 33007df533a7SJerome Brunet &gxbb_gen_clk, 330187173557SJerome Brunet &gxbb_fixed_pll_dco, 330287173557SJerome Brunet &gxbb_sys_pll_dco, 330387173557SJerome Brunet &gxbb_gp0_pll, 3304a8080f24SNeil Armstrong &gxbb_vid_pll, 3305a8080f24SNeil Armstrong &gxbb_vid_pll_sel, 3306a8080f24SNeil Armstrong &gxbb_vid_pll_div, 3307a8080f24SNeil Armstrong &gxbb_vclk, 3308a8080f24SNeil Armstrong &gxbb_vclk_sel, 3309a8080f24SNeil Armstrong &gxbb_vclk_div, 3310a8080f24SNeil Armstrong &gxbb_vclk_input, 3311a8080f24SNeil Armstrong &gxbb_vclk_div1, 3312a8080f24SNeil Armstrong &gxbb_vclk_div2_en, 3313a8080f24SNeil Armstrong &gxbb_vclk_div4_en, 3314a8080f24SNeil Armstrong &gxbb_vclk_div6_en, 3315a8080f24SNeil Armstrong &gxbb_vclk_div12_en, 3316a8080f24SNeil Armstrong &gxbb_vclk2, 3317a8080f24SNeil Armstrong &gxbb_vclk2_sel, 3318a8080f24SNeil Armstrong &gxbb_vclk2_div, 3319a8080f24SNeil Armstrong &gxbb_vclk2_input, 3320a8080f24SNeil Armstrong &gxbb_vclk2_div1, 3321a8080f24SNeil Armstrong &gxbb_vclk2_div2_en, 3322a8080f24SNeil Armstrong &gxbb_vclk2_div4_en, 3323a8080f24SNeil Armstrong &gxbb_vclk2_div6_en, 3324a8080f24SNeil Armstrong &gxbb_vclk2_div12_en, 3325a8080f24SNeil Armstrong &gxbb_cts_enci, 3326a8080f24SNeil Armstrong &gxbb_cts_enci_sel, 3327a8080f24SNeil Armstrong &gxbb_cts_encp, 3328a8080f24SNeil Armstrong &gxbb_cts_encp_sel, 3329a8080f24SNeil Armstrong &gxbb_cts_vdac, 3330a8080f24SNeil Armstrong &gxbb_cts_vdac_sel, 3331a8080f24SNeil Armstrong &gxbb_hdmi_tx, 3332a8080f24SNeil Armstrong &gxbb_hdmi_tx_sel, 3333a8080f24SNeil Armstrong &gxbb_hdmi_sel, 3334a8080f24SNeil Armstrong &gxbb_hdmi_div, 3335a8080f24SNeil Armstrong &gxbb_hdmi, 33366682bd4dSJerome Brunet &gxbb_gp0_pll_dco, 33376682bd4dSJerome Brunet &gxbb_hdmi_pll, 33386682bd4dSJerome Brunet &gxbb_hdmi_pll_od, 33396682bd4dSJerome Brunet &gxbb_hdmi_pll_od2, 33406682bd4dSJerome Brunet &gxbb_hdmi_pll_dco, 3341738f66d3SMichael Turquette }; 3342738f66d3SMichael Turquette 33436682bd4dSJerome Brunet static struct clk_regmap *const gxl_clk_regmaps[] = { 33446682bd4dSJerome Brunet &gxbb_clk81, 33456682bd4dSJerome Brunet &gxbb_ddr, 33466682bd4dSJerome Brunet &gxbb_dos, 33476682bd4dSJerome Brunet &gxbb_isa, 33486682bd4dSJerome Brunet &gxbb_pl301, 33496682bd4dSJerome Brunet &gxbb_periphs, 33506682bd4dSJerome Brunet &gxbb_spicc, 33516682bd4dSJerome Brunet &gxbb_i2c, 33526682bd4dSJerome Brunet &gxbb_sar_adc, 33536682bd4dSJerome Brunet &gxbb_smart_card, 33546682bd4dSJerome Brunet &gxbb_rng0, 33556682bd4dSJerome Brunet &gxbb_uart0, 33566682bd4dSJerome Brunet &gxbb_sdhc, 33576682bd4dSJerome Brunet &gxbb_stream, 33586682bd4dSJerome Brunet &gxbb_async_fifo, 33596682bd4dSJerome Brunet &gxbb_sdio, 33606682bd4dSJerome Brunet &gxbb_abuf, 33616682bd4dSJerome Brunet &gxbb_hiu_iface, 33626682bd4dSJerome Brunet &gxbb_assist_misc, 33636682bd4dSJerome Brunet &gxbb_spi, 33646682bd4dSJerome Brunet &gxbb_i2s_spdif, 33656682bd4dSJerome Brunet &gxbb_eth, 33666682bd4dSJerome Brunet &gxbb_demux, 33676682bd4dSJerome Brunet &gxbb_aiu_glue, 33686682bd4dSJerome Brunet &gxbb_iec958, 33696682bd4dSJerome Brunet &gxbb_i2s_out, 33706682bd4dSJerome Brunet &gxbb_amclk, 33716682bd4dSJerome Brunet &gxbb_aififo2, 33726682bd4dSJerome Brunet &gxbb_mixer, 33736682bd4dSJerome Brunet &gxbb_mixer_iface, 33746682bd4dSJerome Brunet &gxbb_adc, 33756682bd4dSJerome Brunet &gxbb_blkmv, 33766682bd4dSJerome Brunet &gxbb_aiu, 33776682bd4dSJerome Brunet &gxbb_uart1, 33786682bd4dSJerome Brunet &gxbb_g2d, 33796682bd4dSJerome Brunet &gxbb_usb0, 33806682bd4dSJerome Brunet &gxbb_usb1, 33816682bd4dSJerome Brunet &gxbb_reset, 33826682bd4dSJerome Brunet &gxbb_nand, 33836682bd4dSJerome Brunet &gxbb_dos_parser, 33846682bd4dSJerome Brunet &gxbb_usb, 33856682bd4dSJerome Brunet &gxbb_vdin1, 33866682bd4dSJerome Brunet &gxbb_ahb_arb0, 33876682bd4dSJerome Brunet &gxbb_efuse, 33886682bd4dSJerome Brunet &gxbb_boot_rom, 33896682bd4dSJerome Brunet &gxbb_ahb_data_bus, 33906682bd4dSJerome Brunet &gxbb_ahb_ctrl_bus, 33916682bd4dSJerome Brunet &gxbb_hdmi_intr_sync, 33926682bd4dSJerome Brunet &gxbb_hdmi_pclk, 33936682bd4dSJerome Brunet &gxbb_usb1_ddr_bridge, 33946682bd4dSJerome Brunet &gxbb_usb0_ddr_bridge, 33956682bd4dSJerome Brunet &gxbb_mmc_pclk, 33966682bd4dSJerome Brunet &gxbb_dvin, 33976682bd4dSJerome Brunet &gxbb_uart2, 33986682bd4dSJerome Brunet &gxbb_sana, 33996682bd4dSJerome Brunet &gxbb_vpu_intr, 34006682bd4dSJerome Brunet &gxbb_sec_ahb_ahb3_bridge, 34016682bd4dSJerome Brunet &gxbb_clk81_a53, 34026682bd4dSJerome Brunet &gxbb_vclk2_venci0, 34036682bd4dSJerome Brunet &gxbb_vclk2_venci1, 34046682bd4dSJerome Brunet &gxbb_vclk2_vencp0, 34056682bd4dSJerome Brunet &gxbb_vclk2_vencp1, 34066682bd4dSJerome Brunet &gxbb_gclk_venci_int0, 34076682bd4dSJerome Brunet &gxbb_gclk_vencp_int, 34086682bd4dSJerome Brunet &gxbb_dac_clk, 34096682bd4dSJerome Brunet &gxbb_aoclk_gate, 34106682bd4dSJerome Brunet &gxbb_iec958_gate, 34116682bd4dSJerome Brunet &gxbb_enc480p, 34126682bd4dSJerome Brunet &gxbb_rng1, 34136682bd4dSJerome Brunet &gxbb_gclk_venci_int1, 34146682bd4dSJerome Brunet &gxbb_vclk2_venclmcc, 34156682bd4dSJerome Brunet &gxbb_vclk2_vencl, 34166682bd4dSJerome Brunet &gxbb_vclk_other, 34176682bd4dSJerome Brunet &gxbb_edp, 34186682bd4dSJerome Brunet &gxbb_ao_media_cpu, 34196682bd4dSJerome Brunet &gxbb_ao_ahb_sram, 34206682bd4dSJerome Brunet &gxbb_ao_ahb_bus, 34216682bd4dSJerome Brunet &gxbb_ao_iface, 34226682bd4dSJerome Brunet &gxbb_ao_i2c, 34236682bd4dSJerome Brunet &gxbb_emmc_a, 34246682bd4dSJerome Brunet &gxbb_emmc_b, 34256682bd4dSJerome Brunet &gxbb_emmc_c, 34266682bd4dSJerome Brunet &gxbb_sar_adc_clk, 34276682bd4dSJerome Brunet &gxbb_mali_0, 34286682bd4dSJerome Brunet &gxbb_mali_1, 34296682bd4dSJerome Brunet &gxbb_cts_amclk, 34306682bd4dSJerome Brunet &gxbb_cts_mclk_i958, 34316682bd4dSJerome Brunet &gxbb_32k_clk, 34326682bd4dSJerome Brunet &gxbb_sd_emmc_a_clk0, 34336682bd4dSJerome Brunet &gxbb_sd_emmc_b_clk0, 34346682bd4dSJerome Brunet &gxbb_sd_emmc_c_clk0, 34356682bd4dSJerome Brunet &gxbb_vpu_0, 34366682bd4dSJerome Brunet &gxbb_vpu_1, 34376682bd4dSJerome Brunet &gxbb_vapb_0, 34386682bd4dSJerome Brunet &gxbb_vapb_1, 34396682bd4dSJerome Brunet &gxbb_vapb, 34406682bd4dSJerome Brunet &gxbb_mpeg_clk_div, 34416682bd4dSJerome Brunet &gxbb_sar_adc_clk_div, 34426682bd4dSJerome Brunet &gxbb_mali_0_div, 34436682bd4dSJerome Brunet &gxbb_mali_1_div, 34446682bd4dSJerome Brunet &gxbb_cts_mclk_i958_div, 34456682bd4dSJerome Brunet &gxbb_32k_clk_div, 34466682bd4dSJerome Brunet &gxbb_sd_emmc_a_clk0_div, 34476682bd4dSJerome Brunet &gxbb_sd_emmc_b_clk0_div, 34486682bd4dSJerome Brunet &gxbb_sd_emmc_c_clk0_div, 34496682bd4dSJerome Brunet &gxbb_vpu_0_div, 34506682bd4dSJerome Brunet &gxbb_vpu_1_div, 34516682bd4dSJerome Brunet &gxbb_vapb_0_div, 34526682bd4dSJerome Brunet &gxbb_vapb_1_div, 34536682bd4dSJerome Brunet &gxbb_mpeg_clk_sel, 34546682bd4dSJerome Brunet &gxbb_sar_adc_clk_sel, 34556682bd4dSJerome Brunet &gxbb_mali_0_sel, 34566682bd4dSJerome Brunet &gxbb_mali_1_sel, 34576682bd4dSJerome Brunet &gxbb_mali, 34586682bd4dSJerome Brunet &gxbb_cts_amclk_sel, 34596682bd4dSJerome Brunet &gxbb_cts_mclk_i958_sel, 34606682bd4dSJerome Brunet &gxbb_cts_i958, 34616682bd4dSJerome Brunet &gxbb_32k_clk_sel, 34626682bd4dSJerome Brunet &gxbb_sd_emmc_a_clk0_sel, 34636682bd4dSJerome Brunet &gxbb_sd_emmc_b_clk0_sel, 34646682bd4dSJerome Brunet &gxbb_sd_emmc_c_clk0_sel, 34656682bd4dSJerome Brunet &gxbb_vpu_0_sel, 34666682bd4dSJerome Brunet &gxbb_vpu_1_sel, 34676682bd4dSJerome Brunet &gxbb_vpu, 34686682bd4dSJerome Brunet &gxbb_vapb_0_sel, 34696682bd4dSJerome Brunet &gxbb_vapb_1_sel, 34706682bd4dSJerome Brunet &gxbb_vapb_sel, 34716682bd4dSJerome Brunet &gxbb_mpll0, 34726682bd4dSJerome Brunet &gxbb_mpll1, 34736682bd4dSJerome Brunet &gxbb_mpll2, 3474ff54938dSMartin Blumenstingl &gxl_mpll0_div, 34756682bd4dSJerome Brunet &gxbb_mpll1_div, 34766682bd4dSJerome Brunet &gxbb_mpll2_div, 34776682bd4dSJerome Brunet &gxbb_cts_amclk_div, 34786682bd4dSJerome Brunet &gxbb_fixed_pll, 34796682bd4dSJerome Brunet &gxbb_sys_pll, 34806682bd4dSJerome Brunet &gxbb_mpll_prediv, 34816682bd4dSJerome Brunet &gxbb_fclk_div2, 34826682bd4dSJerome Brunet &gxbb_fclk_div3, 34836682bd4dSJerome Brunet &gxbb_fclk_div4, 34846682bd4dSJerome Brunet &gxbb_fclk_div5, 34856682bd4dSJerome Brunet &gxbb_fclk_div7, 34866682bd4dSJerome Brunet &gxbb_vdec_1_sel, 34876682bd4dSJerome Brunet &gxbb_vdec_1_div, 34886682bd4dSJerome Brunet &gxbb_vdec_1, 34896682bd4dSJerome Brunet &gxbb_vdec_hevc_sel, 34906682bd4dSJerome Brunet &gxbb_vdec_hevc_div, 34916682bd4dSJerome Brunet &gxbb_vdec_hevc, 34926682bd4dSJerome Brunet &gxbb_gen_clk_sel, 34936682bd4dSJerome Brunet &gxbb_gen_clk_div, 34946682bd4dSJerome Brunet &gxbb_gen_clk, 34956682bd4dSJerome Brunet &gxbb_fixed_pll_dco, 34966682bd4dSJerome Brunet &gxbb_sys_pll_dco, 34976682bd4dSJerome Brunet &gxbb_gp0_pll, 34986682bd4dSJerome Brunet &gxbb_vid_pll, 34996682bd4dSJerome Brunet &gxbb_vid_pll_sel, 35006682bd4dSJerome Brunet &gxbb_vid_pll_div, 35016682bd4dSJerome Brunet &gxbb_vclk, 35026682bd4dSJerome Brunet &gxbb_vclk_sel, 35036682bd4dSJerome Brunet &gxbb_vclk_div, 35046682bd4dSJerome Brunet &gxbb_vclk_input, 35056682bd4dSJerome Brunet &gxbb_vclk_div1, 35066682bd4dSJerome Brunet &gxbb_vclk_div2_en, 35076682bd4dSJerome Brunet &gxbb_vclk_div4_en, 35086682bd4dSJerome Brunet &gxbb_vclk_div6_en, 35096682bd4dSJerome Brunet &gxbb_vclk_div12_en, 35106682bd4dSJerome Brunet &gxbb_vclk2, 35116682bd4dSJerome Brunet &gxbb_vclk2_sel, 35126682bd4dSJerome Brunet &gxbb_vclk2_div, 35136682bd4dSJerome Brunet &gxbb_vclk2_input, 35146682bd4dSJerome Brunet &gxbb_vclk2_div1, 35156682bd4dSJerome Brunet &gxbb_vclk2_div2_en, 35166682bd4dSJerome Brunet &gxbb_vclk2_div4_en, 35176682bd4dSJerome Brunet &gxbb_vclk2_div6_en, 35186682bd4dSJerome Brunet &gxbb_vclk2_div12_en, 35196682bd4dSJerome Brunet &gxbb_cts_enci, 35206682bd4dSJerome Brunet &gxbb_cts_enci_sel, 35216682bd4dSJerome Brunet &gxbb_cts_encp, 35226682bd4dSJerome Brunet &gxbb_cts_encp_sel, 35236682bd4dSJerome Brunet &gxbb_cts_vdac, 35246682bd4dSJerome Brunet &gxbb_cts_vdac_sel, 35256682bd4dSJerome Brunet &gxbb_hdmi_tx, 35266682bd4dSJerome Brunet &gxbb_hdmi_tx_sel, 35276682bd4dSJerome Brunet &gxbb_hdmi_sel, 35286682bd4dSJerome Brunet &gxbb_hdmi_div, 35296682bd4dSJerome Brunet &gxbb_hdmi, 35306682bd4dSJerome Brunet &gxl_gp0_pll_dco, 35316682bd4dSJerome Brunet &gxl_hdmi_pll, 35326682bd4dSJerome Brunet &gxl_hdmi_pll_od, 35336682bd4dSJerome Brunet &gxl_hdmi_pll_od2, 35346682bd4dSJerome Brunet &gxl_hdmi_pll_dco, 353573c7ddd8SJerome Brunet &gxl_acodec, 35360d48fc55SNeil Armstrong }; 35370d48fc55SNeil Armstrong 35386682bd4dSJerome Brunet static const struct meson_eeclkc_data gxbb_clkc_data = { 3539722825dcSJerome Brunet .regmap_clks = gxbb_clk_regmaps, 35406682bd4dSJerome Brunet .regmap_clk_num = ARRAY_SIZE(gxbb_clk_regmaps), 3541141fbc27SNeil Armstrong .hw_clks = { 3542141fbc27SNeil Armstrong .hws = gxbb_hw_clks, 3543141fbc27SNeil Armstrong .num = ARRAY_SIZE(gxbb_hw_clks), 3544141fbc27SNeil Armstrong }, 35450d48fc55SNeil Armstrong }; 35460d48fc55SNeil Armstrong 35476682bd4dSJerome Brunet static const struct meson_eeclkc_data gxl_clkc_data = { 3548722825dcSJerome Brunet .regmap_clks = gxl_clk_regmaps, 35496682bd4dSJerome Brunet .regmap_clk_num = ARRAY_SIZE(gxl_clk_regmaps), 3550141fbc27SNeil Armstrong .hw_clks = { 3551141fbc27SNeil Armstrong .hws = gxl_hw_clks, 3552141fbc27SNeil Armstrong .num = ARRAY_SIZE(gxl_hw_clks), 3553141fbc27SNeil Armstrong }, 35540d48fc55SNeil Armstrong }; 35550d48fc55SNeil Armstrong 35560d48fc55SNeil Armstrong static const struct of_device_id clkc_match_table[] = { 35570d48fc55SNeil Armstrong { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data }, 35580d48fc55SNeil Armstrong { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data }, 35590d48fc55SNeil Armstrong {}, 35600d48fc55SNeil Armstrong }; 356120425f63SKevin Hilman MODULE_DEVICE_TABLE(of, clkc_match_table); 35620d48fc55SNeil Armstrong 3563738f66d3SMichael Turquette static struct platform_driver gxbb_driver = { 35646682bd4dSJerome Brunet .probe = meson_eeclkc_probe, 3565738f66d3SMichael Turquette .driver = { 3566738f66d3SMichael Turquette .name = "gxbb-clkc", 35670d48fc55SNeil Armstrong .of_match_table = clkc_match_table, 3568738f66d3SMichael Turquette }, 3569738f66d3SMichael Turquette }; 3570738f66d3SMichael Turquette 357120425f63SKevin Hilman module_platform_driver(gxbb_driver); 357220425f63SKevin Hilman MODULE_LICENSE("GPL v2"); 3573