17e5c90e0SQiufang Dai /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 27e5c90e0SQiufang Dai /* 37e5c90e0SQiufang Dai * Meson-AXG clock tree IDs 47e5c90e0SQiufang Dai * 57e5c90e0SQiufang Dai * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 67e5c90e0SQiufang Dai */ 77e5c90e0SQiufang Dai 87e5c90e0SQiufang Dai #ifndef __AXG_CLKC_H 97e5c90e0SQiufang Dai #define __AXG_CLKC_H 107e5c90e0SQiufang Dai 117e5c90e0SQiufang Dai #define CLKID_SYS_PLL 0 127e5c90e0SQiufang Dai #define CLKID_FIXED_PLL 1 137e5c90e0SQiufang Dai #define CLKID_FCLK_DIV2 2 147e5c90e0SQiufang Dai #define CLKID_FCLK_DIV3 3 157e5c90e0SQiufang Dai #define CLKID_FCLK_DIV4 4 167e5c90e0SQiufang Dai #define CLKID_FCLK_DIV5 5 177e5c90e0SQiufang Dai #define CLKID_FCLK_DIV7 6 187e5c90e0SQiufang Dai #define CLKID_GP0_PLL 7 19*8fdbdc79SNeil Armstrong #define CLKID_MPEG_SEL 8 20*8fdbdc79SNeil Armstrong #define CLKID_MPEG_DIV 9 217e5c90e0SQiufang Dai #define CLKID_CLK81 10 227e5c90e0SQiufang Dai #define CLKID_MPLL0 11 237e5c90e0SQiufang Dai #define CLKID_MPLL1 12 247e5c90e0SQiufang Dai #define CLKID_MPLL2 13 257e5c90e0SQiufang Dai #define CLKID_MPLL3 14 267e5c90e0SQiufang Dai #define CLKID_DDR 15 277e5c90e0SQiufang Dai #define CLKID_AUDIO_LOCKER 16 287e5c90e0SQiufang Dai #define CLKID_MIPI_DSI_HOST 17 297e5c90e0SQiufang Dai #define CLKID_ISA 18 307e5c90e0SQiufang Dai #define CLKID_PL301 19 317e5c90e0SQiufang Dai #define CLKID_PERIPHS 20 327e5c90e0SQiufang Dai #define CLKID_SPICC0 21 337e5c90e0SQiufang Dai #define CLKID_I2C 22 347e5c90e0SQiufang Dai #define CLKID_RNG0 23 357e5c90e0SQiufang Dai #define CLKID_UART0 24 367e5c90e0SQiufang Dai #define CLKID_MIPI_DSI_PHY 25 377e5c90e0SQiufang Dai #define CLKID_SPICC1 26 387e5c90e0SQiufang Dai #define CLKID_PCIE_A 27 397e5c90e0SQiufang Dai #define CLKID_PCIE_B 28 407e5c90e0SQiufang Dai #define CLKID_HIU_IFACE 29 417e5c90e0SQiufang Dai #define CLKID_ASSIST_MISC 30 427e5c90e0SQiufang Dai #define CLKID_SD_EMMC_B 31 437e5c90e0SQiufang Dai #define CLKID_SD_EMMC_C 32 447e5c90e0SQiufang Dai #define CLKID_DMA 33 457e5c90e0SQiufang Dai #define CLKID_SPI 34 467e5c90e0SQiufang Dai #define CLKID_AUDIO 35 477e5c90e0SQiufang Dai #define CLKID_ETH 36 487e5c90e0SQiufang Dai #define CLKID_UART1 37 497e5c90e0SQiufang Dai #define CLKID_G2D 38 507e5c90e0SQiufang Dai #define CLKID_USB0 39 517e5c90e0SQiufang Dai #define CLKID_USB1 40 527e5c90e0SQiufang Dai #define CLKID_RESET 41 537e5c90e0SQiufang Dai #define CLKID_USB 42 547e5c90e0SQiufang Dai #define CLKID_AHB_ARB0 43 557e5c90e0SQiufang Dai #define CLKID_EFUSE 44 567e5c90e0SQiufang Dai #define CLKID_BOOT_ROM 45 577e5c90e0SQiufang Dai #define CLKID_AHB_DATA_BUS 46 587e5c90e0SQiufang Dai #define CLKID_AHB_CTRL_BUS 47 597e5c90e0SQiufang Dai #define CLKID_USB1_DDR_BRIDGE 48 607e5c90e0SQiufang Dai #define CLKID_USB0_DDR_BRIDGE 49 617e5c90e0SQiufang Dai #define CLKID_MMC_PCLK 50 627e5c90e0SQiufang Dai #define CLKID_VPU_INTR 51 637e5c90e0SQiufang Dai #define CLKID_SEC_AHB_AHB3_BRIDGE 52 647e5c90e0SQiufang Dai #define CLKID_GIC 53 657e5c90e0SQiufang Dai #define CLKID_AO_MEDIA_CPU 54 667e5c90e0SQiufang Dai #define CLKID_AO_AHB_SRAM 55 677e5c90e0SQiufang Dai #define CLKID_AO_AHB_BUS 56 687e5c90e0SQiufang Dai #define CLKID_AO_IFACE 57 697e5c90e0SQiufang Dai #define CLKID_AO_I2C 58 707e5c90e0SQiufang Dai #define CLKID_SD_EMMC_B_CLK0 59 717e5c90e0SQiufang Dai #define CLKID_SD_EMMC_C_CLK0 60 72*8fdbdc79SNeil Armstrong #define CLKID_SD_EMMC_B_CLK0_SEL 61 73*8fdbdc79SNeil Armstrong #define CLKID_SD_EMMC_B_CLK0_DIV 62 74*8fdbdc79SNeil Armstrong #define CLKID_SD_EMMC_C_CLK0_SEL 63 75*8fdbdc79SNeil Armstrong #define CLKID_SD_EMMC_C_CLK0_DIV 64 76*8fdbdc79SNeil Armstrong #define CLKID_MPLL0_DIV 65 77*8fdbdc79SNeil Armstrong #define CLKID_MPLL1_DIV 66 78*8fdbdc79SNeil Armstrong #define CLKID_MPLL2_DIV 67 79*8fdbdc79SNeil Armstrong #define CLKID_MPLL3_DIV 68 80a4fb7df2SJerome Brunet #define CLKID_HIFI_PLL 69 81*8fdbdc79SNeil Armstrong #define CLKID_MPLL_PREDIV 70 82*8fdbdc79SNeil Armstrong #define CLKID_FCLK_DIV2_DIV 71 83*8fdbdc79SNeil Armstrong #define CLKID_FCLK_DIV3_DIV 72 84*8fdbdc79SNeil Armstrong #define CLKID_FCLK_DIV4_DIV 73 85*8fdbdc79SNeil Armstrong #define CLKID_FCLK_DIV5_DIV 74 86*8fdbdc79SNeil Armstrong #define CLKID_FCLK_DIV7_DIV 75 87*8fdbdc79SNeil Armstrong #define CLKID_PCIE_PLL 76 88*8fdbdc79SNeil Armstrong #define CLKID_PCIE_MUX 77 89*8fdbdc79SNeil Armstrong #define CLKID_PCIE_REF 78 906c0ad1dfSYixun Lan #define CLKID_PCIE_CML_EN0 79 916c0ad1dfSYixun Lan #define CLKID_PCIE_CML_EN1 80 92*8fdbdc79SNeil Armstrong #define CLKID_GEN_CLK_SEL 82 93*8fdbdc79SNeil Armstrong #define CLKID_GEN_CLK_DIV 83 94de3c1e71SJerome Brunet #define CLKID_GEN_CLK 84 95*8fdbdc79SNeil Armstrong #define CLKID_SYS_PLL_DCO 85 96*8fdbdc79SNeil Armstrong #define CLKID_FIXED_PLL_DCO 86 97*8fdbdc79SNeil Armstrong #define CLKID_GP0_PLL_DCO 87 98*8fdbdc79SNeil Armstrong #define CLKID_HIFI_PLL_DCO 88 99*8fdbdc79SNeil Armstrong #define CLKID_PCIE_PLL_DCO 89 100*8fdbdc79SNeil Armstrong #define CLKID_PCIE_PLL_OD 90 101*8fdbdc79SNeil Armstrong #define CLKID_VPU_0_DIV 91 102b5330c56SNeil Armstrong #define CLKID_VPU_0_SEL 92 103b5330c56SNeil Armstrong #define CLKID_VPU_0 93 104*8fdbdc79SNeil Armstrong #define CLKID_VPU_1_DIV 94 105b5330c56SNeil Armstrong #define CLKID_VPU_1_SEL 95 106b5330c56SNeil Armstrong #define CLKID_VPU_1 96 107b5330c56SNeil Armstrong #define CLKID_VPU 97 108*8fdbdc79SNeil Armstrong #define CLKID_VAPB_0_DIV 98 109b5330c56SNeil Armstrong #define CLKID_VAPB_0_SEL 99 110b5330c56SNeil Armstrong #define CLKID_VAPB_0 100 111*8fdbdc79SNeil Armstrong #define CLKID_VAPB_1_DIV 101 112b5330c56SNeil Armstrong #define CLKID_VAPB_1_SEL 102 113b5330c56SNeil Armstrong #define CLKID_VAPB_1 103 114b5330c56SNeil Armstrong #define CLKID_VAPB_SEL 104 115b5330c56SNeil Armstrong #define CLKID_VAPB 105 116b5330c56SNeil Armstrong #define CLKID_VCLK 106 117b5330c56SNeil Armstrong #define CLKID_VCLK2 107 118*8fdbdc79SNeil Armstrong #define CLKID_VCLK_SEL 108 119*8fdbdc79SNeil Armstrong #define CLKID_VCLK2_SEL 109 120*8fdbdc79SNeil Armstrong #define CLKID_VCLK_INPUT 110 121*8fdbdc79SNeil Armstrong #define CLKID_VCLK2_INPUT 111 122*8fdbdc79SNeil Armstrong #define CLKID_VCLK_DIV 112 123*8fdbdc79SNeil Armstrong #define CLKID_VCLK2_DIV 113 124*8fdbdc79SNeil Armstrong #define CLKID_VCLK_DIV2_EN 114 125*8fdbdc79SNeil Armstrong #define CLKID_VCLK_DIV4_EN 115 126*8fdbdc79SNeil Armstrong #define CLKID_VCLK_DIV6_EN 116 127*8fdbdc79SNeil Armstrong #define CLKID_VCLK_DIV12_EN 117 128*8fdbdc79SNeil Armstrong #define CLKID_VCLK2_DIV2_EN 118 129*8fdbdc79SNeil Armstrong #define CLKID_VCLK2_DIV4_EN 119 130*8fdbdc79SNeil Armstrong #define CLKID_VCLK2_DIV6_EN 120 131*8fdbdc79SNeil Armstrong #define CLKID_VCLK2_DIV12_EN 121 132b5330c56SNeil Armstrong #define CLKID_VCLK_DIV1 122 133b5330c56SNeil Armstrong #define CLKID_VCLK_DIV2 123 134b5330c56SNeil Armstrong #define CLKID_VCLK_DIV4 124 135b5330c56SNeil Armstrong #define CLKID_VCLK_DIV6 125 136b5330c56SNeil Armstrong #define CLKID_VCLK_DIV12 126 137b5330c56SNeil Armstrong #define CLKID_VCLK2_DIV1 127 138b5330c56SNeil Armstrong #define CLKID_VCLK2_DIV2 128 139b5330c56SNeil Armstrong #define CLKID_VCLK2_DIV4 129 140b5330c56SNeil Armstrong #define CLKID_VCLK2_DIV6 130 141b5330c56SNeil Armstrong #define CLKID_VCLK2_DIV12 131 142*8fdbdc79SNeil Armstrong #define CLKID_CTS_ENCL_SEL 132 143b5330c56SNeil Armstrong #define CLKID_CTS_ENCL 133 144*8fdbdc79SNeil Armstrong #define CLKID_VDIN_MEAS_SEL 134 145*8fdbdc79SNeil Armstrong #define CLKID_VDIN_MEAS_DIV 135 146cd3caa57SNeil Armstrong #define CLKID_VDIN_MEAS 136 1477e5c90e0SQiufang Dai 1487e5c90e0SQiufang Dai #endif /* __AXG_CLKC_H */ 149