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Searched refs:CLKID_DDR (Results 1 – 11 of 11) sorted by relevance

/openbmc/u-boot/include/dt-bindings/clock/
H A Daxg-clkc.h24 #define CLKID_DDR 15 macro
H A Dgxbb-clkc.h22 #define CLKID_DDR 16 macro
/openbmc/linux/include/dt-bindings/clock/
H A Daxg-clkc.h26 #define CLKID_DDR 15 macro
H A Dgxbb-clkc.h24 #define CLKID_DDR 16 macro
H A Dmeson8b-clkc.h23 #define CLKID_DDR 16 macro
H A Dg12a-clkc.h26 #define CLKID_DDR 15 macro
/openbmc/u-boot/drivers/clk/
H A Dclk_meson.c86 MESON_GATE(CLKID_DDR, HHI_GCLK_MPEG0, 0),
/openbmc/linux/drivers/clk/meson/
H A Dmeson8b.c2792 [CLKID_DDR] = &meson8b_ddr.hw,
2996 [CLKID_DDR] = &meson8b_ddr.hw,
3211 [CLKID_DDR] = &meson8b_ddr.hw,
H A Dgxbb.c2749 [CLKID_DDR] = &gxbb_ddr.hw,
2957 [CLKID_DDR] = &gxbb_ddr.hw,
H A Dg12a.c4266 [CLKID_DDR] = &g12a_ddr.hw,
4491 [CLKID_DDR] = &g12a_ddr.hw,
4751 [CLKID_DDR] = &g12a_ddr.hw,
H A Daxg.c1911 [CLKID_DDR] = &axg_ddr.hw,