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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-core/opencl/files/
H A D0001-Command-buffer-supported-queue-properties-265.patch12 CL/cl_ext.h | 4 ++--
15 diff --git a/CL/cl_ext.h b/CL/cl_ext.h
17 --- a/CL/cl_ext.h
18 +++ b/CL/cl_ext.h
/openbmc/openbmc/poky/scripts/
H A Dsend-pull-request105 CL="$PDIR/0000-cover-letter.patch"
107 grep -q "*** $TOKEN HERE ***" "$CL"
109 echo "ERROR: Please edit $CL and try again (Look for '*** $TOKEN HERE ***')."
157 …l "git send-email $GIT_TO $GIT_CC $GIT_EXTRA_CC --confirm=always --no-thread --suppress-cc=all $CL"
162 PATCHES=${PATCHES/"$CL"/}
H A Dcreate-pull-request205 CL="$(echo $ODIR/*0000-cover-letter.patch)"
222 sed -n "0,\#$REMOTE_URL# p" "$PM" | sed -i "/BLURB HERE/ r /dev/stdin" "$CL"
233 ) | sed -i "/BLURB HERE/ r /dev/stdin" "$CL"
238 echo " $WEB_URL" | sed -i "\#$REMOTE_URL# r /dev/stdin" "$CL"
245 sed -i "/BLURB HERE/ r $BODY" "$CL"
246 sed -i "/BLURB HERE/ d" "$CL"
257 sed -i -e "s\`\*\*\* SUBJECT HERE \*\*\*\`$SUBJECT\`" "$CL"
267 $CL
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c89 u32 CL; member
360 u32 CL = 0; in mctl_channel_init() local
437 CL = para->cl_cwl_table[i].CL; in mctl_channel_init()
440 debug("found CL/CWL: CL = %d, CWL = %d\n", CL, CWL); in mctl_channel_init()
445 if ((CL == 0) && (CWL == 0)) { in mctl_channel_init()
461 DDR3_MR0_CL(CL); in mctl_channel_init()
525 #define RD2WR (CL + MCTL_BL/2 + 2 - CWL) in mctl_channel_init()
539 writel((MCTL_DIV2(CWL) << 24) | (MCTL_DIV2(CL) << 16) | in mctl_channel_init()
573 writel((2 << 24) | ((MCTL_DIV2(CL) - 2) << 16) | in mctl_channel_init()
860 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
[all …]
/openbmc/u-boot/board/Seagate/nas220/
H A Dkwbimage.cfg26 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
41 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
42 # bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
90 # bit6-4: 4, CL=5
/openbmc/u-boot/board/Seagate/dockstar/
H A Dkwbimage.cfg24 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
39 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
40 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
88 # bit6-4: 4, CL=5
/openbmc/u-boot/board/Synology/ds109/
H A Dkwbimage.cfg25 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
40 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
41 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
89 # bit6-4: 4, CL=5
/openbmc/u-boot/board/Seagate/goflexhome/
H A Dkwbimage.cfg27 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
42 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
43 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
91 # bit6-4: 4, CL=5
/openbmc/u-boot/board/Marvell/dreamplug/
H A Dkwbimage.cfg22 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
37 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
38 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
86 # bit6-4: 4, CL=5
/openbmc/u-boot/board/Marvell/sheevaplug/
H A Dkwbimage.cfg21 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
36 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
37 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
85 # bit6-4: 4, CL=5
/openbmc/u-boot/board/Marvell/guruplug/
H A Dkwbimage.cfg21 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
36 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
37 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
85 # bit6-4: 4, CL=5
/openbmc/u-boot/board/compulab/cl-som-imx7/
H A DMAINTAINERS1 CL-SOM-IMX7 BOARD
/openbmc/u-boot/board/compulab/cl-som-am57x/
H A DMAINTAINERS1 CL-SOM-AM57x BOARD
/openbmc/u-boot/board/LaCie/netspace_v2/
H A Dkwbimage.cfg22 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
37 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
38 # bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
85 # bit6-4: 4, CL=5
H A Dkwbimage-is2.cfg22 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
37 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
38 # bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
85 # bit6-4: 4, CL=5
H A Dkwbimage-ns2l.cfg22 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
37 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
38 # bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
85 # bit6-4: 4, CL=5
/openbmc/u-boot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg25 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
40 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
41 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
89 # bit6-4: 4, CL=5
/openbmc/u-boot/board/iomega/iconnect/
H A Dkwbimage.cfg21 # Dram initalization for SINGLE x16 CL=5 @ 400MHz
36 # bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
37 # bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
85 # bit6-4: 0x4, CL=5
/openbmc/u-boot/board/Marvell/openrd/
H A Dkwbimage.cfg21 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
36 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
37 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
85 # bit6-4: 4, CL=5
/openbmc/u-boot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg22 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
37 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
38 # bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
85 # bit6-4: 4, CL=5
/openbmc/u-boot/board/raidsonic/ib62x0/
H A Dkwbimage.cfg22 # Dram initalization for SINGLE x16 CL=5 @ 400MHz
37 # bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
38 # bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
86 # bit6-4: 0x4, CL=5
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg25 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
46 # bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
47 # bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
95 # bit6-4: 5, CAS Latency (CL) 5
/openbmc/u-boot/arch/arm/mach-imx/mx7/
H A DKconfig24 bool "CL-SOM-iMX7"
/openbmc/u-boot/configs/
H A Dcl-som-imx7_defconfig26 CONFIG_SYS_PROMPT="CL-SOM-iMX7 # "
/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg48 # bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
49 # bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
103 # bit6-4: 5, CAS Latency (CL) 5

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