Home
last modified time | relevance | path

Searched refs:BIT (Results 1 – 25 of 774) sorted by relevance

12345678910>>...31

/openbmc/qemu/hw/net/
H A Dtulip.h13 #define CSR0_SWR BIT(0)
14 #define CSR0_BAR BIT(1)
17 #define CSR0_BLE BIT(7)
27 #define CSR0_RLE BIT(23)
28 #define CSR0_WIE BIT(24)
32 #define CSR5_TI BIT(0)
33 #define CSR5_TPS BIT(1)
34 #define CSR5_TU BIT(2)
35 #define CSR5_TJT BIT(3)
36 #define CSR5_LNP_ANC BIT(4)
[all …]
/openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dtimer.c40 #define TCU_TCSR_PWM_SD BIT(9)
41 #define TCU_TCSR_PWM_INITL_HIGH BIT(8)
42 #define TCU_TCSR_PWM_EN BIT(7)
51 #define TCU_TCSR_EXT_EN BIT(2)
52 #define TCU_TCSR_RTC_EN BIT(1)
53 #define TCU_TCSR_PCK_EN BIT(0)
55 #define TCU_TER_TCEN5 BIT(5)
56 #define TCU_TER_TCEN4 BIT(4)
57 #define TCU_TER_TCEN3 BIT(3)
58 #define TCU_TER_TCEN2 BIT(2)
[all …]
H A Dpll.c85 #define CPM_CPCSR_H2DIV_BUSY BIT(2)
86 #define CPM_CPCSR_H0DIV_BUSY BIT(1)
87 #define CPM_CPCSR_CDIV_BUSY BIT(0)
100 #define CPM_CPXPCR_XLOCK BIT(6)
101 #define CPM_CPXPCR_XPLL_ON BIT(4)
102 #define CPM_CPXPCR_XF_MODE BIT(3)
103 #define CPM_CPXPCR_XPLLBP BIT(1)
104 #define CPM_CPXPCR_XPLLEN BIT(0)
111 #define CPM_USBPCR_USB_MODE BIT(31) /* 1: OTG, 0: UDC*/
112 #define CPM_USBPCR_AVLD_REG BIT(30)
[all …]
/openbmc/qemu/include/hw/usb/
H A Ddwc2-regs.h48 #define GOTGCTL_CHIRPEN BIT(27)
51 #define GOTGCTL_OTGVER BIT(20)
52 #define GOTGCTL_BSESVLD BIT(19)
53 #define GOTGCTL_ASESVLD BIT(18)
54 #define GOTGCTL_DBNC_SHORT BIT(17)
55 #define GOTGCTL_CONID_B BIT(16)
56 #define GOTGCTL_DBNCE_FLTR_BYPASS BIT(15)
57 #define GOTGCTL_DEVHNPEN BIT(11)
58 #define GOTGCTL_HSTSETHNPEN BIT(10)
59 #define GOTGCTL_HNPREQ BIT(9)
[all …]
/openbmc/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
342 #define AR933X_PLL_CLK_CTRL_BYPASS BIT(2)
368 #define AR934X_PLL_CPU_CONFIG_PLLPWD BIT(30)
369 #define AR934X_PLL_CPU_CONFIG_UPDATING BIT(31)
381 #define AR934X_PLL_DDR_CONFIG_PLLPWD BIT(30)
382 #define AR934X_PLL_DDR_CONFIG_UPDATING BIT(31)
384 #define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
385 #define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
386 #define AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
[all …]
/openbmc/qemu/include/hw/net/
H A Dnpcm_gmac.h42 #define RX_DESC_RDES0_OWN BIT(31)
44 #define RX_DESC_RDES0_DEST_ADDR_FILT_FAIL BIT(30)
50 #define RX_DESC_RDES0_ERR_SUMM_MASK BIT(15)
52 #define RX_DESC_RDES0_DESC_ERR_MASK BIT(14)
54 #define RX_DESC_RDES0_SRC_ADDR_FILT_FAIL_MASK BIT(13)
56 #define RX_DESC_RDES0_LEN_ERR_MASK BIT(12)
58 #define RX_DESC_RDES0_OVRFLW_ERR_MASK BIT(11)
60 #define RX_DESC_RDES0_VLAN_TAG_MASK BIT(10)
62 #define RX_DESC_RDES0_FIRST_DESC_MASK BIT(9)
64 #define RX_DESC_RDES0_LAST_DESC_MASK BIT(8)
[all …]
/openbmc/u-boot/drivers/sound/
H A Dmax98090.h71 #define M98090_SWRESET_MASK BIT(7)
76 #define M98090_SR_96K_MASK BIT(5)
79 #define M98090_SR_32K_MASK BIT(4)
82 #define M98090_SR_48K_MASK BIT(3)
85 #define M98090_SR_44K1_MASK BIT(2)
88 #define M98090_SR_16K_MASK BIT(1)
91 #define M98090_SR_8K_MASK BIT(0)
97 #define M98090_SR_ALL_NUM BIT(M98090_SR_ALL_WIDTH)
102 #define M98090_RJ_M_MASK BIT(5)
105 #define M98090_RJ_S_MASK BIT(4)
[all …]
H A Dmax98088.h97 #define M98088_DAI_MAS BIT(7)
98 #define M98088_DAI_WCI BIT(6)
99 #define M98088_DAI_BCI BIT(5)
100 #define M98088_DAI_DLY BIT(4)
101 #define M98088_DAI_TDM BIT(2)
102 #define M98088_DAI_FSW BIT(1)
103 #define M98088_DAI_WS BIT(0)
106 #define M98088_DAI_BSEL64 BIT(0)
107 #define M98088_DAI_OSR64 BIT(6)
110 #define M98088_S1NORMAL BIT(6)
[all …]
/openbmc/u-boot/drivers/clk/sunxi/
H A Dclk_r40.c16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_MMC3] = GATE(0x060, BIT(11)),
20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
22 [CLK_BUS_SPI2] = GATE(0x060, BIT(22)),
23 [CLK_BUS_SPI3] = GATE(0x060, BIT(23)),
24 [CLK_BUS_OTG] = GATE(0x060, BIT(25)),
25 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
[all …]
H A Dclk_a31.c16 [CLK_AHB1_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_AHB1_MMC3] = GATE(0x060, BIT(11)),
20 [CLK_AHB1_EMAC] = GATE(0x060, BIT(17)),
21 [CLK_AHB1_SPI0] = GATE(0x060, BIT(20)),
22 [CLK_AHB1_SPI1] = GATE(0x060, BIT(21)),
23 [CLK_AHB1_SPI2] = GATE(0x060, BIT(22)),
24 [CLK_AHB1_SPI3] = GATE(0x060, BIT(23)),
25 [CLK_AHB1_OTG] = GATE(0x060, BIT(24)),
[all …]
H A Dclk_h3.c16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
22 [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
23 [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
24 [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
25 [CLK_BUS_EHCI2] = GATE(0x060, BIT(26)),
[all …]
H A Dclk_a64.c16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
22 [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
23 [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
24 [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
25 [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
[all …]
H A Dclk_a83t.c16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
22 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
23 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
24 [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
25 [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
[all …]
H A Dclk_a23.c16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
20 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
21 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
22 [CLK_BUS_EHCI] = GATE(0x060, BIT(26)),
23 [CLK_BUS_OHCI] = GATE(0x060, BIT(29)),
25 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
26 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[all …]
H A Dclk_a10.c16 [CLK_AHB_OTG] = GATE(0x060, BIT(0)),
17 [CLK_AHB_EHCI0] = GATE(0x060, BIT(1)),
18 [CLK_AHB_OHCI0] = GATE(0x060, BIT(2)),
19 [CLK_AHB_EHCI1] = GATE(0x060, BIT(3)),
20 [CLK_AHB_OHCI1] = GATE(0x060, BIT(4)),
21 [CLK_AHB_MMC0] = GATE(0x060, BIT(8)),
22 [CLK_AHB_MMC1] = GATE(0x060, BIT(9)),
23 [CLK_AHB_MMC2] = GATE(0x060, BIT(10)),
24 [CLK_AHB_MMC3] = GATE(0x060, BIT(11)),
25 [CLK_AHB_EMAC] = GATE(0x060, BIT(17)),
[all …]
H A Dclk_a80.c16 [CLK_SPI0] = GATE(0x430, BIT(31)),
17 [CLK_SPI1] = GATE(0x434, BIT(31)),
18 [CLK_SPI2] = GATE(0x438, BIT(31)),
19 [CLK_SPI3] = GATE(0x43c, BIT(31)),
21 [CLK_BUS_MMC] = GATE(0x580, BIT(8)),
22 [CLK_BUS_SPI0] = GATE(0x580, BIT(20)),
23 [CLK_BUS_SPI1] = GATE(0x580, BIT(21)),
24 [CLK_BUS_SPI2] = GATE(0x580, BIT(22)),
25 [CLK_BUS_SPI3] = GATE(0x580, BIT(23)),
27 [CLK_BUS_UART0] = GATE(0x594, BIT(16)),
[all …]
/openbmc/u-boot/drivers/net/
H A Dftgmac100.h73 #define FTGMAC100_INT_RPKT_BUF BIT(0)
74 #define FTGMAC100_INT_RPKT_FIFO BIT(1)
75 #define FTGMAC100_INT_NO_RXBUF BIT(2)
76 #define FTGMAC100_INT_RPKT_LOST BIT(3)
77 #define FTGMAC100_INT_XPKT_ETH BIT(4)
78 #define FTGMAC100_INT_XPKT_FIFO BIT(5)
79 #define FTGMAC100_INT_NO_NPTXBUF BIT(6)
80 #define FTGMAC100_INT_XPKT_LOST BIT(7)
81 #define FTGMAC100_INT_AHB_ERR BIT(8)
82 #define FTGMAC100_INT_PHYSTS_CHG BIT(9)
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dreset_manager_arria10.h79 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK BIT(1)
80 #define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK BIT(0)
81 #define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK BIT(1)
82 #define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK BIT(2)
83 #define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK BIT(3)
84 #define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK BIT(4)
85 #define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK BIT(5)
86 #define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK BIT(6)
87 #define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK BIT(7)
88 #define ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK BIT(8)
[all …]
H A Dfpga_manager_arria10.h10 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0)
11 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1)
12 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2)
13 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3)
14 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4)
15 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5)
16 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6)
17 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK BIT(7)
18 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK BIT(8)
19 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK BIT(9)
[all …]
/openbmc/u-boot/include/net/pfe_eth/pfe/cbus/
H A Demac.h32 #define EMAC_IEVENT_HBERR BIT(31)
33 #define EMAC_IEVENT_BABR BIT(30)
34 #define EMAC_IEVENT_BABT BIT(29)
35 #define EMAC_IEVENT_GRA BIT(28)
36 #define EMAC_IEVENT_TXF BIT(27)
37 #define EMAC_IEVENT_TXB BIT(26)
38 #define EMAC_IEVENT_RXF BIT(25)
39 #define EMAC_IEVENT_RXB BIT(24)
40 #define EMAC_IEVENT_MII BIT(23)
41 #define EMAC_IEVENT_EBERR BIT(22)
[all …]
/openbmc/u-boot/drivers/mmc/
H A Dtmio-common.h11 #define TMIO_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
12 #define TMIO_SD_CMD_MULTI BIT(13) /* multiple block transfer */
13 #define TMIO_SD_CMD_RD BIT(12) /* 1: read, 0: write */
14 #define TMIO_SD_CMD_DATA BIT(11) /* data transfer */
15 #define TMIO_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */
24 #define TMIO_SD_STOP_SEC BIT(8) /* use sector count */
25 #define TMIO_SD_STOP_STP BIT(0) /* issue CMD12 */
32 #define TMIO_SD_INFO1_CD BIT(5) /* state of card detect */
33 #define TMIO_SD_INFO1_INSERT BIT(4) /* card inserted */
34 #define TMIO_SD_INFO1_REMOVE BIT(3) /* card removed */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dlvds_rk3288.h10 #define RK3288_LVDS_CH0_REG0_LVDS_EN BIT(7)
11 #define RK3288_LVDS_CH0_REG0_TTL_EN BIT(6)
12 #define RK3288_LVDS_CH0_REG0_LANECK_EN BIT(5)
13 #define RK3288_LVDS_CH0_REG0_LANE4_EN BIT(4)
14 #define RK3288_LVDS_CH0_REG0_LANE3_EN BIT(3)
15 #define RK3288_LVDS_CH0_REG0_LANE2_EN BIT(2)
16 #define RK3288_LVDS_CH0_REG0_LANE1_EN BIT(1)
17 #define RK3288_LVDS_CH0_REG0_LANE0_EN BIT(0)
20 #define RK3288_LVDS_CH0_REG1_LANECK_BIAS BIT(5)
21 #define RK3288_LVDS_CH0_REG1_LANE4_BIAS BIT(4)
[all …]
/openbmc/u-boot/drivers/phy/marvell/
H A Dcomphy_a3700.h27 #define rb_pin_pu_iveref BIT(1)
28 #define rb_pin_reset_core BIT(11)
29 #define rb_pin_reset_comphy BIT(12)
30 #define rb_pin_pu_pll BIT(16)
31 #define rb_pin_pu_rx BIT(17)
32 #define rb_pin_pu_tx BIT(18)
33 #define rb_pin_tx_idle BIT(19)
38 #define rb_phy_rx_init BIT(30)
41 #define rb_rx_init_done BIT(0)
42 #define rb_pll_ready_rx BIT(2)
[all …]
/openbmc/u-boot/board/alliedtelesis/SBx81LIFKW/
H A Dsbx81lifkw.c27 #define SBX81LIFKW_OE_LOW ~(BIT(31) | BIT(30) | BIT(28) | BIT(27) | \
28 BIT(18) | BIT(17) | BIT(13) | BIT(12) | \
29 BIT(10))
30 #define SBX81LIFKW_OE_HIGH ~(BIT(0) | BIT(1) | BIT(7))
31 #define SBX81LIFKW_OE_VAL_LOW (BIT(31) | BIT(30) | BIT(28) | BIT(27))
32 #define SBX81LIFKW_OE_VAL_HIGH (BIT(0) | BIT(1))
46 BIT(10),
47 BIT(18) | BIT(10)
52 BIT(18) | BIT(10),
53 BIT(18) | BIT(10)
[all …]
/openbmc/u-boot/arch/arm/mach-aspeed/ast2600/
H A Dscu_info.c59 if(strap1 & BIT(6)) { in aspeed_get_mac_phy_interface()
66 if(strap1 & BIT(7)) { in aspeed_get_mac_phy_interface()
74 if(strap2 & BIT(0)) { in aspeed_get_mac_phy_interface()
81 if(strap2 & BIT(1)) { in aspeed_get_mac_phy_interface()
99 if (!(sb_sts & BIT(6))) in aspeed_print_security_info()
102 if (qsr & BIT(7)) { in aspeed_print_security_info()
108 if (qsr & BIT(27)) { in aspeed_print_security_info()
146 #define SYS_WDT8_SW_RESET BIT(15)
147 #define SYS_WDT8_ARM_RESET BIT(14)
148 #define SYS_WDT8_FULL_RESET BIT(13)
[all …]

12345678910>>...31