1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 22baa9972STien Fong Chee /* 32baa9972STien Fong Chee * Copyright (C) 2017 Intel Corporation <www.intel.com> 42baa9972STien Fong Chee * All rights reserved. 52baa9972STien Fong Chee */ 62baa9972STien Fong Chee 72baa9972STien Fong Chee #ifndef _FPGA_MANAGER_ARRIA10_H_ 82baa9972STien Fong Chee #define _FPGA_MANAGER_ARRIA10_H_ 92baa9972STien Fong Chee 102baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0) 112baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1) 122baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2) 132baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3) 142baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4) 152baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5) 162baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6) 172baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK BIT(7) 182baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK BIT(8) 192baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK BIT(9) 202baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK BIT(10) 212baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11) 222baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK BIT(12) 232baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13) 242baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16) 252baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17) 262baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18) 272baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\ 282baa9972STien Fong Chee ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\ 292baa9972STien Fong Chee ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\ 302baa9972STien Fong Chee ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK) 312baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK BIT(24) 322baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSK BIT(25) 332baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK BIT(28) 342baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSK BIT(29) 352baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB 16 362baa9972STien Fong Chee 372baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK BIT(0) 382baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK BIT(1) 392baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK BIT(2) 402baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK BIT(8) 412baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK BIT(16) 422baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK BIT(24) 432baa9972STien Fong Chee 442baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK BIT(0) 452baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16) 462baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24) 472baa9972STien Fong Chee 482baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0) 492baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8) 502baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000 512baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24) 522baa9972STien Fong Chee #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16 532baa9972STien Fong Chee 542baa9972STien Fong Chee #ifndef __ASSEMBLY__ 552baa9972STien Fong Chee 562baa9972STien Fong Chee struct socfpga_fpga_manager { 572baa9972STien Fong Chee u32 _pad_0x0_0x7[2]; 582baa9972STien Fong Chee u32 dclkcnt; 592baa9972STien Fong Chee u32 dclkstat; 602baa9972STien Fong Chee u32 gpo; 612baa9972STien Fong Chee u32 gpi; 622baa9972STien Fong Chee u32 misci; 632baa9972STien Fong Chee u32 _pad_0x1c_0x2f[5]; 642baa9972STien Fong Chee u32 emr_data0; 652baa9972STien Fong Chee u32 emr_data1; 662baa9972STien Fong Chee u32 emr_data2; 672baa9972STien Fong Chee u32 emr_data3; 682baa9972STien Fong Chee u32 emr_data4; 692baa9972STien Fong Chee u32 emr_data5; 702baa9972STien Fong Chee u32 emr_valid; 712baa9972STien Fong Chee u32 emr_en; 722baa9972STien Fong Chee u32 jtag_config; 732baa9972STien Fong Chee u32 jtag_status; 742baa9972STien Fong Chee u32 jtag_kick; 752baa9972STien Fong Chee u32 _pad_0x5c_0x5f; 762baa9972STien Fong Chee u32 jtag_data_w; 772baa9972STien Fong Chee u32 jtag_data_r; 782baa9972STien Fong Chee u32 _pad_0x68_0x6f[2]; 792baa9972STien Fong Chee u32 imgcfg_ctrl_00; 802baa9972STien Fong Chee u32 imgcfg_ctrl_01; 812baa9972STien Fong Chee u32 imgcfg_ctrl_02; 822baa9972STien Fong Chee u32 _pad_0x7c_0x7f; 832baa9972STien Fong Chee u32 imgcfg_stat; 842baa9972STien Fong Chee u32 intr_masked_status; 852baa9972STien Fong Chee u32 intr_mask; 862baa9972STien Fong Chee u32 intr_polarity; 872baa9972STien Fong Chee u32 dma_config; 882baa9972STien Fong Chee u32 imgcfg_fifo_status; 892baa9972STien Fong Chee }; 902baa9972STien Fong Chee 912baa9972STien Fong Chee /* Functions */ 922baa9972STien Fong Chee int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size); 932baa9972STien Fong Chee int fpgamgr_program_finish(void); 942baa9972STien Fong Chee int is_fpgamgr_user_mode(void); 952baa9972STien Fong Chee int fpgamgr_wait_early_user_mode(void); 962baa9972STien Fong Chee 972baa9972STien Fong Chee #endif /* __ASSEMBLY__ */ 982baa9972STien Fong Chee 992baa9972STien Fong Chee #endif /* _FPGA_MANAGER_ARRIA10_H_ */ 100