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Searched refs:ASPEED_SYS_RESET_CTRL (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/arm/mach-aspeed/ast2400/
H A Dscu_info.c107 u32 rest = readl(ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
111 writel(readl(ASPEED_SYS_RESET_CTRL) & ~SYS_WDT1_RESET, ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
115 writel(readl(ASPEED_SYS_RESET_CTRL) & ~SYS_WDT2_RESET, ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
123 writel(readl(ASPEED_SYS_RESET_CTRL) & ~SYS_WDT3_RESET, ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
127 writel(readl(ASPEED_SYS_RESET_CTRL) & ~SYS_EXT_RESET, ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
131 writel(readl(ASPEED_SYS_RESET_CTRL) & ~SYS_PWR_RESET_FLAG, ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
/openbmc/u-boot/arch/arm/mach-aspeed/ast2500/
H A Dscu_info.c136 u32 rest = readl(ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
140 writel(readl(ASPEED_SYS_RESET_CTRL) & ~SYS_WDT1_RESET, ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
144 writel(readl(ASPEED_SYS_RESET_CTRL) & ~SYS_WDT2_RESET, ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
152 writel(readl(ASPEED_SYS_RESET_CTRL) & ~SYS_WDT3_RESET, ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
156 writel(readl(ASPEED_SYS_RESET_CTRL) & ~SYS_EXT_RESET, ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
160 writel(readl(ASPEED_SYS_RESET_CTRL) & ~SYS_PWR_RESET_FLAG, ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
/openbmc/u-boot/arch/arm/mach-aspeed/ast2600/
H A Dscu_info.c218 u32 rest = readl(ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
223 writel(rest, ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
229 HANDLE_WDTx_RESET(4, rest, ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
230 HANDLE_WDTx_RESET(3, rest, ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
231 HANDLE_WDTx_RESET(2, rest, ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
232 HANDLE_WDTx_RESET(1, rest, ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
236 writel(SYS_CM3_EXT_RESET, ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
243 writel(SYS_PCI1_RESET, ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
248 writel(SYS_PCI2_RESET, ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
255 writel(SYS_FLASH_ABR_RESET, ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
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/openbmc/u-boot/arch/arm/include/asm/arch-aspeed/
H A Dplatform.h21 #define ASPEED_SYS_RESET_CTRL 0x1e6e203C macro
36 #define ASPEED_SYS_RESET_CTRL 0x1e6e203C macro
54 #define ASPEED_SYS_RESET_CTRL 0x1e6e2064 macro