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Searched refs:A12 (Results 1 – 25 of 41) sorted by relevance

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/openbmc/phosphor-webui/app/assets/icons/
H A Dicon-plus.svg1 <svg viewBox="0 0 32 32"><path d="M16 4A12 12 0 1 1 4 16 12 12 0 0 1 16 4m0-2a14 14 0 1 0 14 14A14 …
H A Dicon-information.svg1 …<path d="M16 30a14 14 0 1 1 14-14 14 14 0 0 1-14 14zm0-26a12 12 0 1 0 12 12A12 12 0 0 0 16 4z"/><p…
/openbmc/linux/drivers/pinctrl/aspeed/
H A Dpinctrl-aspeed-g4.c1277 #define A12 152 macro
1278 SIG_EXPR_LIST_DECL_SINGLE(A12, GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0));
1279 SIG_EXPR_LIST_DECL_SINGLE(A12, RMII1TXEN, RMII1, RMII1_DESC);
1280 SIG_EXPR_LIST_DECL_SINGLE(A12, RGMII1TXCK, RGMII1);
1281 PIN_DECL_(A12, SIG_EXPR_LIST_PTR(A12, GPIOT0),
1282 SIG_EXPR_LIST_PTR(A12, RMII1TXEN),
1283 SIG_EXPR_LIST_PTR(A12, RGMII1TXCK));
1911 ASPEED_PINCTRL_PIN(A12),
2474 ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, A12, A13, SCU90, 9),
2475 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A12, A13, SCU90, 12),
[all …]
H A Dpinctrl-aspeed-g5.c155 #define A12 17 macro
156 SIG_EXPR_LIST_DECL_SINGLE(A12, SD1CMD, SD1, SD1_DESC);
157 SIG_EXPR_LIST_DECL_SINGLE(A12, SDA10, I2C10, I2C10_DESC);
158 PIN_DECL_2(A12, GPIOC1, SD1CMD, SDA10);
160 FUNC_GROUP_DECL(I2C10, C12, A12);
200 FUNC_GROUP_DECL(SD1, C12, A12, B12, D9, D10, E12, C11, B11);
1905 ASPEED_PINCTRL_PIN(A12),
H A Dpinctrl-aspeed-g6.c711 #define A12 98 macro
712 SSSF_PIN_DECL(A12, GPIOM2, NDSR1, SIG_DESC_SET(SCU41C, 2));
1638 ASPEED_PINCTRL_PIN(A12),
2490 ASPEED_PULL_DOWN_PINCONF(A12, SCU61C, 2),
/openbmc/linux/Documentation/admin-guide/device-mapper/
H A Ddm-raid.rst146 A5 A6 A7 A8 A9 A9 A10 A11 A12
150 A6 A5 A9 A7 A8 A10 A9 A12 A11
164 A5 A6 A7 A8 A9 A9 A10 A11 A12
165 A6 A5 A9 A7 A8 A10 A9 A12 A11
/openbmc/linux/arch/arm/
H A DKconfig862 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
864 - Cortex-A12 852422: Execution of a sequence of instructions might
866 any Cortex-A12 cores yet.
875 This option enables the workaround for the 821420 Cortex-A12
882 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
885 This option enables the workaround for the 825619 Cortex-A12
894 This option enables the workaround for the 857271 Cortex-A12
915 This is identical to Cortex-A12 erratum 852422. It is a separate
916 config option from the A12 erratum due to the way errata are checked
925 This is identical to Cortex-A12 erratum 857271. It is a separate
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dstm32429i-eval-u-boot.dtsi206 <STM32_PINMUX('G', 2, AF12)>, /* A12 */
/openbmc/linux/drivers/net/mdio/
H A DKconfig55 A12, A10s, etc.)
/openbmc/linux/arch/m68k/fpsp040/
H A Dbindec.S561 | A12. Calculate YINT = FINT(Y) according to user's rounding mode.
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am625-beagleplay.dts529 AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */
H A Dk3-am62-verdin.dtsi756 AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */ /* SODIMM 91 */
/openbmc/linux/arch/arm/mm/
H A Dproc-v7.S509 ldr r10, =0x00000c0d @ Cortex-A12 primary part number
/openbmc/u-boot/drivers/pinctrl/renesas/
H A Dpfc-r8a77970.c165 #define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
435 PINMUX_IPSR_GPSR(IP1_19_16, A12),
H A Dpfc-r8a77990.c73 #define GPSR1_12 F_(A12, IP4_15_12)
226 #define IP4_15_12 FM(A12) FM(RX5_A) FM(MSIOF2_SS2_B) FM(VI4_DATA17) FM(VI5_DATA3_A) FM(DU_DG6)…
726 PINMUX_IPSR_GPSR(IP4_15_12, A12),
H A Dpfc-r8a7796.c79 #define GPSR1_12 F_(A12, IP3_15_12)
247 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU…
779 PINMUX_IPSR_GPSR(IP3_15_12, A12),
H A Dpfc-r8a7795.c73 #define GPSR1_12 F_(A12, IP3_15_12)
241 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU…
777 PINMUX_IPSR_GPSR(IP3_15_12, A12),
/openbmc/linux/drivers/pinctrl/renesas/
H A Dpfc-r8a77970.c176 #define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(…
444 PINMUX_IPSR_GPSR(IP1_19_16, A12),
H A Dpfc-r8a77980.c210 #define IP1_19_16 FM(DU_DB2) FM(HSCK0_A) F_(0, 0) FM(A12) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) …
521 PINMUX_IPSR_GPSR(IP1_19_16, A12),
H A Dpfc-r8a77990.c98 #define GPSR1_12 F_(A12, IP4_15_12)
251 #define IP4_15_12 FM(A12) FM(RX5_A) FM(MSIOF2_SS2_B) FM(VI4_DATA17) FM(VI5_DATA3_A) FM(DU_DG6)…
756 PINMUX_IPSR_GPSR(IP4_15_12, A12),
H A Dpfc-sh7734.c650 PINMUX_IPSR_GPSR(IP0_25_24, A12),
1388 GPIO_FN(A12), GPIO_FN(LCD_DATA12_A), GPIO_FN(TIOC3A_C),
H A Dpfc-r8a77951.c115 #define GPSR1_12 F_(A12, IP3_15_12)
283 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU…
824 PINMUX_IPSR_GPSR(IP3_15_12, A12),
H A Dpfc-r8a7796.c120 #define GPSR1_12 F_(A12, IP3_15_12)
288 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU…
828 PINMUX_IPSR_GPSR(IP3_15_12, A12),
H A Dpfc-r8a77965.c120 #define GPSR1_12 F_(A12, IP3_15_12)
288 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU…
830 PINMUX_IPSR_GPSR(IP3_15_12, A12),
H A Dpfc-r8a779a0.c370 #define IP1SR1_19_16 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DG2) FM(A12) F_(0, 0) F_(0, 0…
841 PINMUX_IPSR_GPSR(IP1SR1_19_16, A12),

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