| /openbmc/u-boot/board/ti/ks2_evm/ |
| H A D | mux-k2g.h | 32 { 0, MODE(0) }, /* GPMCAD0 */
309 { 235, MODE(0) },
310 { 236, MODE(0) },
311 { 237, MODE(0) },
312 { 238, MODE(0) },
313 { 239, MODE(0) },
314 { 240, MODE(0) },
315 { 241, MODE(0) },
316 { 242, MODE(0) },
317 { 243, MODE(0) },
[all …]
|
| /openbmc/u-boot/board/siemens/rut/ |
| H A D | mux.c | 28 {OFFSET(ddr_resetn), (MODE(0))},
30 {OFFSET(ddr_ck), (MODE(0))},
31 {OFFSET(ddr_nck), (MODE(0))},
54 {OFFSET(ddr_odt), (MODE(0))},
83 {OFFSET(gpmc_ad8), (MODE(1))},
84 {OFFSET(gpmc_ad9), (MODE(1))},
85 {OFFSET(gpmc_ad10), (MODE(1))},
86 {OFFSET(gpmc_ad11), (MODE(1))},
87 {OFFSET(gpmc_ad12), (MODE(1))},
88 {OFFSET(gpmc_ad13), (MODE(1))},
[all …]
|
| /openbmc/u-boot/board/siemens/draco/ |
| H A D | mux.c | 34 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
36 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
65 {OFFSET(emu0), MODE(7)}, /* LED1 GPIO3_7 */
229 {OFFSET(mii1_col), (MODE(3) | RXACTIVE)},
230 {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)},
232 {OFFSET(mii1_txen), (MODE(1))},
233 {OFFSET(mii1_rxdv), (MODE(3) | RXACTIVE)},
234 {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)},
236 {OFFSET(mii1_txd1), (MODE(1))},
237 {OFFSET(mii1_txd0), (MODE(1))},
[all …]
|
| /openbmc/u-boot/board/bosch/shc/ |
| H A D | mux.c | 108 {OFFSET(tdo), (MODE(0) | PULLUP_EN)},
110 {OFFSET(ntrst), (MODE(0) | RXACTIVE)},
114 {OFFSET(rsvd2), (MODE(0) | PULLUP_EN)},
176 {OFFSET(mii1_col), MODE(0) | RXACTIVE},
177 {OFFSET(mii1_crs), MODE(0) | RXACTIVE},
179 {OFFSET(mii1_txen), MODE(0)},
180 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},
181 {OFFSET(mii1_txd3), MODE(0)},
182 {OFFSET(mii1_txd2), MODE(0)},
183 {OFFSET(mii1_txd1), MODE(0) | RXACTIVE},
[all …]
|
| /openbmc/u-boot/board/BuR/brppt1/ |
| H A D | mux.c | 20 {OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)},
26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
37 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
82 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
84 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
85 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
100 {OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */
102 {OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */
103 {OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */
104 {OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */
[all …]
|
| /openbmc/u-boot/board/siemens/pxm2/ |
| H A D | mux.c | 68 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
69 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
84 {OFFSET(gpmc_a0), MODE(2)}, /* RGMII2_TCTL */
86 {OFFSET(gpmc_a2), MODE(2)}, /* RGMII2_TD3 */
87 {OFFSET(gpmc_a3), MODE(2)}, /* RGMII2_TD2 */
88 {OFFSET(gpmc_a4), MODE(2)}, /* RGMII2_TD1 */
89 {OFFSET(gpmc_a5), MODE(2)}, /* RGMII2_TD0 */
90 {OFFSET(gpmc_a6), MODE(7)}, /* RGMII2_TCLK */
93 {OFFSET(gpmc_a9), MODE(7)}, /* RGMII2_RD2 */
142 {OFFSET(lcd_pclk), (MODE(0))}, /* LCD_PCLK */
[all …]
|
| /openbmc/u-boot/board/BuR/brxre1/ |
| H A D | mux.c | 20 {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
22 {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
24 {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
36 {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
44 {OFFSET(uart1_txd), MODE(2) | RXACTIVE},
56 {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
62 {OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},
64 {OFFSET(gpmc_csn0), (MODE(7) | PULLUDDIS)},
70 {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},
72 {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)},
[all …]
|
| /openbmc/u-boot/board/ti/am335x/ |
| H A D | mux.c | 108 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
110 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
116 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
118 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
125 {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
128 {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
163 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
165 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
166 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
167 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
[all …]
|
| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-graphics/gphoto2/libgphoto2/ |
| H A D | 40-libgphoto2.rules | 10 ATTRS{idVendor}=="0979", ATTRS{idProduct}=="0227", MODE="l36"
44 ATTRS{idVendor}=="0553", ATTRS{idProduct}=="0202", MODE="l36"
45 ATTRS{idVendor}=="06bd", ATTRS{idProduct}=="0403", MODE="l36"
46 ATTRS{idVendor}=="06bd", ATTRS{idProduct}=="0404", MODE="l36"
47 ATTRS{idVendor}=="04fc", ATTRS{idProduct}=="504b", MODE="l36"
48 ATTRS{idVendor}=="0553", ATTRS{idProduct}=="0202", MODE="l36"
49 ATTRS{idVendor}=="04fc", ATTRS{idProduct}=="504a", MODE="l36"
50 ATTRS{idVendor}=="0553", ATTRS{idProduct}=="0202", MODE="l36"
51 ATTRS{idVendor}=="08ca", ATTRS{idProduct}=="0111", MODE="l36"
52 ATTRS{idVendor}=="04fc", ATTRS{idProduct}=="504a", MODE="l36"
[all …]
|
| /openbmc/u-boot/board/compulab/cm_t43/ |
| H A D | mux.c | 12 {OFFSET(mii1_txen), MODE(2)},
13 {OFFSET(mii1_txd3), MODE(2)},
14 {OFFSET(mii1_txd2), MODE(2)},
15 {OFFSET(mii1_txd1), MODE(2)},
16 {OFFSET(mii1_txd0), MODE(2)},
17 {OFFSET(mii1_txclk), MODE(2)},
28 {OFFSET(gpmc_a0), MODE(2)}, /* txen */
29 {OFFSET(gpmc_a2), MODE(2)}, /* txd3 */
30 {OFFSET(gpmc_a3), MODE(2)}, /* txd2 */
31 {OFFSET(gpmc_a4), MODE(2)}, /* txd1 */
[all …]
|
| /openbmc/u-boot/board/ti/am43xx/ |
| H A D | mux.c | 15 {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
16 {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TD1 */
17 {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TD0 */
18 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RD1 */
19 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RD0 */
28 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
30 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
31 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
32 {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
33 {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
[all …]
|
| /openbmc/u-boot/board/birdland/bav335x/ |
| H A D | mux.c | 86 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
88 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
94 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
96 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
104 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
105 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
121 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
123 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
124 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
125 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
[all …]
|
| /openbmc/u-boot/board/ti/ti814x/ |
| H A D | mux.c | 31 {OFFSET(pincntl1), PULLUP_EN | MODE(0x01)}, /* SD1_CLK */
32 {OFFSET(pincntl2), PULLUP_EN | MODE(0x01)}, /* SD1_CMD */
38 {OFFSET(pincntl75), MODE(0x40)}, /* SD1_SDWP */
44 {OFFSET(pincntl232), MODE(0x01)}, /* EMAC_RMREFCLK */
47 {OFFSET(pincntl235), MODE(0x01)}, /* EMAC[0]_MTCLK */
48 {OFFSET(pincntl236), MODE(0x01)}, /* EMAC[0]_MCOL */
49 {OFFSET(pincntl237), MODE(0x01)}, /* EMAC[0]_MCRS */
50 {OFFSET(pincntl238), MODE(0x01)}, /* EMAC[0]_MRXER */
51 {OFFSET(pincntl239), MODE(0x01)}, /* EMAC[0]_MRCLK */
60 {OFFSET(pincntl248), MODE(0x01)}, /* EMAC[0]_MRXDV */
[all …]
|
| /openbmc/u-boot/board/vscom/baltos/ |
| H A D | mux.c | 41 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
43 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
50 {OFFSET(mii1_txen), MODE(1)}, /* RGMII1_TCTL */
51 {OFFSET(mii1_txd1), MODE(1)}, /* RGMII1_TCTL */
52 {OFFSET(mii1_txd0), MODE(1)}, /* RGMII1_TCTL */
62 {OFFSET(gpmc_a0), MODE(2)}, /* RGMII1_TCTL */
64 {OFFSET(gpmc_a2), MODE(2)}, /* RGMII1_TD3 */
65 {OFFSET(gpmc_a3), MODE(2)}, /* RGMII1_TD2 */
66 {OFFSET(gpmc_a4), MODE(2)}, /* RGMII1_TD1 */
67 {OFFSET(gpmc_a5), MODE(2)}, /* RGMII1_TD0 */
[all …]
|
| /openbmc/u-boot/board/compulab/cm_t335/ |
| H A D | mux.c | 17 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
18 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
23 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
24 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
26 {OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN)},
55 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
57 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
58 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
59 {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
60 {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
[all …]
|
| /openbmc/u-boot/board/silica/pengwyn/ |
| H A D | mux.c | 18 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
26 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
28 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
48 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
49 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
50 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
51 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
52 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
53 {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
56 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
[all …]
|
| /openbmc/u-boot/board/tcl/sl50/ |
| H A D | mux.c | 18 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
30 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
77 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
79 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
85 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
87 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
94 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
96 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
97 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
98 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
[all …]
|
| /openbmc/u-boot/board/phytec/pcm051/ |
| H A D | mux.c | 26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
45 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
47 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
56 {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
59 {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
66 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
68 {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
69 {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
74 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
97 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
[all …]
|
| /openbmc/u-boot/board/isee/igep003x/ |
| H A D | mux.c | 24 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
50 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
52 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
53 {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
59 {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
60 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
62 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
63 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
64 {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
65 {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
[all …]
|
| /openbmc/u-boot/board/gumstix/pepper/ |
| H A D | mux.c | 34 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
36 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
41 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
43 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
44 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
45 {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
46 {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
49 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
54 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
55 {OFFSET(rmii1_refclk), MODE(7) | RXACTIVE}, /* ETH_INT */
[all …]
|
| /openbmc/u-boot/board/grinn/chiliboard/ |
| H A D | board.c | 33 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
42 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
48 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
49 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
50 {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
51 {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
52 {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
53 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
54 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
56 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
[all …]
|
| /openbmc/u-boot/board/eets/pdu001/ |
| H A D | mux.c | 19 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
20 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
25 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
26 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
32 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
37 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
38 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
44 {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
50 {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
55 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
[all …]
|
| /openbmc/u-boot/arch/arm/mach-omap2/am33xx/ |
| H A D | chilisom.c | 29 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
31 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
37 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
38 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
39 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
40 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
47 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
48 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
49 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
50 {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
[all …]
|
| /openbmc/u-boot/scripts/ |
| H A D | coccicheck | 96 if [ "$MODE" = "" ] ; then
103 MODE="report"
106 if [ "$MODE" = "chain" ] ; then
111 elif [ "$MODE" = "report" -o "$MODE" = "org" ] ; then
206 if [ "$MODE" = "patch" ] ; then
208 elif [ "$MODE" = "report" ] ; then
210 elif [ "$MODE" = "context" ] ; then
212 elif [ "$MODE" = "org" ] ; then
230 if [ "$MODE" = "chain" ] ; then
239 elif [ "$MODE" = "rep+ctxt" ] ; then
[all …]
|
| /openbmc/linux/scripts/ |
| H A D | coccicheck | 115 if [ "$MODE" = "" ] ; then
122 MODE="report"
125 if [ "$MODE" = "chain" ] ; then
130 elif [ "$MODE" = "report" -o "$MODE" = "org" ] ; then
222 if [ "$MODE" = "patch" ] ; then
224 elif [ "$MODE" = "report" ] ; then
226 elif [ "$MODE" = "context" ] ; then
228 elif [ "$MODE" = "org" ] ; then
246 if [ "$MODE" = "chain" ] ; then
255 elif [ "$MODE" = "rep+ctxt" ] ; then
[all …]
|