Lines Matching refs:MODE
25 {OFFSET(pincntl70), PULLUP_EN | MODE(0x01)}, /* UART0_RXD */
26 {OFFSET(pincntl71), PULLUP_EN | MODE(0x01)}, /* UART0_TXD */
31 {OFFSET(pincntl1), PULLUP_EN | MODE(0x01)}, /* SD1_CLK */
32 {OFFSET(pincntl2), PULLUP_EN | MODE(0x01)}, /* SD1_CMD */
33 {OFFSET(pincntl3), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[0] */
34 {OFFSET(pincntl4), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[1] */
35 {OFFSET(pincntl5), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[2] */
36 {OFFSET(pincntl6), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[3] */
37 {OFFSET(pincntl74), PULLUP_EN | MODE(0x40)}, /* SD1_POW */
38 {OFFSET(pincntl75), MODE(0x40)}, /* SD1_SDWP */
39 {OFFSET(pincntl80), PULLUP_EN | MODE(0x02)}, /* SD1_SDCD */
44 {OFFSET(pincntl232), MODE(0x01)}, /* EMAC_RMREFCLK */
45 {OFFSET(pincntl233), PULLUP_EN | MODE(0x01)}, /* MDCLK */
46 {OFFSET(pincntl234), PULLUP_EN | MODE(0x01)}, /* MDIO */
47 {OFFSET(pincntl235), MODE(0x01)}, /* EMAC[0]_MTCLK */
48 {OFFSET(pincntl236), MODE(0x01)}, /* EMAC[0]_MCOL */
49 {OFFSET(pincntl237), MODE(0x01)}, /* EMAC[0]_MCRS */
50 {OFFSET(pincntl238), MODE(0x01)}, /* EMAC[0]_MRXER */
51 {OFFSET(pincntl239), MODE(0x01)}, /* EMAC[0]_MRCLK */
52 {OFFSET(pincntl240), MODE(0x01)}, /* EMAC[0]_MRXD[0] */
53 {OFFSET(pincntl241), MODE(0x01)}, /* EMAC[0]_MRXD[1] */
54 {OFFSET(pincntl242), MODE(0x01)}, /* EMAC[0]_MRXD[2] */
55 {OFFSET(pincntl243), MODE(0x01)}, /* EMAC[0]_MRXD[3] */
56 {OFFSET(pincntl244), MODE(0x01)}, /* EMAC[0]_MRXD[4] */
57 {OFFSET(pincntl245), MODE(0x01)}, /* EMAC[0]_MRXD[5] */
58 {OFFSET(pincntl246), MODE(0x01)}, /* EMAC[0]_MRXD[6] */
59 {OFFSET(pincntl247), MODE(0x01)}, /* EMAC[0]_MRXD[7] */
60 {OFFSET(pincntl248), MODE(0x01)}, /* EMAC[0]_MRXDV */
61 {OFFSET(pincntl249), MODE(0x01)}, /* EMAC[0]_GMTCLK */
62 {OFFSET(pincntl250), MODE(0x01)}, /* EMAC[0]_MTXD[0] */
63 {OFFSET(pincntl251), MODE(0x01)}, /* EMAC[0]_MTXD[1] */
64 {OFFSET(pincntl252), MODE(0x01)}, /* EMAC[0]_MTXD[2] */
65 {OFFSET(pincntl253), MODE(0x01)}, /* EMAC[0]_MTXD[3] */
66 {OFFSET(pincntl254), MODE(0x01)}, /* EMAC[0]_MTXD[4] */
67 {OFFSET(pincntl255), MODE(0x01)}, /* EMAC[0]_MTXD[5] */
68 {OFFSET(pincntl256), MODE(0x01)}, /* EMAC[0]_MTXD[6] */
69 {OFFSET(pincntl257), MODE(0x01)}, /* EMAC[0]_MTXD[7] */
70 {OFFSET(pincntl258), MODE(0x01)}, /* EMAC[0]_MTXEN */