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Searched refs:tlb_table (Results 26 – 42 of 42) sorted by relevance

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/openbmc/u-boot/board/freescale/t1040qds/
H A Dtlb.c9 struct fsl_e_tlb_entry tlb_table[] = { variable
107 int num_tlb_entries = ARRAY_SIZE(tlb_table);
/openbmc/u-boot/board/freescale/p1_p2_rdb_pc/
H A Dtlb.c9 struct fsl_e_tlb_entry tlb_table[] = { variable
110 int num_tlb_entries = ARRAY_SIZE(tlb_table);
/openbmc/u-boot/board/freescale/t102xqds/
H A Dtlb.c9 struct fsl_e_tlb_entry tlb_table[] = { variable
116 int num_tlb_entries = ARRAY_SIZE(tlb_table);
/openbmc/u-boot/board/freescale/t102xrdb/
H A Dtlb.c9 struct fsl_e_tlb_entry tlb_table[] = { variable
116 int num_tlb_entries = ARRAY_SIZE(tlb_table);
/openbmc/u-boot/board/freescale/t104xrdb/
H A Dtlb.c9 struct fsl_e_tlb_entry tlb_table[] = { variable
131 int num_tlb_entries = ARRAY_SIZE(tlb_table);
/openbmc/u-boot/board/freescale/t4rdb/
H A Dtlb.c9 struct fsl_e_tlb_entry tlb_table[] = { variable
123 int num_tlb_entries = ARRAY_SIZE(tlb_table);
/openbmc/u-boot/board/freescale/common/p_corenet/
H A Dtlb.c12 struct fsl_e_tlb_entry tlb_table[] = { variable
160 int num_tlb_entries = ARRAY_SIZE(tlb_table);
/openbmc/u-boot/board/freescale/t4qds/
H A Dtlb.c12 struct fsl_e_tlb_entry tlb_table[] = { variable
146 int num_tlb_entries = ARRAY_SIZE(tlb_table);
/openbmc/u-boot/board/freescale/t208xrdb/
H A Dtlb.c12 struct fsl_e_tlb_entry tlb_table[] = { variable
152 int num_tlb_entries = ARRAY_SIZE(tlb_table);
/openbmc/u-boot/board/freescale/t208xqds/
H A Dtlb.c12 struct fsl_e_tlb_entry tlb_table[] = { variable
152 int num_tlb_entries = ARRAY_SIZE(tlb_table);
/openbmc/u-boot/board/freescale/b4860qds/
H A Dtlb.c9 struct fsl_e_tlb_entry tlb_table[] = { variable
154 int num_tlb_entries = ARRAY_SIZE(tlb_table);
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dmmu.h537 extern struct fsl_e_tlb_entry tlb_table[];
/openbmc/qemu/tcg/sparc64/
H A Dtcg-target.c.inc1072 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
1081 /* Add the tlb_table pointer, creating the CPUTLBEntry address into R2. */
/openbmc/qemu/tcg/mips/
H A Dtcg-target.c.inc1239 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
1253 /* Add the tlb_table pointer, creating the CPUTLBEntry address. */
/openbmc/qemu/tcg/arm/
H A Dtcg-target.c.inc1425 * Add the tlb_table pointer, creating the CPUTLBEntry address in R1.
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target.c.inc1691 /* Add the tlb_table pointer, forming the CPUTLBEntry address. */
/openbmc/qemu/tcg/ppc/
H A Dtcg-target.c.inc2332 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */

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