1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2360275b3SKumar Gala /* 3360275b3SKumar Gala * Copyright 2008-2011 Freescale Semiconductor, Inc. 4360275b3SKumar Gala * 5360275b3SKumar Gala * (C) Copyright 2000 6360275b3SKumar Gala * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7360275b3SKumar Gala */ 8360275b3SKumar Gala 9360275b3SKumar Gala #include <common.h> 10360275b3SKumar Gala #include <asm/mmu.h> 11360275b3SKumar Gala 12360275b3SKumar Gala struct fsl_e_tlb_entry tlb_table[] = { 13360275b3SKumar Gala /* TLB 0 - for temp stack in cache */ 14360275b3SKumar Gala SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 15360275b3SKumar Gala CONFIG_SYS_INIT_RAM_ADDR_PHYS, 16360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 17360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 18360275b3SKumar Gala SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 19360275b3SKumar Gala CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 20360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 21360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 22360275b3SKumar Gala SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 23360275b3SKumar Gala CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 24360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 25360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 26360275b3SKumar Gala SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 27360275b3SKumar Gala CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 28360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 29360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 30f8bc7bb5SKumar Gala #ifdef CPLD_BASE 31f8bc7bb5SKumar Gala SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS, 32f8bc7bb5SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 33f8bc7bb5SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 34f8bc7bb5SKumar Gala #endif 35360275b3SKumar Gala 36f8bc7bb5SKumar Gala #ifdef PIXIS_BASE 37360275b3SKumar Gala SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS, 38360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 39360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 0), 40f8bc7bb5SKumar Gala #endif 41360275b3SKumar Gala 42360275b3SKumar Gala /* TLB 1 */ 43360275b3SKumar Gala /* *I*** - Covers boot page */ 44360275b3SKumar Gala #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 45467a40dfSAneesh Bansal 46467a40dfSAneesh Bansal #if !defined(CONFIG_SECURE_BOOT) 47360275b3SKumar Gala /* 48360275b3SKumar Gala * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the 49360275b3SKumar Gala * SRAM is at 0xfff00000, it covered the 0xfffff000. 50360275b3SKumar Gala */ 51360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 52360275b3SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 53360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_1M, 1), 54467a40dfSAneesh Bansal #else 55467a40dfSAneesh Bansal /* 56467a40dfSAneesh Bansal * *I*G - L3SRAM. When L3 is used as 1M SRAM, in case of Secure Boot 57467a40dfSAneesh Bansal * the physical address of the SRAM is at CONFIG_SYS_INIT_L3_ADDR, 58467a40dfSAneesh Bansal * and virtual address is CONFIG_SYS_MONITOR_BASE 59467a40dfSAneesh Bansal */ 60467a40dfSAneesh Bansal 61467a40dfSAneesh Bansal SET_TLB_ENTRY(1, CONFIG_SYS_MONITOR_BASE & 0xfff00000, 62467a40dfSAneesh Bansal CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, 63467a40dfSAneesh Bansal MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 64467a40dfSAneesh Bansal 0, 0, BOOKE_PAGESZ_1M, 1), 65467a40dfSAneesh Bansal #endif 66467a40dfSAneesh Bansal 67461632bdSLiu Gang #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 68292dc6c5SLiu Gang /* 69461632bdSLiu Gang * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the 70292dc6c5SLiu Gang * space is at 0xfff00000, it covered the 0xfffff000. 71292dc6c5SLiu Gang */ 72461632bdSLiu Gang SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, 73461632bdSLiu Gang CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, 74292dc6c5SLiu Gang MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 75292dc6c5SLiu Gang 0, 0, BOOKE_PAGESZ_1M, 1), 76360275b3SKumar Gala #else 77360275b3SKumar Gala SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 78360275b3SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 79360275b3SKumar Gala 0, 0, BOOKE_PAGESZ_4K, 1), 80360275b3SKumar Gala #endif 81360275b3SKumar Gala 82360275b3SKumar Gala /* *I*G* - CCSRBAR */ 83360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 84360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 85360275b3SKumar Gala 0, 1, BOOKE_PAGESZ_16M, 1), 86360275b3SKumar Gala 87360275b3SKumar Gala /* *I*G* - Flash, localbus */ 88360275b3SKumar Gala /* This will be changed to *I*G* after relocation to RAM. */ 89360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 90360275b3SKumar Gala MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 91360275b3SKumar Gala 0, 2, BOOKE_PAGESZ_256M, 1), 92360275b3SKumar Gala 93360275b3SKumar Gala /* *I*G* - PCI */ 94360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 95360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 96360275b3SKumar Gala 0, 3, BOOKE_PAGESZ_1G, 1), 97360275b3SKumar Gala 98360275b3SKumar Gala /* *I*G* - PCI */ 99360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, 100360275b3SKumar Gala CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, 101360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 102360275b3SKumar Gala 0, 4, BOOKE_PAGESZ_256M, 1), 103360275b3SKumar Gala 104360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, 105360275b3SKumar Gala CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, 106360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 107360275b3SKumar Gala 0, 5, BOOKE_PAGESZ_256M, 1), 108360275b3SKumar Gala 109360275b3SKumar Gala /* *I*G* - PCI I/O */ 110360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 111360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 112360275b3SKumar Gala 0, 6, BOOKE_PAGESZ_256K, 1), 113360275b3SKumar Gala 114360275b3SKumar Gala /* Bman/Qman */ 115360275b3SKumar Gala #ifdef CONFIG_SYS_BMAN_MEM_PHYS 116360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 117360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 118360275b3SKumar Gala 0, 9, BOOKE_PAGESZ_1M, 1), 119360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, 120360275b3SKumar Gala CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, 121360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 122360275b3SKumar Gala 0, 10, BOOKE_PAGESZ_1M, 1), 123360275b3SKumar Gala #endif 124360275b3SKumar Gala #ifdef CONFIG_SYS_QMAN_MEM_PHYS 125360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 126360275b3SKumar Gala MAS3_SW|MAS3_SR, 0, 127360275b3SKumar Gala 0, 11, BOOKE_PAGESZ_1M, 1), 128360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, 129360275b3SKumar Gala CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, 130360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 131360275b3SKumar Gala 0, 12, BOOKE_PAGESZ_1M, 1), 132360275b3SKumar Gala #endif 133360275b3SKumar Gala #ifdef CONFIG_SYS_DCSRBAR_PHYS 134360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 135360275b3SKumar Gala MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 136360275b3SKumar Gala 0, 13, BOOKE_PAGESZ_4M, 1), 137360275b3SKumar Gala #endif 138360275b3SKumar Gala #ifdef CONFIG_SYS_NAND_BASE 139360275b3SKumar Gala /* 140360275b3SKumar Gala * *I*G - NAND 141360275b3SKumar Gala * entry 14 and 15 has been used hard coded, they will be disabled 142360275b3SKumar Gala * in cpu_init_f, so we use entry 16 for nand. 143360275b3SKumar Gala */ 144360275b3SKumar Gala SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 145360275b3SKumar Gala MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 146360275b3SKumar Gala 0, 16, BOOKE_PAGESZ_1M, 1), 147360275b3SKumar Gala #endif 148461632bdSLiu Gang #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 1493f1af81bSLiu Gang /* 150461632bdSLiu Gang * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for 151461632bdSLiu Gang * fetching ucode and ENV from master 1523f1af81bSLiu Gang */ 153461632bdSLiu Gang SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, 154461632bdSLiu Gang CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, 1553f1af81bSLiu Gang MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 1563f1af81bSLiu Gang 0, 17, BOOKE_PAGESZ_1M, 1), 1573f1af81bSLiu Gang #endif 158360275b3SKumar Gala }; 159360275b3SKumar Gala 160360275b3SKumar Gala int num_tlb_entries = ARRAY_SIZE(tlb_table); 161