1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2ee52b188SYork Sun /* 3ee52b188SYork Sun * Copyright 2008-2012 Freescale Semiconductor, Inc. 4ee52b188SYork Sun * 5ee52b188SYork Sun * (C) Copyright 2000 6ee52b188SYork Sun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7ee52b188SYork Sun */ 8ee52b188SYork Sun 9ee52b188SYork Sun #include <common.h> 10ee52b188SYork Sun #include <asm/mmu.h> 11ee52b188SYork Sun 12ee52b188SYork Sun struct fsl_e_tlb_entry tlb_table[] = { 13ee52b188SYork Sun /* TLB 0 - for temp stack in cache */ 14ee52b188SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 15ee52b188SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS, 16ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 17ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 18ee52b188SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 19ee52b188SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 20ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 21ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 22ee52b188SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 23ee52b188SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 24ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 25ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 26ee52b188SYork Sun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 27ee52b188SYork Sun CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 28ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 29ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_4K, 0), 30ee52b188SYork Sun 31ee52b188SYork Sun /* TLB 1 */ 32ee52b188SYork Sun /* *I*** - Covers boot page */ 33ee52b188SYork Sun #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 34ee52b188SYork Sun /* 35ee52b188SYork Sun * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the 36ee52b188SYork Sun * SRAM is at 0xfff00000, it covered the 0xfffff000. 37ee52b188SYork Sun */ 38ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 39ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 40ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_1M, 1), 4169fdf900SLiu Gang #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 4269fdf900SLiu Gang /* 4369fdf900SLiu Gang * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the 4469fdf900SLiu Gang * space is at 0xfff00000, it covered the 0xfffff000. 4569fdf900SLiu Gang */ 4669fdf900SLiu Gang SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, 4769fdf900SLiu Gang CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, 4869fdf900SLiu Gang MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 4969fdf900SLiu Gang 0, 0, BOOKE_PAGESZ_1M, 1), 50ee52b188SYork Sun #else 51ee52b188SYork Sun SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 52ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 53ee52b188SYork Sun 0, 0, BOOKE_PAGESZ_4K, 1), 54ee52b188SYork Sun #endif 55ee52b188SYork Sun 56ee52b188SYork Sun /* *I*G* - CCSRBAR */ 57ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 58ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 59ee52b188SYork Sun 0, 1, BOOKE_PAGESZ_16M, 1), 60ee52b188SYork Sun 61ee52b188SYork Sun /* *I*G* - Flash, localbus */ 62ee52b188SYork Sun /* This will be changed to *I*G* after relocation to RAM. */ 63ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 64ee52b188SYork Sun MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 65ee52b188SYork Sun 0, 2, BOOKE_PAGESZ_256M, 1), 66b6036993SShaohui Xie #ifndef CONFIG_SPL_BUILD 67ee52b188SYork Sun /* *I*G* - PCI */ 68ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 69ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 70ee52b188SYork Sun 0, 3, BOOKE_PAGESZ_1G, 1), 71ee52b188SYork Sun 72ee52b188SYork Sun /* *I*G* - PCI */ 73ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, 74ee52b188SYork Sun CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, 75ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 76ee52b188SYork Sun 0, 4, BOOKE_PAGESZ_256M, 1), 77ee52b188SYork Sun 78ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, 79ee52b188SYork Sun CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, 80ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 81ee52b188SYork Sun 0, 5, BOOKE_PAGESZ_256M, 1), 82ee52b188SYork Sun 83ee52b188SYork Sun /* *I*G* - PCI I/O */ 84ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 85ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 86ee52b188SYork Sun 0, 6, BOOKE_PAGESZ_256K, 1), 87ee52b188SYork Sun 88ee52b188SYork Sun /* Bman/Qman */ 89ee52b188SYork Sun #ifdef CONFIG_SYS_BMAN_MEM_PHYS 90ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 91ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 92ee52b188SYork Sun 0, 9, BOOKE_PAGESZ_16M, 1), 93ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, 94ee52b188SYork Sun CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, 95ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 96ee52b188SYork Sun 0, 10, BOOKE_PAGESZ_16M, 1), 97ee52b188SYork Sun #endif 98ee52b188SYork Sun #ifdef CONFIG_SYS_QMAN_MEM_PHYS 99ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 100ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, 0, 101ee52b188SYork Sun 0, 11, BOOKE_PAGESZ_16M, 1), 102ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, 103ee52b188SYork Sun CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, 104ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 105ee52b188SYork Sun 0, 12, BOOKE_PAGESZ_16M, 1), 106ee52b188SYork Sun #endif 107b6036993SShaohui Xie #endif 108ee52b188SYork Sun #ifdef CONFIG_SYS_DCSRBAR_PHYS 109ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 110ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 11149e946cbSStephen George 0, 13, BOOKE_PAGESZ_32M, 1), 112ee52b188SYork Sun #endif 113ee52b188SYork Sun #ifdef CONFIG_SYS_NAND_BASE 114ee52b188SYork Sun /* 115ee52b188SYork Sun * *I*G - NAND 116ee52b188SYork Sun * entry 14 and 15 has been used hard coded, they will be disabled 117ee52b188SYork Sun * in cpu_init_f, so we use entry 16 for nand. 118ee52b188SYork Sun */ 119ee52b188SYork Sun SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 120ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 121ac13eb5dSPrabhakar Kushwaha 0, 16, BOOKE_PAGESZ_64K, 1), 122ee52b188SYork Sun #endif 1231cb19fbbSYork Sun #ifdef QIXIS_BASE_PHYS 124ee52b188SYork Sun SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, 125ee52b188SYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 126ee52b188SYork Sun 0, 17, BOOKE_PAGESZ_4K, 1), 1271cb19fbbSYork Sun #endif 12869fdf900SLiu Gang #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 12969fdf900SLiu Gang /* 13069fdf900SLiu Gang * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for 13169fdf900SLiu Gang * fetching ucode and ENV from master 13269fdf900SLiu Gang */ 13369fdf900SLiu Gang SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, 13469fdf900SLiu Gang CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, 13569fdf900SLiu Gang MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 13669fdf900SLiu Gang 0, 18, BOOKE_PAGESZ_1M, 1), 13769fdf900SLiu Gang #endif 138ee52b188SYork Sun 139b6036993SShaohui Xie #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) 140b6036993SShaohui Xie SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 141316f0d0fSYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 142b6036993SShaohui Xie 0, 19, BOOKE_PAGESZ_2G, 1) 143b6036993SShaohui Xie #endif 144ee52b188SYork Sun }; 145ee52b188SYork Sun 146ee52b188SYork Sun int num_tlb_entries = ARRAY_SIZE(tlb_table); 147