1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2062ef1a6SPriyanka Jain /* 3062ef1a6SPriyanka Jain * Copyright 2013 Freescale Semiconductor, Inc. 4062ef1a6SPriyanka Jain */ 5062ef1a6SPriyanka Jain 6062ef1a6SPriyanka Jain #include <common.h> 7062ef1a6SPriyanka Jain #include <asm/mmu.h> 8062ef1a6SPriyanka Jain 9062ef1a6SPriyanka Jain struct fsl_e_tlb_entry tlb_table[] = { 10062ef1a6SPriyanka Jain /* TLB 0 - for temp stack in cache */ 11062ef1a6SPriyanka Jain SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 12062ef1a6SPriyanka Jain CONFIG_SYS_INIT_RAM_ADDR_PHYS, 13062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 14062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_4K, 0), 15062ef1a6SPriyanka Jain SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 16062ef1a6SPriyanka Jain CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 17062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 18062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_4K, 0), 19062ef1a6SPriyanka Jain SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 20062ef1a6SPriyanka Jain CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 21062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 22062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_4K, 0), 23062ef1a6SPriyanka Jain SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 24062ef1a6SPriyanka Jain CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 25062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 26062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_4K, 0), 27062ef1a6SPriyanka Jain 28062ef1a6SPriyanka Jain /* TLB 1 */ 29062ef1a6SPriyanka Jain /* *I*** - Covers boot page */ 30aa36c84eSSumit Garg #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \ 31aa36c84eSSumit Garg !defined(CONFIG_SECURE_BOOT) 32062ef1a6SPriyanka Jain /* 33062ef1a6SPriyanka Jain * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the 34062ef1a6SPriyanka Jain * SRAM is at 0xfffc0000, it covered the 0xfffff000. 35062ef1a6SPriyanka Jain */ 36062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 37062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 38062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_256K, 1), 39aa36c84eSSumit Garg 40aa36c84eSSumit Garg #elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD) 41aa36c84eSSumit Garg /* 42aa36c84eSSumit Garg * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot 43aa36c84eSSumit Garg * the physical address of the SRAM is at 0xbffc0000, 44aa36c84eSSumit Garg * and virtual address is 0xfffc0000 45aa36c84eSSumit Garg */ 46aa36c84eSSumit Garg 47aa36c84eSSumit Garg SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR, 48aa36c84eSSumit Garg CONFIG_SYS_INIT_L3_ADDR, 49aa36c84eSSumit Garg MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 50aa36c84eSSumit Garg 0, 0, BOOKE_PAGESZ_256K, 1), 51062ef1a6SPriyanka Jain #else 52062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 53062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 54062ef1a6SPriyanka Jain 0, 0, BOOKE_PAGESZ_4K, 1), 55062ef1a6SPriyanka Jain #endif 56062ef1a6SPriyanka Jain 57062ef1a6SPriyanka Jain /* *I*G* - CCSRBAR */ 58062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 59062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 60062ef1a6SPriyanka Jain 0, 1, BOOKE_PAGESZ_16M, 1), 61062ef1a6SPriyanka Jain 62062ef1a6SPriyanka Jain /* *I*G* - Flash, localbus */ 63062ef1a6SPriyanka Jain /* This will be changed to *I*G* after relocation to RAM. */ 64062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 65062ef1a6SPriyanka Jain MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 66062ef1a6SPriyanka Jain 0, 2, BOOKE_PAGESZ_256M, 1), 67062ef1a6SPriyanka Jain 6818c01445SPrabhakar Kushwaha #ifndef CONFIG_SPL_BUILD 69062ef1a6SPriyanka Jain /* *I*G* - PCI */ 70062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 71062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 72062ef1a6SPriyanka Jain 0, 3, BOOKE_PAGESZ_1G, 1), 73062ef1a6SPriyanka Jain 74062ef1a6SPriyanka Jain /* *I*G* - PCI I/O */ 75062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 76062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 77062ef1a6SPriyanka Jain 0, 4, BOOKE_PAGESZ_256K, 1), 78062ef1a6SPriyanka Jain 79062ef1a6SPriyanka Jain /* Bman/Qman */ 80062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_BMAN_MEM_PHYS 81062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 82062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 83062ef1a6SPriyanka Jain 0, 5, BOOKE_PAGESZ_16M, 1), 84062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, 85062ef1a6SPriyanka Jain CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, 86062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 87062ef1a6SPriyanka Jain 0, 6, BOOKE_PAGESZ_16M, 1), 88062ef1a6SPriyanka Jain #endif 89062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_QMAN_MEM_PHYS 90062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 91062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, 0, 92062ef1a6SPriyanka Jain 0, 7, BOOKE_PAGESZ_16M, 1), 93062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, 94062ef1a6SPriyanka Jain CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, 95062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 96062ef1a6SPriyanka Jain 0, 8, BOOKE_PAGESZ_16M, 1), 97062ef1a6SPriyanka Jain #endif 9818c01445SPrabhakar Kushwaha #endif 99062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_DCSRBAR_PHYS 100062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 101062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 102062ef1a6SPriyanka Jain 0, 9, BOOKE_PAGESZ_4M, 1), 103062ef1a6SPriyanka Jain #endif 104062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_NAND_BASE 105062ef1a6SPriyanka Jain /* 106062ef1a6SPriyanka Jain * *I*G - NAND 107062ef1a6SPriyanka Jain * entry 14 and 15 has been used hard coded, they will be disabled 108062ef1a6SPriyanka Jain * in cpu_init_f, so we use entry 16 for nand. 109062ef1a6SPriyanka Jain */ 110062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 111062ef1a6SPriyanka Jain MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 112062ef1a6SPriyanka Jain 0, 10, BOOKE_PAGESZ_64K, 1), 113062ef1a6SPriyanka Jain #endif 114062ef1a6SPriyanka Jain #ifdef CONFIG_SYS_CPLD_BASE 115062ef1a6SPriyanka Jain SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, 116062ef1a6SPriyanka Jain MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 117062ef1a6SPriyanka Jain 0, 11, BOOKE_PAGESZ_256K, 1), 118062ef1a6SPriyanka Jain #endif 11918c01445SPrabhakar Kushwaha 12018c01445SPrabhakar Kushwaha #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) 12118c01445SPrabhakar Kushwaha SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 122316f0d0fSYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 12318c01445SPrabhakar Kushwaha 0, 12, BOOKE_PAGESZ_1G, 1), 12418c01445SPrabhakar Kushwaha SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, 12518c01445SPrabhakar Kushwaha CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, 126316f0d0fSYork Sun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 12718c01445SPrabhakar Kushwaha 0, 13, BOOKE_PAGESZ_1G, 1) 12818c01445SPrabhakar Kushwaha #endif 129062ef1a6SPriyanka Jain }; 130062ef1a6SPriyanka Jain 131062ef1a6SPriyanka Jain int num_tlb_entries = ARRAY_SIZE(tlb_table); 132