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Searched refs:stage (Results 276 – 300 of 446) sorted by relevance

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/openbmc/linux/Documentation/locking/
H A Dfutex-requeue-pi.rst121 the lock can be acquired at this stage as well, if so, the next
/openbmc/openbmc/meta-arm/meta-arm-bsp/documentation/corstone1000/
H A Dchange-log.rst92 - Use TF-M BL1 code as the ROM code instead of MCUboot (the next stage bootloader BL2 remains to be…
H A Dsoftware-architecture.rst188 block to get the information on the boot bank. In the successful trial stage,
190 regular. Any failure in the trial stage or system hangs leads to a system
/openbmc/openbmc/poky/meta/classes-recipe/
H A Doverlayfs.bbclass121 # we need to generate file names early during parsing stage
/openbmc/linux/Documentation/admin-guide/media/
H A Dvisl.rst14 been upstreamed yet. This can reveal bugs at an early stage.
/openbmc/linux/Documentation/process/
H A D3.Early-stage.rst3 Early-stage planning
176 One discouraging thing which can happen at this stage is not a hostile
/openbmc/linux/lib/zstd/compress/
H A Dzstd_compress.c1851 zc->stage = ZSTDcs_init; in ZSTD_resetCCtx_internal()
2136 RETURN_ERROR_IF(srcCCtx->stage!=ZSTDcs_init, stage_wrong, in ZSTD_copyCCtx_internal()
3916 if (lastFrameChunk && (op>ostart)) cctx->stage = ZSTDcs_ending; in ZSTD_compress_frameChunk()
4006 RETURN_ERROR_IF(cctx->stage != ZSTDcs_init, stage_wrong, in ZSTD_referenceExternalSequences()
4029 cctx->stage, (unsigned)srcSize); in ZSTD_compressContinue_internal()
4030 RETURN_ERROR_IF(cctx->stage==ZSTDcs_created, stage_wrong, in ZSTD_compressContinue_internal()
4033 if (frame && (cctx->stage==ZSTDcs_init)) { in ZSTD_compressContinue_internal()
4040 cctx->stage = ZSTDcs_ongoing; in ZSTD_compressContinue_internal()
4505 if (cctx->stage == ZSTDcs_init) { in ZSTD_writeEpilogue()
4510 cctx->stage = ZSTDcs_ongoing; in ZSTD_writeEpilogue()
[all …]
/openbmc/linux/Documentation/bpf/
H A Ds390.rst150 /debootstrap/debootstrap --second-stage
/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg129 # bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
H A Dkwbimage-lsxhl.cfg129 # bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
/openbmc/qemu/docs/system/riscv/
H A Dmicrochip-icicle-kit.rst34 HSS loads the second stage bootloader U-Boot from an SD card. Then a kernel
/openbmc/qemu/docs/system/arm/
H A Demulation.rst107 - FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dcs35l36.txt74 Configures the signal threshold at which the PWM output stage enters
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/ostree/
H A Dostree_2024.5.bb114 # do_configure stage so we do depend on it
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1293 wr_supp_res[if_id][bus_id].stage = PHASE_SHIFT; in ddr3_tip_wl_supp_align_phase_shift()
1421 wr_supp_res[if_id][bus_id].stage = edge_offset; in ddr3_tip_xsb_compare_test()
1634 [bus_id].stage)); in ddr3_tip_print_wl_supp_result()
/openbmc/linux/Documentation/livepatch/
H A Dlivepatch.rst316 implementation of the patched functions at this stage.
327 ftrace handler is registered\ [#]_. This stage is indicated by a value of '1'
371 the previously enabled patch or even the original one. This stage is
/openbmc/linux/Documentation/accel/qaic/
H A Daic100.rst145 the SBL stage. SBL performs a number of operations:
157 The QSM uses MHI to notify the host that the device has entered the QSM stage
484 multi-stage recovery process is then used to cleanup both sides, and get the
/openbmc/linux/drivers/dma/sh/
H A Drcar-dmac.c1495 unsigned int stage; in rcar_dmac_isr_desc_stage_end() local
1507 stage = (rcar_dmac_chan_read(chan, RCAR_DMACHCRB) & in rcar_dmac_isr_desc_stage_end()
1509 rcar_dmac_chan_write(chan, RCAR_DMADPCR, RCAR_DMADPCR_DIPT(stage)); in rcar_dmac_isr_desc_stage_end()
/openbmc/linux/fs/f2fs/
H A Dgc.c607 int stage = 0; in atssr_lookup_victim() local
617 if (stage++ == 0) in atssr_lookup_victim()
647 ve = rb_entry(stage == 0 ? rb_prev(&ve->rb_node) : in atssr_lookup_victim()
653 if (stage++ == 0) in atssr_lookup_victim()
/openbmc/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_main.c5432 struct hclge_fd_key_cfg *stage; in hclge_set_fd_key_config() local
5439 stage = &hdev->fd_cfg.key_cfg[stage_num]; in hclge_set_fd_key_config()
5440 req->stage = stage_num; in hclge_set_fd_key_config()
5441 req->key_select = stage->key_sel; in hclge_set_fd_key_config()
5442 req->inner_sipv6_word_en = stage->inner_sipv6_word_en; in hclge_set_fd_key_config()
5443 req->inner_dipv6_word_en = stage->inner_dipv6_word_en; in hclge_set_fd_key_config()
5444 req->outer_sipv6_word_en = stage->outer_sipv6_word_en; in hclge_set_fd_key_config()
5445 req->outer_dipv6_word_en = stage->outer_dipv6_word_en; in hclge_set_fd_key_config()
5446 req->tuple_mask = cpu_to_le32(~stage->tuple_active); in hclge_set_fd_key_config()
5549 req1->stage = stage; in hclge_fd_tcam_config()
[all …]
/openbmc/linux/fs/btrfs/
H A Dtree-log.c300 int stage; member
2419 wc->stage == LOG_WALK_REPLAY_INODES) { in replay_one_buffer()
2503 wc->stage == LOG_WALK_REPLAY_DIR_INDEX) { in replay_one_buffer()
2510 if (wc->stage < LOG_WALK_REPLAY_ALL) in replay_one_buffer()
7141 .stage = LOG_WALK_PIN_ONLY, in btrfs_recover_log_trees()
7231 if (!ret && wc.stage == LOG_WALK_REPLAY_ALL) { in btrfs_recover_log_trees()
7238 if (!ret && wc.stage == LOG_WALK_REPLAY_ALL) { in btrfs_recover_log_trees()
7273 wc.stage = LOG_WALK_REPLAY_INODES; in btrfs_recover_log_trees()
7277 if (wc.stage < LOG_WALK_REPLAY_ALL) { in btrfs_recover_log_trees()
7278 wc.stage++; in btrfs_recover_log_trees()
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg119 # bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
/openbmc/openbmc/poky/meta/classes/
H A Dgo-vendor.bbclass8 # a network (proxy) connection ahead of the compile stage. This contradicts
/openbmc/linux/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-qcom.c225 (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && in qcom_adreno_smmu_init_context()
/openbmc/linux/drivers/iommu/arm/arm-smmu-v3/
H A Darm-smmu-v3.h725 enum arm_smmu_domain_stage stage; member

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