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Searched refs:reg_offset (Results 176 – 200 of 393) sorted by relevance

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/openbmc/linux/drivers/pinctrl/samsung/
H A Dpinctrl-samsung.c405 data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]); in samsung_pinmux_setup()
408 writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]); in samsung_pinmux_setup()
452 cfg_reg = type->reg_offset[cfg_type]; in samsung_pinconf_rw()
551 data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]); in samsung_gpio_set_value()
555 writel(data, reg + type->reg_offset[PINCFG_TYPE_DAT]); in samsung_gpio_set_value()
579 data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]); in samsung_gpio_get()
603 + type->reg_offset[PINCFG_TYPE_FUNC]; in samsung_gpio_set_direction()
1203 const u8 *offs = bank->type->reg_offset; in samsung_pinctrl_suspend()
1256 const u8 *offs = bank->type->reg_offset; in samsung_pinctrl_resume()
/openbmc/linux/drivers/crypto/hisilicon/zip/
H A Dzip_main.c337 .reg_offset = HZIP_CORE_DFX_BASE,
340 .reg_offset = HZIP_CORE_DFX_COMP_0,
343 .reg_offset = HZIP_CORE_DFX_COMP_1,
346 .reg_offset = HZIP_CORE_DFX_DECOMP_0,
349 .reg_offset = HZIP_CORE_DFX_DECOMP_1,
352 .reg_offset = HZIP_CORE_DFX_DECOMP_2,
355 .reg_offset = HZIP_CORE_DFX_DECOMP_3,
358 .reg_offset = HZIP_CORE_DFX_DECOMP_4,
361 .reg_offset = HZIP_CORE_DFX_DECOMP_5,
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dclock.h101 int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
/openbmc/u-boot/drivers/net/
H A Dsh_eth.h606 const u16 *reg_offset = sh_eth_offset_gigabit; in sh_eth_reg_addr() local
608 const u16 *reg_offset = sh_eth_offset_fast_sh4; in sh_eth_reg_addr()
612 return (unsigned long)port->iobase + reg_offset[enum_index]; in sh_eth_reg_addr()
H A Dmvgbe.c348 u32 reg_offset; in port_uc_addr() local
355 reg_offset = uc_nibble % 4; in port_uc_addr()
364 unicast_reg &= (0xFF << (8 * reg_offset)); in port_uc_addr()
370 unicast_reg &= (0xFF << (8 * reg_offset)); in port_uc_addr()
371 unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset)); in port_uc_addr()
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dnbio_v7_2.c53 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); in nbio_v7_2_remap_hdp_registers()
55 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); in nbio_v7_2_remap_hdp_registers()
407 adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, in nbio_v7_2_init_registers()
H A Dnbio_v6_1.c59 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); in nbio_v6_1_remap_hdp_registers()
61 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); in nbio_v6_1_remap_hdp_registers()
281 adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, in nbio_v6_1_init_registers()
H A Dvi.c747 u32 sh_num, u32 reg_offset) in vi_get_register_value() argument
754 switch (reg_offset) { in vi_get_register_value()
769 val = RREG32(reg_offset); in vi_get_register_value()
778 switch (reg_offset) { in vi_get_register_value()
815 idx = (reg_offset - mmGB_TILE_MODE0); in vi_get_register_value()
833 idx = (reg_offset - mmGB_MACROTILE_MODE0); in vi_get_register_value()
836 return RREG32(reg_offset); in vi_get_register_value()
842 u32 sh_num, u32 reg_offset, u32 *value) in vi_read_register() argument
850 if (reg_offset != vi_allowed_read_registers[i].reg_offset) in vi_read_register()
854 reg_offset); in vi_read_register()
H A Damdgpu_amdkfd_gfx_v10.h57 uint32_t *reg_offset,
H A Dgfx_v6_0.c386 u32 reg_offset, split_equal_to_row_size, *tilemode; in gfx_v6_0_tiling_mode_table_init() local
626 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()
627 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); in gfx_v6_0_tiling_mode_table_init()
832 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()
833 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); in gfx_v6_0_tiling_mode_table_init()
1056 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()
1057 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); in gfx_v6_0_tiling_mode_table_init()
1280 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()
1281 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); in gfx_v6_0_tiling_mode_table_init()
/openbmc/linux/drivers/clk/bcm/
H A Dclk-kona.c122 static inline u32 __ccu_read(struct ccu_data *ccu, u32 reg_offset) in __ccu_read() argument
124 return readl(ccu->base + reg_offset); in __ccu_read()
129 __ccu_write(struct ccu_data *ccu, u32 reg_offset, u32 reg_val) in __ccu_write() argument
131 writel(reg_val, ccu->base + reg_offset); in __ccu_write()
183 __ccu_wait_bit(struct ccu_data *ccu, u32 reg_offset, u32 bit, bool want) in __ccu_wait_bit() argument
192 val = __ccu_read(ccu, reg_offset); in __ccu_wait_bit()
199 ccu->name, reg_offset, bit, want ? "set" : "clear"); in __ccu_wait_bit()
/openbmc/linux/drivers/net/ethernet/cavium/thunder/
H A Dnicvf_ethtool.c368 u64 reg_offset; in nicvf_get_regs() local
420 reg_offset = NIC_QSET_RQ_0_7_STAT_0_1 | (1 << 3); in nicvf_get_regs()
421 p[i++] = nicvf_queue_reg_read(nic, reg_offset, q); in nicvf_get_regs()
438 reg_offset = NIC_QSET_SQ_0_7_STAT_0_1 | (1 << 3); in nicvf_get_regs()
439 p[i++] = nicvf_queue_reg_read(nic, reg_offset, q); in nicvf_get_regs()
453 reg_offset = NIC_QSET_RBDR_0_1_PREFETCH_STATUS; in nicvf_get_regs()
454 p[i++] = nicvf_queue_reg_read(nic, reg_offset, q); in nicvf_get_regs()
/openbmc/linux/drivers/power/supply/
H A Dsbs-battery.c611 int reg_offset, enum power_supply_property psp, in sbs_get_battery_property() argument
617 ret = sbs_read_word_data(client, sbs_data[reg_offset].addr); in sbs_get_battery_property()
622 if (sbs_data[reg_offset].min_value < 0) in sbs_get_battery_property()
625 if (ret >= sbs_data[reg_offset].min_value && in sbs_get_battery_property()
626 ret <= sbs_data[reg_offset].max_value) { in sbs_get_battery_property()
797 int reg_offset, enum power_supply_property psp, in sbs_get_battery_capacity() argument
810 ret = sbs_read_word_data(client, sbs_data[reg_offset].addr); in sbs_get_battery_capacity()
/openbmc/linux/include/linux/
H A Dirq.h1216 u32 val, int reg_offset) in irq_reg_writel() argument
1219 gc->reg_writel(val, gc->reg_base + reg_offset); in irq_reg_writel()
1221 writel(val, gc->reg_base + reg_offset); in irq_reg_writel()
1225 int reg_offset) in irq_reg_readl() argument
1228 return gc->reg_readl(gc->reg_base + reg_offset); in irq_reg_readl()
1230 return readl(gc->reg_base + reg_offset); in irq_reg_readl()
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dcik.c2350 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()
2352 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()
2493 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()
2494 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); in cik_tiling_mode_table_init()
2495 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()
2636 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()
2638 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()
2861 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()
2863 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()
3004 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()
[all …]
/openbmc/linux/drivers/pinctrl/mediatek/
H A Dmtk-eint.c104 unsigned int reg_offset; in mtk_eint_flip_edge() local
114 reg_offset = eint->regs->pol_clr; in mtk_eint_flip_edge()
116 reg_offset = eint->regs->pol_set; in mtk_eint_flip_edge()
117 writel(mask, reg + reg_offset); in mtk_eint_flip_edge()
/openbmc/linux/sound/soc/sof/amd/
H A Dacp-trace.c60 dtrace_params->buffer.phy_addr = stream->reg_offset; in acp_sof_trace_init()
/openbmc/linux/sound/soc/codecs/
H A Dwm8995.c1800 int reg_offset, ret; in wm8995_set_fll() local
1815 reg_offset = 0; in wm8995_set_fll()
1819 reg_offset = 0x20; in wm8995_set_fll()
1865 snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_1 + reg_offset, in wm8995_set_fll()
1870 snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_2 + reg_offset, in wm8995_set_fll()
1874 snd_soc_component_write(component, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k); in wm8995_set_fll()
1876 snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_4 + reg_offset, in wm8995_set_fll()
1880 snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_5 + reg_offset, in wm8995_set_fll()
1887 snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_1 + reg_offset, in wm8995_set_fll()
/openbmc/linux/drivers/crypto/cavium/zip/
H A Dzip_main.h68 u64 reg_offset; member
/openbmc/linux/drivers/net/ethernet/8390/
H A Dhydra.c31 #define EI_SHIFT(x) (ei_local->reg_offset[x])
161 ei_status.reg_offset = hydra_offsets; in hydra_init()
/openbmc/linux/drivers/crypto/marvell/octeontx2/
H A Dotx2_cpt_mbox_common.c67 reg_msg->reg_offset = reg; in otx2_cpt_add_read_af_reg()
92 reg_msg->reg_offset = reg; in otx2_cpt_add_write_af_reg()
/openbmc/linux/sound/pci/
H A Dvia82xx.c310 unsigned int reg_offset; member
1033 if (chip->spdif_on && viadev->reg_offset == 0x30) in snd_via8233_playback_prepare()
1044 outb(chip->playback_volume[viadev->reg_offset / 0x10][0], in snd_via8233_playback_prepare()
1046 outb(chip->playback_volume[viadev->reg_offset / 0x10][1], in snd_via8233_playback_prepare()
1174 if (chip->spdif_on && viadev->reg_offset == 0x30) { in snd_via82xx_pcm_open()
1178 } else if (chip->dxs_fixed && viadev->reg_offset < 0x40) { in snd_via82xx_pcm_open()
1182 } else if (chip->dxs_src && viadev->reg_offset < 0x40) { in snd_via82xx_pcm_open()
1248 stream = viadev->reg_offset / 0x10; in snd_via8233_playback_open()
1343 stream = viadev->reg_offset / 0x10; in snd_via8233_playback_close()
1413 chip->devs[idx].reg_offset = reg_offset; in init_viadev()
[all …]
/openbmc/linux/include/linux/platform_data/
H A Dmmc-omap.h36 u16 reg_offset; member
/openbmc/linux/drivers/clk/ti/
H A Dclkctrl.c51 u16 reg_offset; member
237 if (iter->reg_offset == clkspec->args[0] && in _ti_omap4_clkctrl_xlate()
318 clkctrl_clk->reg_offset = offset; in _ti_clkctrl_clk_register()
697 clkctrl_clk->reg_offset = reg_data->offset; in _ti_omap4_clkctrl_setup()
/openbmc/linux/drivers/soc/ti/
H A Dpruss.c311 u32 reg_offset; in pruss_clk_mux_setup() local
344 ret = of_property_read_u32(clk_mux_np, "reg", &reg_offset); in pruss_clk_mux_setup()
348 reg = pruss->cfg_base + reg_offset; in pruss_clk_mux_setup()

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