1640035a2SMahipal Challa /***********************license start************************************
2640035a2SMahipal Challa  * Copyright (c) 2003-2017 Cavium, Inc.
3640035a2SMahipal Challa  * All rights reserved.
4640035a2SMahipal Challa  *
5640035a2SMahipal Challa  * License: one of 'Cavium License' or 'GNU General Public License Version 2'
6640035a2SMahipal Challa  *
7640035a2SMahipal Challa  * This file is provided under the terms of the Cavium License (see below)
8640035a2SMahipal Challa  * or under the terms of GNU General Public License, Version 2, as
9640035a2SMahipal Challa  * published by the Free Software Foundation. When using or redistributing
10640035a2SMahipal Challa  * this file, you may do so under either license.
11640035a2SMahipal Challa  *
12640035a2SMahipal Challa  * Cavium License:  Redistribution and use in source and binary forms, with
13640035a2SMahipal Challa  * or without modification, are permitted provided that the following
14640035a2SMahipal Challa  * conditions are met:
15640035a2SMahipal Challa  *
16640035a2SMahipal Challa  *  * Redistributions of source code must retain the above copyright
17640035a2SMahipal Challa  *    notice, this list of conditions and the following disclaimer.
18640035a2SMahipal Challa  *
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25640035a2SMahipal Challa  *    used to endorse or promote products derived from this software without
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27640035a2SMahipal Challa  *
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33640035a2SMahipal Challa  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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44640035a2SMahipal Challa  ***********************license end**************************************/
45640035a2SMahipal Challa 
46640035a2SMahipal Challa #ifndef __ZIP_MAIN_H__
47640035a2SMahipal Challa #define __ZIP_MAIN_H__
48640035a2SMahipal Challa 
49640035a2SMahipal Challa #include "zip_device.h"
50640035a2SMahipal Challa #include "zip_regs.h"
51640035a2SMahipal Challa 
52640035a2SMahipal Challa /* PCI device IDs */
53640035a2SMahipal Challa #define PCI_DEVICE_ID_THUNDERX_ZIP   0xA01A
54640035a2SMahipal Challa 
55640035a2SMahipal Challa /* ZIP device BARs */
56640035a2SMahipal Challa #define PCI_CFG_ZIP_PF_BAR0   0  /* Base addr for normal regs */
57640035a2SMahipal Challa 
58640035a2SMahipal Challa /* Maximum available zip queues */
59640035a2SMahipal Challa #define ZIP_MAX_NUM_QUEUES    8
60640035a2SMahipal Challa 
61640035a2SMahipal Challa #define ZIP_128B_ALIGN        7
62640035a2SMahipal Challa 
63640035a2SMahipal Challa /* Command queue buffer size */
64640035a2SMahipal Challa #define ZIP_CMD_QBUF_SIZE     (8064 + 8)
65640035a2SMahipal Challa 
66640035a2SMahipal Challa struct zip_registers {
67640035a2SMahipal Challa 	char  *reg_name;
68640035a2SMahipal Challa 	u64   reg_offset;
69640035a2SMahipal Challa };
70640035a2SMahipal Challa 
7109ae5d37SMahipal Challa /* ZIP Compression - Decompression stats */
7209ae5d37SMahipal Challa struct zip_stats {
7309ae5d37SMahipal Challa 	atomic64_t    comp_req_submit;
7409ae5d37SMahipal Challa 	atomic64_t    comp_req_complete;
7509ae5d37SMahipal Challa 	atomic64_t    decomp_req_submit;
7609ae5d37SMahipal Challa 	atomic64_t    decomp_req_complete;
7709ae5d37SMahipal Challa 	atomic64_t    comp_in_bytes;
7809ae5d37SMahipal Challa 	atomic64_t    comp_out_bytes;
7909ae5d37SMahipal Challa 	atomic64_t    decomp_in_bytes;
8009ae5d37SMahipal Challa 	atomic64_t    decomp_out_bytes;
8109ae5d37SMahipal Challa 	atomic64_t    decomp_bad_reqs;
8209ae5d37SMahipal Challa };
8309ae5d37SMahipal Challa 
84640035a2SMahipal Challa /* ZIP Instruction Queue */
85640035a2SMahipal Challa struct zip_iq {
86640035a2SMahipal Challa 	u64        *sw_head;
87640035a2SMahipal Challa 	u64        *sw_tail;
88640035a2SMahipal Challa 	u64        *hw_tail;
89640035a2SMahipal Challa 	u64        done_cnt;
90640035a2SMahipal Challa 	u64        pend_cnt;
91640035a2SMahipal Challa 	u64        free_flag;
92640035a2SMahipal Challa 
93640035a2SMahipal Challa 	/* ZIP IQ lock */
94640035a2SMahipal Challa 	spinlock_t  lock;
95640035a2SMahipal Challa };
96640035a2SMahipal Challa 
97640035a2SMahipal Challa /* ZIP Device */
98640035a2SMahipal Challa struct zip_device {
99640035a2SMahipal Challa 	u32               index;
100640035a2SMahipal Challa 	void __iomem      *reg_base;
101640035a2SMahipal Challa 	struct pci_dev    *pdev;
102640035a2SMahipal Challa 
103640035a2SMahipal Challa 	/* Different ZIP Constants */
104640035a2SMahipal Challa 	u64               depth;
105640035a2SMahipal Challa 	u64               onfsize;
106640035a2SMahipal Challa 	u64               ctxsize;
107640035a2SMahipal Challa 
108640035a2SMahipal Challa 	struct zip_iq     iq[ZIP_MAX_NUM_QUEUES];
10909ae5d37SMahipal Challa 	struct zip_stats  stats;
110640035a2SMahipal Challa };
111640035a2SMahipal Challa 
112640035a2SMahipal Challa /* Prototypes */
113640035a2SMahipal Challa struct zip_device *zip_get_device(int node_id);
114640035a2SMahipal Challa int zip_get_node_id(void);
115640035a2SMahipal Challa void zip_reg_write(u64 val, u64 __iomem *addr);
116640035a2SMahipal Challa u64 zip_reg_read(u64 __iomem *addr);
117640035a2SMahipal Challa void zip_update_cmd_bufs(struct zip_device *zip_dev, u32 queue);
118640035a2SMahipal Challa u32 zip_load_instr(union zip_inst_s *instr, struct zip_device *zip_dev);
119640035a2SMahipal Challa 
120640035a2SMahipal Challa #endif /* ZIP_MAIN_H */
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