2328 	u32 reg_offset, split_equal_to_row_size;  in cik_tiling_mode_table_init()  local
2350 	for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)  in cik_tiling_mode_table_init()
2351 		tile[reg_offset] = 0;  in cik_tiling_mode_table_init()
2352 	for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)  in cik_tiling_mode_table_init()
2353 		macrotile[reg_offset] = 0;  in cik_tiling_mode_table_init()
2493 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)  in cik_tiling_mode_table_init()
2494 			WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);  in cik_tiling_mode_table_init()
2495 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)  in cik_tiling_mode_table_init()
2496 			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);  in cik_tiling_mode_table_init()
2636 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)  in cik_tiling_mode_table_init()
2637 			WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);  in cik_tiling_mode_table_init()
2638 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)  in cik_tiling_mode_table_init()
2639 			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);  in cik_tiling_mode_table_init()
2861 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)  in cik_tiling_mode_table_init()
2862 			WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);  in cik_tiling_mode_table_init()
2863 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)  in cik_tiling_mode_table_init()
2864 			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);  in cik_tiling_mode_table_init()
3004 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)  in cik_tiling_mode_table_init()
3005 			WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);  in cik_tiling_mode_table_init()
3006 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)  in cik_tiling_mode_table_init()
3007 			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);  in cik_tiling_mode_table_init()